SAMSUNG K9F1208X0C Technical data

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K9F1208U0C K9F1208R0C

K9F1208B0C

K9F1208X0C

FLASH MEMORY

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TO ANY INTELLECTUAL PROPERTY RIGHTS IN SAMSUNG PRODUCTS OR TECHNOLOGY. ALL INFORMATION IN THIS DOCUMENT IS PROVIDED

ON AS "AS IS" BASIS WITHOUT GUARANTEE OR WARRANTY OF ANY KIND.

1. For updates or additional information about Samsung products, contact your nearest Samsung office.

2. Samsung products are not intended for use in life support, critical care, medical, safety equipment, or similar applications where Product failure could result in loss of life or personal or physical harm, or any military or defense application, or any governmental procurement to which special terms or provisions may apply.

* Samsung Electronics reserves the right to change products or specification without notice.

K9F1208U0C K9F1208R0C

K9F1208B0C

Document Title

64M x 8 Bits NAND Flash Memory

Revision History

FLASH MEMORY

Revision No.

0.0

0.1

0.2

0.3

0.4

0.5

1.0

1.1

History

Initial issue.

2.7V part is added

Address of Read 2 is changed (A

1. Add tRPS/tRCS/tREAS parameter for status read

2. Add nWP timing guide

1. Change from tRPS/tRCS/tREAS to tRPB/tRCB/tREAB parameter for

1.8V device busy state

1. Sequential Row Read is added

1. tCRY is changed (50ns+tR(R/B) --> 5us)

1. Mode selection is modified ("CE

: Don’t care -> Fixed "Low" )

4~A7

don’t care" case)

Draft Date

Nov. 10th 2005

July 13th 2006

Aug. 1st 2006

Oct. 12th 2006

Nov. 14th 2006

Nov. 15th 2006

Dec. 28th 2006

June 18th 2007

Remark

Advance

Preliminary

Final

Note : For more detailed features and specifications including FAQ, please refer to Samsung’s Flash web site. http://www.samsung.com/Products/Semiconductor/

The attached datasheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions about device. If you have any questions, please contact the SAMSUNG branch office near you.

K9F1208U0C K9F1208R0C

K9F1208B0C

64M x 8 Bits NAND Flash Memory

PRODUCT LIST

Part Number Vcc Range Organization PKG Type

K9F1208R0C-J 1.65V ~ 1.95V

K9F1208B0C-P 2.5V ~ 2.9V TSOP1

K9F1208U0C-P

K9F1208U0C-J FBGA

FEATURES

• Voltage Supply

- 1.8V Device(K9F1208R0C) : 1.65V ~ 1.95V

- 2.7V Device(K9F1208B0C) : 2.5V ~ 2.9V

- 3.3V Device(K9F1208U0C) : 2.7V ~ 3.6V

• Organization

- Memory Cell Array : (64M + 2M) x 8bits

- Data Register : (512 + 16) x 8bits

• Automatic Program and Erase

- Page Program : (512 + 16) x 8bits

- Block Erase : (16K + 512)Bytes

• Page Read Operation

- Page Size : (512 + 16)Bytes

- Random Access : 15µs(Max.)

- Serial Page Access : 42ns(Min.)

• Fast Write Cycle Time

- Program time : 200µs(Typ.)

- Block Erase Time : 2ms(Typ.)

• Command/Address/Data Multiplexed I/O Port

• Hardware Data Protection

- Program/Erase Lockout During Power Transitions

2.7V ~ 3.6V

FLASH MEMORY

FBGA

TSOP1

• Reliable CMOS Floating-Gate Technology

- Endurance : 100K Program/Erase Cycles (with 1bit/512Byte ECC)

- Data Retention : 10 Years

• Command Register Operation

• Unique ID for Copyright Protection

• Package

- K9F1208U0C-PCB0/PIB0 : Pb-Free Package 48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

- K9F1208X0C-JCB0/JIB0: Pb-Free Package 63-Ball FBGA(8.5 x 13 x 1.2mmt)

- K9F1208B0C-PCB0/PIB0 : Pb-Free Package

48 - Pin TSOP I (12 x 20 / 0.5 mm pitch)

GENERAL DESCRIPTION

Offered in 64Mx8bits, the K9F1208X0C is 512Mbit with spare 16Mbit capacity. The device is offered in 1.8V, 2.7V and 3.3V Vcc. Its NAND cell provides the most cost-effective solutIon for the solid state mass storage market. A program operation can be performed in typical 200µs on the 528-bytes and an erase operation can be performed in typical 2ms on a 16K-bytes block. Data in the page can be read out at 42ns cycle time per byte. The I/O pins serve as the ports for address and data input/output as well as command input. The on-chip write control automates all program and erase functions including pulse repetition, where required, and internal verification and margining of data. Even the write-intensive systems can take advantage of the K9F1208X0C′s extended reliability of 100K program/erase cycles by providing ECC(Error Correcting Code) with real time mapping-out algorithm. The K9F1208X0C is an optimum solution for large nonvolatile storage applications such as solid state file storage and other portable applications requiring non-volatility.

K9F1208U0C K9F1208R0C

PIN CONFIGURATION (TSOP1)

K9F1208B0C

FLASH MEMORY

K9F1208X0C-PCB0/PIB0

N.C N.C N.C N.C N.C N.C R/B RE

CE N.C N.C Vcc Vss N.C N.C

CLE ALE

WE WP N.C N.C N.C N.C N.C

1 2 3 4 5 6 7 8

9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25

PACKAGE DIMENSIONS

48-PIN LEAD/LEAD FREE PLASTIC THIN SMALL OUT-LINE PACKAGE TYPE(I)

48 - TSOP1 - 1220AF

20.00±0.20

0.787±0.008

+0.07

-0.03

0.20

#48

N.C N.C N.C N.C I/O7 I/O6 I/O5 I/O4 N.C N.C N.C Vcc Vss N.C N.C N.C I/O3 I/O2 I/O1 I/O0 N.C N.C N.C N.C

Unit :mm/Inch

MAX

0.10

0.004

0.25 ()

0.010

+0.003

-0.001

+0.07

-0.03

0.16

0.008

0.50

0.0197

0~8°

0.45~0.75

0.018~0.030

#24

0.25

MAX

12.00

0.472

0.488

12.40

#25

1.00±0.05

0.039±0.002

1.20

TYP

0.010

18.40±0.10

0.724±0.004

+0.075

0.035 +0.003

-0.001

0.125

0.005

0.50

()

0.020

0.047

MAX

0.05

0.002

MIN

K9F1208U0C K9F1208R0C

PIN CONFIGURATION (FBGA)

K9F1208B0C

FLASH MEMORY

K9F1208X0C-JCB0/JIB0

3456 1 2

N.C N.C

N.C

N.C N.C

N.C

/RE CLE

NC NC

NC NC NC

NC NC

NCNCNC

NC NC

NCNC I/O0

I/O1NC NC VccQ I/O5 I/O7

Top View

N.C N.C

N.C

R/B/WE/CEVssALE/WP

NCNC

Vcc

VssI/O6I/O4I/O3I/O2Vss

N.C N.C

N.C

N.CN.C

K9F1208U0C K9F1208R0C

63-Ball FBGA (measured in millimeters)

K9F1208B0C

FLASH MEMORY

#A1

Top View

8.50±0.10

13.00±0.10

(Datum A)

(Datum B)

2.80

Bottom View

#A1 INDEX MARK(OPTIONAL)

8.50±0.10

0.80 x 9= 7.20

0.80 x 5= 4.00

0.80

4321

0.80

0.80 x 7= 5.60

13.00±0.10

0.80 x 11= 8.80

0.10MAX

63-∅0.45±0.05

∅

0.20

A B

Side View

13.00±0.10

2.00

0.45±0.05

0.90±0.10

0.35±0.05

K9F1208U0C K9F1208R0C

PIN DESCRIPTION

Pin Name Pin Function

0 ~ I/O7

I/O

CLE

ALE

K9F1208B0C

DATA INPUTS/OUTPUTS

The I/O pins are used to input command, address and data, and to output data during read operations. The I/ O pins float to high-z when the chip is deselected or when the outputs are disabled.

COMMAND LATCH ENABLE

The CLE input controls the activating path for commands sent to the command register. When active high, commands are latched into the command register through the I/O ports on the rising edge of the WE

ADDRESS LATCH ENABLE

The ALE input controls the activating path for address to the internal address registers. Addresses are latched on the rising edge of WE

CHIP ENABLE

The CE

input is the device selection control. When the device is in the Busy state, CE high is ignored, and the device does not return to standby mode in program or erase opertion. Regarding CE operation, refer to ’Page read’ section of Device operation .

READ ENABLE

The RE

input is the serial data-out control, and when active drives the data onto the I/O bus. Data is valid tREA after the falling edge of RE

WRITE ENABLE

The WE

input controls writes to the I/O port. Commands, address and data are latched on the rising edge of

the WE

pulse.

with ALE high.

which also increments the internal column address counter by one.

FLASH MEMORY

signal.

control during read

WRITE PROTECT

The WP

R/B

Vcc

Vss GROUND

N.C

DNU

NOTE : Connect all VCC and VSS pins of each device to common power supply outputs.

pin provides inadvertent write/erase protection during power transitions. The internal high voltage

generator is reset when the WP

READY/BUSY OUTPUT

The R/B

output indicates the status of the device operation. When low, it indicates that a program, erase or random read operation is in process and returns to high state upon completion. It is an open drain output and does not float to high-z condition when the chip is deselected or when outputs are disabled.

POWER

CC is the power supply for device.

NO CONNECTION

Lead is not internally connected.

DO NOT USE

Leave it disconnected.

pin is active low.

Do not leave VCC or VSS disconnected.

K9F1208U0C K9F1208R0C

Figure 1. K9F1208X0C FUNCTIONAL BLOCK DIAGRAM

VCC

K9F1208B0C

FLASH MEMORY

A9 - A25

A0 - A7

X-Buffers Latches & Decoders

Y-Buffers Latches & Decoders

Command

CE RE WE

Control Logic

& High Voltage

Generator

CLE ALE

Figure 2. K9F1208X0C ARRAY ORGANIZATION

512M + 16M Bits

NAND Flash

ARRAY

(512 + 16)Bytes x 131,072

Page Register & S/A

Y-Gat ing

I/O Buffers & Latches

Global Buffers

1 Block = 32 Pages

= (16K + 512) Bytes

Output

Driver

VCC VSS

I/0 0

I/0 7

128K Pages (=4,096 Blocks)

1st Cycle A

2nd Cycle A9 A10 A11 A12 A13 A14 A15 A16

3rd Cycle A17 A18 A19 A20 A21 A22 A23 A24

4th Cycle A25 *L *L *L *L *L *L *L

NOTE : Column Address : Starting Address of the Register.

1st half Page Register

(=256 Bytes)

512Bytes 16 Bytes

I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7

0 A1 A2 A3 A4 A5 A6 A7

00h Command(Read) : Defines the starting address of the 1st half of the register.

01h Command(Read) : Defines the starting address of the 2nd half of the register.

8 is set to "Low" or "High" by the 00h or 01h Command.

* A

* L must be set to "Low".

* The device ignores any additional input of address cycles than reguired.

2nd half Page Register

(=256 Bytes)

Page Register

512 Bytes

8 bits

I/O 0 ~ I/O 7

16 Bytes

1 Page = 528 Bytes 1 Block = 528 Bytes x 32 Pages = (16K + 512) Bytes 1 Device = 528Bytes x 32Pages x 4,096 Blocks = 528 Mbits

Column Address Row Address

(Page Address)

K9F1208U0C K9F1208R0C

Product Introduction

The K9F1208X0C is a 528Mbits(553,648,218 bits) memory organized as 131,072 rows(pages) by 528 columns. Spare sixteen columns are located from column address of 512 to 527. A 528-bytes data register is connected to memory cell arrays accommodating data transfer between the I/O buffers and memory during page read and page program operations. The memory array is made up of 16 cells that are serially connected to form a NAND structure. Each of the 16 cells resides in a different page. A block consists of the 32 pages formed two NAND structures. A NAND structure consists of 16 cells. Total 135,168 NAND structures reside in a block. The program and read operations are executed on a page basis, while the erase operation is executed on a block basis. The memory array consists of 4,096 separately erasable 16K-bytes blocks. It indicates that the bit by bit erase operation is prohibited on the K9F1208X0C.

The K9F1208X0C has addresses multiplexed into 8 I/O's. This scheme dramatically reduces pin counts and allows systems upgrades to future densities by maintaining consistency in system board design. Command, address and data are all written through I/O's by bringing WE Latch Enable(ALE) are used to multiplex command and address respectively, via the I/O pins. The 64M byte physical space requires 26 addresses, thereby requiring four cycles for byte-level addressing : 1 cycle of column address, 3 cycles of row address, in that order. Page Read and Page Program need the same four address cycles following the required command input. In Block Erase operation, however, only the 3 cycles of row address are used. Device operations are selected by writing specific commands into the command register. Table 1 defines the specific commands of the K9F1208X0C.

Table 1. Command Sets

Read 2 50h -

Read ID 90h -

Reset FFh - O

Page Program 80h 10h

Block Erase 60h D0h

Block Protect 1 41h -

Block Protect 2 42h -

Block Protect 3 43h -

Read Status 70h - O

Read Protection Status 7Ah -

NOTE : 1. The 00h/01h command defines starting address of the 1st/2nd half of registers.

After data access on the 2nd half of register by the 01h command, the status pointer is automatically moved to the 1st half register(00h)

on the next cycle.

Caution : Any undefined command inputs are prohibited except for above command set of Table 1.

K9F1208B0C

to low while CE is low. Data is latched on the rising edge of WE. Command Latch Enable(CLE) and Address

Function 1’st Cycle 2’nd Cycle

00h/01h

(1)

FLASH MEMORY

Acceptable Command

during Busy

K9F1208U0C K9F1208R0C

ABSOLUTE MAXIMUM RATINGS

Voltage on any pin relative to VSS

Temperature Under Bias

Storage Temperature

Short Circuit Current

NOTE :

1. Minimum DC voltage is -0.6V on input/output pins. During transitions, this level may undershoot to -2.0V for periods <30ns. Maximum DC voltage on input/output pins is V

2. Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

(Voltage reference to GND at the condision of K9F1208X0C-XCB0 : TA=0 to 70°C or K9F1208X0C-XIB0 : TA=-40 to 85°C)

Parameter Symbol

Supply Voltage

K9F1208B0C

Parameter Symbol

CC -0.6 to + 2.45 -0.6 to + 4.6

IN -0.6 to + 2.45 -0.6 to + 4.6

I/O -0.6 to Vcc + 0.3 (< 2.45V) -0.6 to Vcc + 0.3 (< 4.6V)

K9F1208X0C-XCB0

K9F1208X0C-XIB0 -40 to +125

K9F1208X0C-XCB0

K9F1208X0C-XIB0

CC+0.3V which, during transitions, may overshoot to VCC+2.0V for periods <20ns.

BIAS

STG -65 to +150 °C

IOS 5mA

1.8V(K9F1208R0C)

1.8V Device 2.7V/3.3V Device

2.7V(K9F1208B0C)

Rating

-10 to +125

FLASH MEMORY

3.3V(K9F1208U0C)

Min Typ . Max Min Typ. Max Min Typ. Max

CC 1.65 1.8 1.95 2.5 2.7 2.9 2.7 3.3 3.6 V

SS 0000 0 0000V

Unit

°C

Unit

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions otherwise noted.)

K9F1208X0C

Parameter Symbol Test Conditions

Operating

Current

Sequential Read

ICC1

tRC=42ns, CE

=0mA

OUT

Program ICC2 - - 8 20 - 10 20 - 10 20

=VIL,

Erase ICC3 - - 8 20 - 10 20 - 10 20

=VIH, WP=0V/V

Stand-by Current(TTL) ISB1

Stand-by Current(CMOS) ISB2

Input Leakage Current

Output Leakage Current

Input High Voltage

Input Low Voltage, All inputs

VIN=0 to Vcc(max)

=VCC-0.2, WP=0V/V

=0 to Vcc(max)

OUT

- -0.3 - 0.4 -0.3 - 0.5 -0.3 - 0.8

K9F1208R0C: IOH=-100µA

Output High Voltage Level

K9F1208B0C: I

K9F1208U0C: I

=-100µA

=-400µA

K9F1208R0C: IOL=100µA

Output Low Voltage Level

K9F1208B0C: I

K9F1208U0C: I

(R/B)VOL=0.4V

Output Low Current(R/B

Notes :

1. Typical values are measured at Vcc=3.3V, TA=25°C. And not 100% tested.

)

=100µA

=2.1mA

1.8V 2.7V 3.3V

Min Typ Max Min Typ Max Min Typ Max

- 8 20 - 10 20 - 10 20

--1 - -1--1

-1050 - 1050 -1050

--±10 - - ±10 - - ±10

-0.4

-0.1

+0.3

-0.4

+0.3

2.0 -

--2.4--

+0.

- - 0.1 - - 0.4 - - 0.4

34- 34- 810-mA

Uni

µA

K9F1208U0C K9F1208R0C

VALID BLOCK

Parameter Symbol Min Typ. Max Unit

Valid Block Number N

NOTE :

1. The K9F1208X0C may include invalid blocks when first shipped. Additional invalid blocks may develop while being used. The number of valid blocks is presented with both cases of invalid blocks considered. Invalid blocks are defined as blocks that contain one or more bad bits. Do not erase or program factory-marked bad blocks. Refer to the attached technical notes for a appropriate management of invalid blocks.

2. The 1st block, which is placed on 00h block address, is guaranteed to be a valid block up to 1K program/erase cycles with 1bit/512Byte ECC.

3. Minimum 1,004 valid blocks are guaranteed for each contiguous 128Mb memory space.

AC TEST CONDITION

(K9F1208X0C-XCB0 :TA=0 to 70°C, K9F1208X0C-XIB0:TA=-40 to 85°C).

Input Pulse Levels

Input Rise and Fall Times 5ns 5ns 5ns

Input and Output Timing Levels

K9F1208R0C:Output Load (Vcc:1.8V +/-10%) K9F1208B0C:Output Load (Vcc:2.7V +/-10%) K9F1208U0C:Output Load (Vcc:3.3V +/-10%)

K9F1208U0C:Output Load (Vcc:3.0V +/-10%) - - 1 TTL GATE and CL=50pF

K9F1208B0C

Parameter

FLASH MEMORY

VB 4,026 - 4,096 Blocks

Value

K9F1208R0C K9F1208B0C K9F1208U0C

0V to V

1 TTL GATE and CL=30pF 1 TTL GATE and CL=30pF

0V to Vcc 0.4V to 2.4V

Vcc/2 1.5V

1 TTL GATE and

CL=100pF

CAPACITANCE(TA=25°C, VCC=1.8V/2.7V/3.3V, f=1.0MHz)

Item Symbol Test Condition Min Max Unit

Input/Output Capacitance C

Input Capacitance C

NOTE : Capacitance is periodically sampled and not 100% tested.

I/O VIL=0V - 10 pF

IN VIN=0V - 10 pF

MODE SELECTION

CLE ALE CE WE RE WP Mode

HLL HX

L H L H X Address Input (4 clocks)

HLL HH

L H L H H Address Input (4 clocks)

L L L H H Data Input

L L L H X Data Output

L L L H H X During Read (Busy) on K9F1208X0C_P

X X X X H X During Read (Busy) except on K9F1208X0C_P

X X X X X H During Program (Busy)

X X X X X H During Erase (Busy)

XXHXX

NOTE : 1. X can be VIL or VIH.

(1)

2. WP should be biased to CMOS high or CMOS low for standby.

X X X L Write Protect

0V/V

(2)

Stand-by

Read Mode

Write Mode

Command Input

K9F1208U0C K9F1208R0C

Program / Erase Characteristics

Program Time

Number of Partial Program Cycles in the Same Page

Block Erase Time t

NOTE NOTE: 1.Typical Program time is defined as the time within which more than 50% of the whole pages are programmed at Vcc of 3.3V and 25’C

AC TIMING CHARACTERISTICS FOR COMMAND / ADDRESS / DATA INPUT

CLE setup Time t

CLE Hold Time t

setup Time tCS 31 - ns

Hold Time tCH 5-ns

Pulse Width

ALE setup Time t

ALE Hold Time t

Data setup Time t

Data Hold Time t

Write Cycle Time t

High Hold Time tWH 15 - ns

K9F1208B0C

Parameter Symbol Min Typ Max Unit

(1)

PROG

Main Array

Spare Array - - 2 cycle

Parameter Symbol Min Max Unit

Nop

BERS -23ms

- 200 500 µs

--1cycle

CLS 21 - ns

CLH 5-ns

(1)

ALS 21 - ns

ALH 5-ns

DS 20 - ns

DH 5-ns

WC 42 - ns

FLASH MEMORY

21 - ns

NOTE: The transition of the corresponding control pins must occur only once while WE is held low.

+ 26 hidden pages