Datasheet K6T4008U1C-TB10, K6T4008U1C-MF85, K6T4008U1C-MB85, K6T4008U1C-MB70, K6T4008U1C-MB10 Datasheet (Samsung)

K6T4008V1C, K6T4008U1C Family

Document Title

512Kx8 bit Low Power and Low Voltage CMOS Static RAM

Revision History

CMOS SRAM

Revision No.

0.0

0.1

0.11

1.0

History

Initial Draft

Revisied

- Speed bin change
KM68U4000C : 85/100ns → 70/85/100ns

- DC Characteristics change
ICC : 5mA at read/write → 4mA at read
ICC1 : 3mA → 4mA
ICC2 : 35mA → 30mA
ISB : 0.5mA → 0.3mA
ISB1 : 10µA → 15µA for commercial parts

- Add 32-TSOP1-0820

Errata correct

- 32-TSOP1-0813 products: T → TG

Finalize

Draft Data

January 13, 1998

June 12, 1998

November 7, 1998

January 15, 1999

Remark

Advance

Preliminary

Final

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.

1

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

512K×8 bit Low Power and Low Voltage CMOS Static RAM

CMOS SRAM

FEATURES

• Process Technology: TFT

• Organization: 512K×8

• Power Supply Voltage

K6T4008V1C Family: 3.0~3.6V
K6T4008U1C Family: 2.7~3.3V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-SOP-525, 32-TSOP2-400F/R

32-TSOP1-0820F, 32-TSOP1-0813.4F

PRODUCT FAMILY

Product Family Operating Temperature Vcc Range Speed

K6T4008V1C-B
K6T4008U1C-B 2.7~3.3V
K6T4008V1C-F
K6T4008U1C-F 2.7~3.3V

Commercial(0~70°C)

Industrial(-40~85°C)

1. The paramerter is measured with 30pF test load.

3.0~3.6V

701)/85/100ns

3.0~3.6V

701)/85/100ns

PIN DESCRIPTION

A18

1
2

A16
A14

3

A12

4
5

A7
A6

6

A5

7
8

32-TSOP2

9

(Forward)

10
11
12
13
14
15
16

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-SOP

I/O1
I/O2
I/O3

VSS

A11

A13
A17

A15

VCC

A18
A16
A14
A12

A4
A3
A2
A1
A0

A9

A8

WE

A7
A6
A5
A4

Name Function Name Function

A0~A18 Address Inputs Vcc Power

WE Write Enable Input Vss Ground

CS Chip Select Input I/O1~I/O8 Data Inputs/Outputs

OE Output Enable Input

VCC

32

A15

31

A17

30

WE

29

A13

28

A8

27

A9

26

A11

25
24

OE

23

A10

22

CS

21

I/O8

20

I/O7

19

I/O6

18

I/O5

17

I/O4

32-TSOP1

32-STSOP1

(Forward)

VCC

A15
A17

WE

A13

A11

OE

A10

CS
I/O8
I/O7
I/O6
I/O5
I/O4

32
31
30
29
28

A8

27

A9

26

32-TSOP2

25

(Reverse)

24
23
22
21
20
19
18
17

32

OE
A10

31
30

CS
I/O8

29
28

I/O7

27

I/O6

26

I/O5

25

I/O4

24

VSS

23

I/O3

22

I/O2

21

I/O1

20

A0

19

A1

18

A2

17

A3

1

A18

2

A16
A14

3

A12

4
5

A7
A6

6

A5

7

A4

8

A3

9

A2

10

A1

11

A0

12

I/O1

13

I/O2

14

I/O3

15

VSS

16

GENERAL DESCRIPTION

The K6T4008V1C and K6T4008U1C families are fabricated by
SAMSUNG′s advanced CMOS process technology. The fami­lies support various operating temperature range and have var­ious package type for user flexibility of system design. The
families also support low data retention voltage for battery
back-up operation with low data retention current.

Power Dissipation

PKG Type

32-SOP
32-TSOP2-F/R
32-TSOP1-F
32-sTSOP1-F

701)/85ns

701)/85ns

Standby

(ISB1, Max)

15µA

20µA

Operating

(ICC2, Max)

30mA

FUNCTIONAL BLOCK DIAGRAM

Clk gen.

A0
A1
A4
A5
A6
A7
A12
A14
A16
A18

I/O1 Data
I/O8

CS

Control

WE

logic

OE

Row
select

cont

Data
cont

Precharge circuit.

Memory array
1024 rows
512×8 columns

I/O Circuit

Column select

A2 A3 A8 A9 A10 A13A11

A15

A17

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

2

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

PRODUCT LIST

Commercial Temp Products(0~70°C) Industrial Temp Products(-40~85°C)

Part Name Function Part Name Function

K6T4008V1C-GB70
K6T4008V1C-GB85
K6T4008V1C-VB70
K6T4008V1C-VB85
K6T4008V1C-MB70
K6T4008V1C-MB85
K6T4008V1C-TB70
K6T4008V1C-TB85
K6T4008V1C-YB70
K6T4008V1C-YB85

32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL

K6T4008V1C-GF70
K6T4008V1C-GF85
K6T4008V1C-VF70
K6T4008V1C-VF85
K6T4008V1C-MF70
K6T4008V1C-MF85
K6T4008V1C-TF70
K6T4008V1C-TF85
K6T4008V1C-YF70
K6T4008V1C-YF85

CMOS SRAM

32-SOP, 70ns, 3.3V, LL
32-SOP, 85ns, 3.3V, LL
32-TSOP2-F, 70ns, 3.3V, LL
32-TSOP2-F, 85ns, 3.3V, LL
32-TSOP2-R, 70ns, 3.3V, LL
32-TSOP2-R, 85ns, 3.3V, LL
32-TSOP1-F, 70ns, 3.3V, LL
32-TSOP1-F, 85ns, 3.3V, LL
32-sTSOP1-F, 70ns, 3.3V, LL
32-sTSOP1-F, 85ns, 3.3V, LL

K6T4008U1C-GB70
K6T4008U1C-GB85
K6T4008U1C-GB10
K6T4008U1C-VB70
K6T4008U1C-VB85
K6T4008U1C-VB10
K6T4008U1C-MB70
K6T4008U1C-MB85
K6T4008U1C-MB10
K6T4008U1C-TB70
K6T4008U1C-TB85
K6T4008U1C-TB10
K6T4008U1C-YB70
K6T4008U1C-YB85
K6T4008U1C-YB10

32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL

K6T4008U1C-GF70
K6T4008U1C-GF85
K6T4008U1C-GF10
K6T4008U1C-VF70
K6T4008U1C-VF85
K6T4008U1C-VF10
K6T4008U1C-MF70
K6T4008U1C-MF85
K6T4008U1C-MF10
K6T4008U1C-TF70
K6T4008U1C-TF85
K6T4008U1C-TF10
K6T4008U1C-YF70
K6T4008U1C-YF85
K6T4008U1C-YF10

32-SOP, 70ns, 3.0V, LL
32-SOP, 85ns, 3.0V, LL
32-SOP, 100ns, 3.0V, LL
32-TSOP2-F, 70ns, 3.0V, LL
32-TSOP2-F, 85ns, 3.0V, LL
32-TSOP2-F, 100ns, 3.0V, LL
32-TSOP2-R, 70ns, 3.0V, LL
32-TSOP2-R, 85ns, 3.0V, LL
32-TSOP2-R, 100ns, 3.0V, LL
32-TSOP1-F, 70ns, 3.0V, LL
32-TSOP1-F, 85ns, 3.0V, LL
32-TSOP1-F, 100ns, 3.0V, LL
32-sTSOP1-F, 70ns, 3.0V, LL
32-sTSOP1-F, 85ns, 3.0V, LL
32-sTSOP1-F, 100ns, 3.0V, LL

FUNCTIONAL DESCRIPTION

CS OE WE I/O Mode Power

H

L H H High-Z Output Disabled Active
L L H Dout Read Active
L

1. X means don′t care (Must be in low or high state)

1)

X

1)

X

1)

X

L Din Write Active

High-Z Deselected Standby

ABSOLUTE MAXIMUM RATINGS

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to VCC+0.5 V ­Voltage on Vcc supply relative to Vss VCC -0.3 to 4.6 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

Operating Temperature TA

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

1)

0 to 70 °C K6T4008V1C-L, K6T4008U1C-L

-40 to 85 °C K6T4008V1C-P, K6T4008U1C-P

3

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

CMOS SRAM

RECOMMENDED DC OPERATING CONDITIONS

1)

Item Symbol Product Min Typ Max Unit

Supply voltage Vcc

K6T4008V1C Family
K6T4008U1C Family

3.0

2.7

3.3

3.0

3.6

3.3

V

Ground Vss All Family 0 0 0 V
Input high voltage VIH K6T4008V1C, K6T4008U1C Family 2.2 ­Input low voltage VIL K6T4008V1C, K6T4008U1C Family

Note:

1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified

2. Overshoot : VCC+2.0V in case of pulse width ≤ 30ns

3. Undershoot : -2.0V in case of pulse width ≤ 30ns

4. Overshoot and undershoot are sampled, not 100% tested.

1)

CAPACITANCE

(f=1MHz, TA=25°C)

-0.3

3)

- 0.6 V

Vcc+0.3

2)

V

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V - 8 pF
Input/Output capacitance CIO VIO=0V - 10 pF

1. Capacitance is sampled, not 100% tested

DC AND OPERATING CHARACTERISTICS

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS=VIH or OE=VIH or WE=VIL VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIL or VIH, Read - - 4 mA

Cycle time=1µs, 100% duty, IIO=0mA CS≤0.2V,VIN≤0.2V or VIN≥Vcc-0.2V

Average operating current

ICC1

Cycle time=Min, 100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL

ICC2
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.2 - - V
Standby Current(TTL) ISB CS=VIH, Other inputs = VIL or VIH - - 0.3 mA
Standby Current (CMOS) ISB1 CS≥Vcc-0.2V, Other inputs=0~Vcc - -

1. Industrial product = 20µA

- - 4 mA

- - 30 mA

1)

15

µA

4

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

AC OPERATING CONDITIONS

TEST CONDITIONS(Test Load and Input/Output Reference)

Input pulse level: 0.4 to 2.2V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL

CL1)=30pF+1TTL

1. 70ns product

CMOS SRAM

1)

CL

1. Including scope and jig capacitance

AC CHARACTERISTICS (K6T4008V1C Family: Vcc=3.0~3.6V, K6T4008U1C Family: Vcc=2.7~3.3V

Commercial product:: TA=0 to 70°C, Industrial product: TA=-40 to 85°C)

Speed Bins

Read

Write

Parameter List Symbol

Read cycle time tRC 70 - 85 - 100 - ns
Address access time tAA - 70 - 85 - 100 ns
Chip select to output tCO - 70 - 85 - 100 ns
Output enable to valid output tOE - 35 - 40 - 50 ns
Chip select to low-Z output tLZ 10 - 10 - 10 - ns
Output enable to low-Z output tOLZ 5 - 5 - 5 - ns
Chip disable to high-Z output tHZ 0 25 0 25 0 30 ns
Output disable to high-Z output tOHZ 0 25 0 25 0 30 ns
Output hold from address change tOH 10 - 10 - 15 - ns
Write cycle time tWC 70 - 85 - 100 - ns
Chip select to end of write tCW 60 - 70 - 80 - ns
Address set-up time tAS 0 - 0 - 0 - ns
Address valid to end of write tAW 60 - 70 - 80 - ns
Write pulse width tWP 55 - 55 - 70 - ns
Write recovery time tWR 0 - 0 - 0 - ns
Write to output high-Z tWHZ 0 25 0 25 0 30 ns
Data to write time overlap tDW 30 - 35 - 40 - ns
Data hold from write time tDH 0 - 0 - 0 - ns
End write to output low-Z tOW 5 - 5 - 5 - ns

70ns 85ns 100ns

Min Max Min Max Min Max

Units

DATA RETENTION CHARACTERISTICS

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR CS≥Vcc-0.2V 2.0 - 3.6 V
Data retention current IDR Vcc=3.0V, CS≥Vcc-0.2V - 0.5
Data retention set-up time tSDR
Recovery time tRDR 5 - -

1. Industrial product = 20µA

See data retention waveform

0 - -

5

1)

15

Revision 1.0

January 1999

µA

ms

K6T4008V1C, K6T4008U1C Family

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)

tRC

Address

tOH

Data Out

Previous Data Valid

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Address

CS

OE

tOLZ

Data out

High-Z

tLZ

tAA

tRC

tAA

tCO1

tOE

CMOS SRAM

Data Valid

tOH

tHZ

tOHZ

Data Valid

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

6

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS

tAW

WE

tAS(3)

Data in

tWHZ

Data out

TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)

Address

CS

Data Undefined

tAS(3)

tWC

tCW(2)

tAW

tWC

tCW(2)

CMOS SRAM

tWR(4)

tWP(1)

tDW tDH

Data Valid

tOW

tWR(4)

tWP(1)

WE

tDW

Data in

Data out

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.

2. tCW is measured from the CS going low to end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.

High-Z

Data Valid

tDH

High-Z

DATA RETENTION WAVE FORM

CS controlled

VCC

3.0/2.7V

2.2V

VDR

CS
GND

tSDR

Data Retention Mode

CS≥VCC - 0.2V

tRDR

7

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

CMOS SRAM

PACKAGE DIMENSIONS

32 PIN PLASTIC SMALL OUTLINE PACKAGE (525mil)

#32

#1

20.87
MAX

0.822

20.47±0.20

0.806±0.008

#17

#16

14.12±0.30

0.556±0.012

2.74±0.20

0.108±0.008

0.118

3.00

11.43±0.20

0.450±0.008

MAX

+0.10

0.20

-0.05
+0.004

0.008

-0.002

0.10 MAX

0.004 MAX

Units: millimeters(inches)

0~8°

13.34

0.525

0.80±0.20

0.031±0.008

0.71

( )

0.028

0.41

0.016

+0.100

-0.050
+0.004

-0.002

1.27

0.050

0.05

0.002

MIN

8

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

CMOS SRAM

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

0.50

0.0197

0~8°

+0.10

0.20

-0.05
+0.004

0.008

-0.002

#16

0.25

TYP

0.010

0.45 ~0.75

0.018 ~0.030

#1

20.00±0.20

0.787±0.008

18.40±0.10

0.724±0.004

#32

0.331

#17

0.15

0.006

0.50

( )

0.020

8.40

Units: millimeters(inches)

MAX

8.00

0.315

1.00±0.10

0.039±0.004

1.20
MAX

0.047

+0.10

-0.05
+0.004

-0.002

0.002

0.10 MAX

0.05

0.004MAX

0.25

( )

0.010

MIN

32 PIN SMALLER THIN SMALL OUTLINE PACKAGE TYPE I (0813.4F)

0.50

0.0197

0~8°

+0.10

0.20

-0.05
+0.004

0.008

-0.002

#16

0.25

TYP

0.010

0.45 ~0.75

0.018 ~0.030

#1

13.40±0.10

0.528±0.008

11.80±0.10

0.465±0.004

#32

#17

0.50

( )

0.020

0.15

0.006

8.40

0.331

+0.10

-0.05
+0.004

-0.002

MAX

1.00±0.10

0.039±0.004

1.20

MAX

0.047

0.25

( )

0.010

8.00

0.315

0.05

MIN

0.002

1.10 MAX

0.004 MAX

9

Revision 1.0

January 1999

K6T4008V1C, K6T4008U1C Family

CMOS SRAM

PACKAGE DIMENSIONS

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400F)

#32

0.95

( )

0.037

#1

0.016±0.004

0.40±0.10

21.35
MAX

0.841

20.95±0.10

0.825±0.004

1.27

0.050

#17

#16

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

0.05

MIN

0.002

1.20

0.047

MAX

0.25

( )

0.010

10.16

0.400

+0.10

0.15

-0.05
+0.004

0.006

-0.002

0.10 MAX

0.004 MAX

Units: millimeters(inches)

0~8°

0.45~0.75

0.018 ~ 0.030

0.50

( )

0.020

32 PIN THIN SMALL OUTLINE PACKAGE TYPE II (400R)

#1

#32

21.35

MAX

0.841

20.95±0.10

0.825±0.004

0.95

( )

0.037

0.40±0.10

0.016±0.004

1.27

0.050

#16

#17

11.76±0.20

0.463±0.008

1.00±0.10

0.039±0.004

0.05

MIN

0.002

1.20

0.047

MAX

( )

10.16

0.400

0.15

0.006

0.10 MAX

0.004 MAX

0.25

0.010

+0.10

-0.05
+0.004

-0.002

0~8°

0.45 ~0.75

0.018 ~ 0.030

0.50

( )

0.020

10

Revision 1.0

January 1999