Datasheet KM684000ALTI-7L, KM684000ALT-5L, KM684000ALR-5L, KM684000ALP-7L, KM684000ALP-7 Datasheet (Samsung)

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

1

Document Title

128Kx8 bit Low Power CMOS Static RAM

Revision History

Revision No.

0.0

1.0

1.01

2.0

3.0

Remark

Preliminary

Final

Final

Final

History

Design target

Finalize

- Improve tWP form 55ns to 50ns for 70ns product.

- Remove 55ns speed bin from industrial product.

Errata correction

Revise

Revise

- Add 55ns parts to industrial products.

Draft Data

October 12, 1998

August 30, 1999

December 1, 1999

February 14, 2000

March 3, 2000

The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and

products. SAMSUNG Electronics will answer to your questions. If you have any questions, please contact the SAMSUNG branch offices.

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

2

128Kx8 bit Low Power CMOS Static RAM

GENERAL DESCRIPTION

The K6T1008C2E families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various pack­age types for user flexibility of system design. The families
also support low data retention voltage for battery back-up
operation with low data retention current.

FEATURES

• Process Technology: TFT

• Organization: 128Kx8

• Power Supply Voltage: 4.5~5.5V

• Low Data Retention Voltage: 2V(Min)

• Three state output and TTL Compatible

• Package Type: 32-DIP-600, 32-SOP-525,

32-TSOP1-0820F/R

PIN DESCRIPTION

Name Function

CS1, CS2 Chip Select Input

OE Output Enable Input

WE Write Enable Input

I/O1~I/O8 Data Inputs/Outputs

A0~A16 Address Inputs

Vcc Power
Vss Ground

N.C. No Connection

PRODUCT FAMILY

1. The parameters are tested with 50pF test load

Product Family Operating Temperature Vcc Range Speed

Power Dissipation

PKG Type

Standby

(ISB1, Max)

Operating
(ICC2, Max)

K6T1008C2E-L

Commercial(0~70°C)

4.5~5.5V 551)/70ns

50µA

50mA

32-DIP-600, 32-SOP-525
32-TSOP1-0820F/R

K6T1008C2E-B 10µA
K6T1008C2E-P

Industrial(-40~85°C)

50µA

32-SOP -525
32-TSOP1-0820F/R

K6T1008C2E-F 15µA

FUNCTIONAL BLOCK DIAGRAM

SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.

Precharge circuit.

Memory array
1024 rows
128×8 columns

I/O Circuit

Column select

Clk gen.

Row
select

I/O1

Data
cont

Data
cont

I/O8

CS1

WE

OE

CS2

Control
logic

A11

A9
A8

A13

WE
CS2
A15

VCC

NC
A16
A14
A12

A7
A6
A5
A4

OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4
VSS
I/O3
I/O2
I/O1
A0
A1
A2
A3

Type1-Forward

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

N.C
A16
A14
A12

A7
A6
A5
A4
A3
A2
A1

A0
I/O1
I/O2
I/O3
VSS

VCC
A15
CS2
WE
A13
A8
A9
A11
OE
A10
CS1
I/O8
I/O7
I/O6
I/O5
I/O4

32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16

32-DIP

32-TSOP

32-SOP

Column Address

Raw
Address

A4
A5
A6

A7
A12
A14
A16

NC

VCC

A15

CS2

WE

A13

A8

A9
A11

A3
A2
A1
A0
I/O1
I/O2
I/O3
VSS
I/O4
I/O5
I/O6
I/O7
I/O8
CS1
A10
OE

Type1-Reverse

17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32

16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1

32-TSOP

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

3

PRODUCT LIST

Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C)

Part Name Function Part Name Function

K6T1008C2E-DL55
K6T1008C2E-DL70
K6T1008C2E-DB55
K6T1008C2E-DB70

K6T1008C2E-GL55
K6T1008C2E-GL70
K6T1008C2E-GB55
K6T1008C2E-GB70

K6T1008C2E-TB55
K6T1008C2E-TB70
K6T1008C2E-RB55
K6T1008C2E-RB70

32-DIP, 55ns, Low Power
32-DIP, 70ns, Low Power
32-DIP, 55ns, Low Low Power
32-DIP, 70ns, Low Low Power

32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power

32-TSOP F, 55ns, Low Low Power
32-TSOP F, 70ns, Low Low Power
32-TSOP R, 55ns, Low Low Power
32-TSOP R, 70ns, Low Low Power

K6T1008C2E-GP55
K6T1008C2E-GP70
K6T1008C2E-GF55
K6T1008C2E-GF70

K6T1008C2E-TF55
K6T1008C2E-TF70
K6T1008C2E-RF55
K6T1008C2E-RF70

32-SOP, 55ns, Low Power
32-SOP, 70ns, Low Power
32-SOP, 55ns, Low Low Power
32-SOP, 70ns, Low Low Power

32-TSOP F, 55ns, Low Low Power
32-TSOP F, 70ns, Low Low Power
32-TSOP R, 55ns, Low Low Power
32-TSOP R, 70ns, Low Low Power

FUNCTIONAL DESCRIPTION

1. X means don′t care (Must be in high or low states)

CS1 CS2 OE WE I/O Mode Power

H

X

1)

X

1)

X

1)

High-Z Deselected Standby

X

1)

L

X

1)

X

1)

High-Z Deselected Standby
L H H H High-Z Output Disabled Active
L H L H Dout Read Active
L H

X

1)

L Din Write Active

ABSOLUTE MAXIMUM RATINGS

1)

1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.

Item Symbol Ratings Unit Remark

Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V ­Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -

Operating Temperature TA

0 to 70 °C K6T1008C2E-L/-B

-40 to 85 °C K6T1008C2E-P/-F

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

4

RECOMMENDED DC OPERATING CONDITIONS

1)

Note:

1. Commercial Product: TA=0 to 70°C
Industrial Product: TA=-40 to 85°C, otherwise specified.

2. Overshoot: Vcc+3.0V in case of pulse width≤30ns.

3. Undershoot: -3.0V in case of pulse width≤30ns.

4. Overshoot and undershoot are sampled, not 100% tested.

Item Symbol Product Min Typ Max Unit

Supply voltage Vcc K6T1008C2E Family 4.5 5.0 5.5 V
Ground Vss All Family 0 0 0 V
Input high voltage VIH K6T1008C2E Family 2.2 -

Vcc+0.5

2)

V

Input low voltage VIL K6T1008C2E Family

-0.5

3)

- 0.8 V

CAPACITANCE

1

)

(f=1MHz, TA=25°C)

1. Capacitance is sampled, not 100% tested

Item Symbol Test Condition Min Max Unit

Input capacitance CIN VIN=0V - 6 pF
Input/Output capacitance CIO VIO=0V - 8 pF

DC AND OPERATING CHARACTERISTICS

1. 50µA for Low power product, in case of Low Low power products are comercial=10µA, industrial=15µA.

Item Symbol Test Conditions Min Typ Max Unit

Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA
Output leakage current ILO CS1=VIH or CS2=VIL or OE=VIH or WE=VIL, VIO=Vss to Vcc -1 - 1 µA
Operating power supply current ICC IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL, Read - - 10 mA

Average operating current

ICC1

Cycle time=1µs, 100%duty, IIO=0mA, CS1≤0.2V, CS2≥Vcc-0.2V, VIN≤0.2V
or VIN≥VCC-0.2V

- - 7 mA

ICC2

Cycle time=Min, 100% duty, IIO=0mA, CS1=VIL, CS2=VIH, VIN=VIH or VIL

- - 50 mA
Output low voltage VOL IOL=2.1mA - - 0.4 V
Output high voltage VOH IOH=-1.0mA 2.4 - - V
Standby Current(TTL) ISB CS1=VIH, CS2=VIL, Other inputs=VIH or VIL - - 3 mA
Standby Current(CMOS) ISB1 CS1≥Vcc-0.2V, CS2≥Vcc-0.2V or CS2≤0.2V, Other inputs=0~Vcc - -

50

1)

µA

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

5

AC CHARACTERISTICS (VCC=4.5~5.5V, Commercial Product: TA=0 to 70°C, Industrial Product: TA=-40 to 85°C)

Parameter List Symbol

Speed Bins

Units

55ns 70ns

Min Max Min Max

Read

Read Cycle Time tRC 55 - 70 - ns
Address Access Time tAA - 55 - 70 ns
Chip Select to Output tCO - 55 - 70 ns
Output Enable to Valid Output tOE - 25 - 35 ns
Chip Select to Low-Z Output tLZ 10 - 10 - ns
Output Enable to Low-Z Output tOLZ 5 - 5 - ns
Chip Disable to High-Z Output tHZ 0 20 0 25 ns
Output Disable to High-Z Output tOHZ 0 20 0 25 ns
Output Hold from Address Change tOH 10 - 10 - ns

Write

Write Cycle Time tWC 55 - 70 - ns
Chip Select to End of Write tCW 45 - 60 - ns
Address Set-up Time tAS 0 - 0 - ns
Address Valid to End of Write tAW 45 - 60 - ns
Write Pulse Width tWP 40 - 50 - ns
Write Recovery Time tWR 0 - 0 - ns
Write to Output High-Z tWHZ 0 20 0 25 ns
Data to Write Time Overlap tDW 20 - 25 - ns
Data Hold from Write Time tDH 0 - 0 - ns
End Write to Output Low-Z tOW 5 - 5 - ns

CL

1)

1. Including scope and jig capacitance

AC OPERATING CONDITIONS

TEST CONDITIONS( Test Load and Input/Output Reference)

Input pulse level: 0.8 to 2.4V
Input rising and falling time: 5ns
Input and output reference voltage:1.5V
Output load(see right): CL=100pF+1TTL

CL=50pF+1TTL

DATA RETENTION CHARACTERISTICS

1. CS1≥Vcc-0.2V, CS2≥Vcc-0.2V(CS1 controlled) or CS2≤0.2V(CS2 controlled)

Item Symbol Test Condition Min Typ Max Unit

Vcc for data retention VDR

CS1≥Vcc-0.2V

1)

2.0 - 5.5 V

Data retention current IDR

Vcc=3.0V, CS1≥Vcc-0.2V

1)

K6T1008C2E-L - - 20

µA

K6T1008C2E-B - - 10
K6T1008C2E-P - - 25
K6T1008C2F-F - - 10

Data retention set-up time tSDR

See data retention waveform

0 - -

ms

Recovery time tRDR 5 - -

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

6

Address

Data Out Previous Data Valid

Data Valid

TIMMING DIAGRAMS

TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS1=OE=VIL, CS2=WE=VIH)

tAA

tRC

tOH

TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)

Data Valid

High-Z

CS1

Address

OE

Data out

NOTES (READ CYCLE)

1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage

levels.

2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device

interconnection.

CS2

tOH

tAA

tOLZ

tLZ

tOHZ

tHZ(1,2)

tRC

tCO2

tOE

tCO1

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

7

TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)

Address

CS1

tCW(2)

tWR(4)

TIMING WAVEFORM OF WRITE CYCLE(2) (CS1 Controlled)

Address

CS1

tWC

tWR(4)

tAS(3)

CS2

tCW(2)

tWP(1)

tDW tDH

tOW

tWHZ

Data Undefined

Data Valid

WE

Data in

Data out

tDW

tDH

Data Valid

WE

Data in

Data out

High-Z

High-Z

CS2

tWC

tAW

tAS(3)

tCW(2)

tWP(1)

tAW

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

8

DATA RETENTION WAVE FORM

CS1 controlled

VCC

4.5V

2.2V

VDR

CS1
GND

Data Retention Mode

CS≥VCC - 0.2V

tSDR

tRDR

TIMING WAVEFORM OF WRITE CYCLE(3) (CS2 Controlled)

Address

CS1

tAW

NOTES (WRITE CYCLE)

1. A write occurs during the overlap of a low CS1, a high CS2 and a low WE. A write begins at the latest transition among CS1 goes low,
CS2 going high and WE going low: A write end at the earliest transition among CS1 going high, CS2 going low and WE going high,
tWP is measured from the begining of write to the end of write.

2. tCW is measured from the CS1 going low or CS2 going high to the end of write.

3. tAS is measured from the address valid to the beginning of write.

4. tWR is measured from the end of write to the address change. tWR1 applied in case a write ends as CS1 or WE going high tWR2 applied
in case a write ends as CS2 going to low.

CS2

tCW(2)

WE

Data in Data Valid

Data out

High-Z

High-Z

tCW(2)

tWR(4)

tWP(1)

tDW

tDH

tAS(3)

tWC

CS2 controlled

VCC

4.5V

0.4V

VDR

CS2

GND

Data Retention Mode

tSDR

tRDR

CS2≤0.2V

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

9

PACKAGE DIMENSIONS

Units: millimeters(inches)

0~15°

1.91

#1

32 DUAL INLINE PACKAGE (600mil)

#32

13.60±0.20

0.535±0.008

41.91±0.20

1.650±0.008

( )

0.075

15.24

0.600

+0.10

MAX

42.31

1.666

0.25

-0.05
+0.004

0.010

-0.002

2.54

0.100

MAX

3.81±0.20

0.150±0.008

5.08

0.200

MIN

0.015

0.38

0.130±0.012

3.30±0.30

#16

#17

1.52±0.10

0.060±0.004

0.46±0.10

0.018±0.004

32 PLASTIC SMALL OUTLINE PACKAGE (525mil)

0~8°

#32

20.47±0.20

0.806±0.008

MAX

20.87

0.822
MAX

2.74±0.20

0.108±0.008

3.00

0.118

MIN

0.002

0.05

0.004 MAX

0.10 MAX

#1

0.71

( )

0.028

13.34

0.525

11.43±0.20

0.450±0.008

0.80±0.20

0.031±0.008

+0.10

0.20

-0.05
+0.004

0.008

-0.002

14.12±0.30

0.556±0.012

#17

#16

1.27

0.050

+0.100

0.41

-0.050
+0.004

0.016

-0.002

CMOS SRAMK6T1008C2E Family

Revision 3.0

March 2000

10

32 PIN THIN SMALL OUTLINE PACKAGE TYPE I (0820F)

#32

1.00±0.10

0.039±0.004

MAX

8.40

0.331

0.10 MAX

0.004 MAX

#1

0.50

( )

0.020

18.40±0.10

0.724±0.004

0.45 ~0.75

0.018 ~0.030

20.00±0.20

0.787±0.008

#17

+0.10

0.15

-0.05
+0.004

0.006

-0.002

0~8°

+0.10

0.20

-0.05
+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

TYP

0.25

0.010

#16

PACKAGE DIMENSIONS

Units: millimeters(inches)

32 THIN SMALL OUTLINE PACKAGE TYPE I (0820R)

#32

1.00±0.10

0.039±0.004

MAX

8.40

0.331

0.004 MAX

0.10 MAX

#1

0.50

( )

0.020

18.40±0.10

0.724±0.004

0.45 ~0.75

0.018 ~0.030

20.00±0.20

0.787±0.008

#17

+0.10

0.15

-0.05
+0.004

0.006

-0.002

0~8°

+0.10

0.20

-0.05
+0.004

0.008

-0.002

0.50

0.0197

0.25

( )

0.010

MIN

0.05

0.002

MAX

1.20

0.047

8.00

0.315

TYP

0.25

0.010

#16