SAMSUNG K6T0808C1D Technical data

查询K6T0808C1D供应商
K6T0808C1D Family CMOS SRAM
Document Title
32Kx8 bit Low Power CMOS Static RAM
Revision History
Revision No
0.0
0.1
1.0
History
Initial draft
First revision
- KM62256DL/DLI ISB1 = 10050µA KM62256DL-L ISB1 = 2010µA KM62256DLI-L ISB1 = 5015µA
- CIN = 6 8pF, CIO = 810pF
- KM62256D-4/5/7 Family tOH = 510ns
- KM62256DL/DLI IDR = 50→30µA KM62256DL-L/DLI-L IDR = 3015µA
Finalize
- Remove ICC write value
- Improved operating current ICC2 = 7060mA
- Improved standby current KM62256DL/DLI ISB1 = 5030µA KM62256DL-L ISB1 = 105µA KM62256DLI-L ISB1 = 155µA
- Improved data retention current KM62256DL/DLI IDR = 305µA KM62256DL-L/DLI-L IDR = 153µA
- Remove 45ns part from commercial product and 100ns part from industrial product. Replace test load 100pF to 50pF for 55ns part
Draft Data
May 18, 1997
April 1, 1997
November 11, 1997
Design target
Preliminily
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
32Kx8 bit Low Power CMOS Static RAM
FEATURES
Process Technology : TFT
Organization : 32Kx8
Power Supply Voltage : 4.5~5.5V
Low Data Retention Voltage : 2V(Min)
Three state output and TTL Compatible
Package Type : 28-DIP-600B, 28-SOP-450
28-TSOP1-0813.4 F/R
GENERAL DESCRIPTION
The K6T0808C1D families are fabricated by SAMSUNG′s advanced CMOS process technology. The families support various operating temperature ranges and have various package types for user flexibility of system design. The fami­lies also support low data retention voltage for battery back­up operation with low data retention current.
PRODUCT FAMILY
Product Family Operating Temperature VCC Range Speed
(ISB1, Max)
K6T0808C1D-L K6T0808C1D-B 5µA K6T0808C1D-P K6T0808C1D-F 5µA
1. The parameter is tested with 50pF test load.
PIN DESCRIPTION
A14
1
A12
2
3
A7
4
A6
5
A5
6
A4
28-DIP
7
A3
28-SOP
8
A2
9
A1
10
A0
11
I/O1
12
I/O2
13
I/O3
14
VSS
Pin Name Function Pin Name Function
CS Chip Select Input I/O1~I/O8 Data Inputs/Outputs OE Output Enable Input Vcc Power WE Write Enable Input Vss Ground
A0~A14 Address Inputs NC No connect
Commercial (0~70°C)
4.5 to 5.5V
Industrial (-40~85°C) 70ns
1
OE
2
A11
3
A9
4
A8
VCC
28
27
WE
26
A13
25
A8
A9
24
A11
23
22
OE
21
A10
20
CS
19
I/O8
18
I/O7
17
I/O6
16
I/O5
15
I/O4
A13
VCC
A14 A12
A12 A14
VCC
A13
A11
WE
WE
5 6 7 8 9 10
A7
11
A6
12
A5
13
A4
14
A3
14
A3
13
A4 A5
12
A6
11
A7
10 9 8 7 6 5
A8
4
A9
3 2 1
OE
28-TSOP
Type1 - Forward
28-TSOP
Type1 - Reverse
28 27 26 25 24 23 22 21 20 19 18 17 16 15
15 16 17 18 19 20 21 22 23 24 25 26 27 28
551)/70ns
FUNCTIONAL BLOCK DIAGRAM
A10 CS I/O8 I/O7 I/O6 I/O5 I/O4 VSS I/O3 I/O2 I/O1 A0 A1 A2
A2 A1 A0 I/O1 I/O2 I/O3 VSS I/O4 I/O5 I/O6 I/O7 I/O8 CS A10
CS
WE
OE
I/O1 I/O8
A13 A8
A12 A14 A4
A5 A6 A7
Control Logic
Power Dissipation
Standby
Operating (Icc2, Max)
30µA
30µA
Clk gen.
Row select
Data cont
Data cont
28-DIP,28-SOP 28-TSOP1-F/R
60mA
28-SOP 28-TSOP1-F/R
Precharge circuit.
Memory array 256 rows 128×8 columns
I/O Circuit
Column select
A10 A3 A0 A1 A2 A11A9
PKG Type
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
PRODUCT LIST
Commercial Temperature Products(0~70°C) Industrial Temperature Products(-40~85°C) Part Name Function Part Name Function
K6T0808C1D-DL55 K6T0808C1D-DB55 K6T0808C1D-DL70 K6T0808C1D-DB70 K6T0808C1D-GL55 K6T0808C1D-GB55 K6T0808C1D-GL70 K6T0808C1D-GB70 K6T0808C1D-TL55 K6T0808C1D-TB55 K6T0808C1D-TL70 K6T0808C1D-TB70 K6T0808C1D-RL55 K6T0808C1D-RB55 K6T0808C1D-RL70 K6T0808C1D-RB70
FUNCTIONAL DESCRIPTION
28-DIP, 55ns, L-pwr 28-DIP, 55ns, LL-pwr 28-DIP, 70ns, L-pwr 28-DIP, 70ns, LL-pwr 28-SOP, 55ns, L-pwr 28-SOP, 55ns, LL-pwr 28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 55ns, L-pwr 28-TSOP1 F, 55ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 55ns, L-pwr 28-TSOP1 R, 55ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr
K6T0808C1D-GP70 K6T0808C1D-GF70 K6T0808C1D-TP70 K6T0808C1D-TF70 K6T0808C1D-RP70 K6T0808C1D-RF70
28-SOP, 70ns, L-pwr 28-SOP, 70ns, LL-pwr 28-TSOP1 F, 70ns, L-pwr 28-TSOP1 F, 70ns, LL-pwr 28-TSOP1 R, 70ns, L-pwr 28-TSOP1 R, 70ns, LL-pwr
CS OE WE I/O Mode Power
H
L H H High-Z Output Disabled Active L L H Dout Read Active L
1. X means dont care (Must be in high or low states)
1)
X
1)
X
ABSOLUTE MAXIMUM RATINGS
Item Symbol Ratings Unit Remark
Voltage on any pin relative to Vss VIN,VOUT -0.5 to 7.0 V ­Voltage on Vcc supply relative to Vss VCC -0.5 to 7.0 V ­Power Dissipation PD 1.0 W ­Storage temperature TSTG -65 to 150 °C -
Operating Temperature TA
Soldering temperature and time TSOLDER 260°C, 10sec (Lead Only) - -
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1)
X
L Din Write Active
1)
High-Z Deselected Standby
0 to 70 °C K6T0808C1D-L
-40 to 85 °C K6T0808C1D-P
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
-0.5
1)
Vcc+0.5V
3)
- 0.8 V
2)
V
RECOMMENDED DC OPERATING CONDITIONS
Item Symbol Min Typ Max Unit
Supply voltage Vcc 4.5 5.0 5.5 V Ground Vss 0 0 0 V Input high voltage VIH 2.2 ­Input low voltage VIL
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested
CAPACITANCE
Input capacitance CIN VIN=0V - 8 pF Input/Output capacitance CIO VIO=0V - 10 pF
1. Capacitance is sampled not, 100% tested
1)
(f=1MHz, TA=25°C)
Item Symbol Test Condition Min Max Unit
DC AND OPERATING CHARACTERISTICS
Item Symbol Test Conditions Min Typ Max Unit
Input leakage current ILI VIN=Vss to Vcc -1 - 1 µA Output leakage current ILO CS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc -1 - 1 µA Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL, Read - 5 10 mA
Cycle time=1µs, 100% duty, IIO=0mA
ICC1
Average operating current
Output low voltage VOL IOL=2.1mA - - 0.4 V Output high voltage VOH IOH=-1.0mA 2.4 - - V Standby Current(TTL) ISB CS=VIH, Other inputs=VIH or VIL - - 1 mA
Standby Current (CMOS) ISB1 CSVcc-0.2V, Other inputs=0~Vcc
CS0.2V, VIN0.2V, VINVcc -0.2V
ICC2 Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL - 45 60 mA
Low Power - 1 30 µA Low Low Power - 0.2 5 µA
Read - 2 5 Write - 20
mA
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V Input rising and falling time : 5ns Input and output reference voltage : 1.5V Output load (See right) :CL=100pF+1TTL
CL=50pF+1TTL
AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70°C, K6T0808C1D-P Family:TA=-40 to 85°C)
Parameter List Symbol
Read cycle time tRC 55 - 70 - ns Address access time tAA - 55 - 70 ns Chip select to output tCO - 55 - 70 ns Output enable to valid output tOE - 25 - 35 ns
Read
Write
1. The parameter is tested with 50pF test load.
Chip select to low-Z output tLZ 10 - 10 - ns Output enable to low-Z output tOLZ 5 - 5 - ns Chip disable to high-Z output tHZ 0 20 0 30 ns Output disable to high-Z output tOHZ 0 20 0 30 ns Output hold from address change tOH 10 - 10 - ns Write cycle time tWC 55 - 70 - ns Chip select to end of write tCW 45 - 60 - ns Address set-up time tAS 0 - 0 - ns Address valid to end of write tAW 45 - 60 - ns Write pulse width tWP 40 - 50 - ns Write recovery time tWR 0 - 0 - ns Write to output high-Z tWHZ 0 20 0 25 ns Data to write time overlap tDW 25 - 30 - ns Data hold from write time tDH 0 - 0 - ns End write to output low-Z tOW 5 - 5 - ns
1)
CL
1. Including scope and jig capacitance
Speed Bins
551)ns
Min Max Min Max
70ns
Units
DATA RETENTION CHARACTERISTICS
Item Symbol Test Condition Min Typ Max Unit
Vcc for data retention VDR CSVcc-0.2V 2.0 - 5.5 V Data retention current IDR Vcc=3.0V, CSVcc-0.2V
Data retention set-up time tSDR Recovery time tRDR 5 - -
See data retention waveform
L-Ver - 1 15 LL-Ver - 0.2 3
0 - -
Revision 1.0
November 1997
µA
ms
K6T0808C1D Family CMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tCO
tOE
tAA
Data Valid
tRC
tOH
tHZ
tOHZ
Data Valid
tOH
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
tOLZ
Data out
High-Z
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tAW
WE
tAS(3)
Data in
tWHZ
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2) (CS Controlled)
Address
tAS(3)
CS
tCW(2)
tWP(1)
tDW
tWC
tCW(2)
tAW
tWP(1)
tWR(4)
tDH
Data Valid
tOW
tWR(4)
WE
tDW
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
High-Z
Data Valid
tDH
High-Z
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
2.2V
VDR
tSDR tRDR
Data Retention Mode
CS GND
CSVCC - 0.2V
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
PACKAGE DIMENSIONS
28 PIN DUAL INLINE PACKAGE(600mil)
#28
13.60± 0.20
0.535± 0.008
#1
0.46± 0.10
1.65
( )
0.065
0.018± 0.004
1.52± 0.10
0.060± 0.004
36.72
MAX
1.446
36.32± 0.20
1.430± 0.008
2.54
0.100
#15
#14
15.24
3.81± 0.20
0.150± 0.008
5.08
0.200
0.38
MIN
0.015
0.600
MAX
3.30± 0.30
0.130± 0.012
Units: millimeter(inch)
+0.10
0.25
-0.05 +0.004
0.010
-0.002
0~15°
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
#28
#1 #14
18.69
MAX
0.736
18.29± 0.20
0.720± 0.008
0.89
( )
0.035
0.41± 0.10
0.016± 0.004
1.27
0.050
#15
11.81± 0.30
0.465± 0.012
2.59± 0.20
0.102± 0.008
0.05
MIN
0.002
3.00
0.118
8.38± 0.20
0.330± 0.008
MAX
+0.10
0.15
-0.05 +0.004
0.006
-0.002
0.10 MAX
0.004 MAX
0~8°
11.43
0.450
1.02± 0.20
0.040± 0.008
Revision 1.0
November 1997
K6T0808C1D Family CMOS SRAM
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
13.40± 0.20
0.528± 0.008
11.80± 0.10
0.465± 0.004
0.55
0.0217
0~8°
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.25
TYP
0.010
0.45 ~0.75
0.018 ~0.030
#1
#28
#15#14
0.50
( )
0.020
0.15
0.006
+0.10
-0.05
+0.004
-0.002
MAX
8.40
0.331
1.00± 0.10
0.039± 0.004
1.20
MAX
0.047
Units: millimeter(inch)
0.10 MAX
0.004 MAX
8.00
0.315
0.05
0.002
0.425
( )
0.017
MIN
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
13.40± 0.20
0.528± 0.008
11.80± 0.10
0.465± 0.004
#15#14
#28
( )
0.55
0.0217
0~8°
+0.10
0.20
-0.05 +0.004
0.008
-0.002
0.25 TYP
0.010
0.45 ~0.75
0.018 ~0.030
#1
0.15
0.006
0.50
0.020
+0.10
-0.05 +0.004
-0.002
MAX
8.40
0.331
1.00± 0.10
0.039± 0.004
1.20
MAX
0.047
0.10 MAX
0.004 MAX
0.425
( )
0.017
8.00
0.315
0.05
MIN
0.002
Revision 1.0
November 1997
Loading...