- Improved data retention current
KM62256DL/DLI IDR = 30 → 5µA
KM62256DL-L/DLI-L IDR = 15 → 3µA
- Remove 45ns part from commercial product and 100ns part
from industrial product.
Replace test load 100pF to 50pF for 55ns part
Draft Data
May 18, 1997
April 1, 1997
November 11, 1997
Remark
Design target
Preliminily
Final
The attached datasheets are provided by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserves the right to change the specifications and
products. SAMSUNG Electronics will answer to your questions about device. If you have any questions, please contact the SAMSUNG branch offices.
Revision 1.0
November 1997
K6T0808C1D FamilyCMOS SRAM
32Kx8 bit Low Power CMOS Static RAM
FEATURES
• Process Technology : TFT
• Organization : 32Kx8
• Power Supply Voltage : 4.5~5.5V
• Low Data Retention Voltage : 2V(Min)
• Three state output and TTL Compatible
• Package Type : 28-DIP-600B, 28-SOP-450
28-TSOP1-0813.4 F/R
GENERAL DESCRIPTION
The K6T0808C1D families are fabricated by SAMSUNG′s
advanced CMOS process technology. The families support
various operating temperature ranges and have various
package types for user flexibility of system design. The families also support low data retention voltage for battery backup operation with low data retention current.
LHHHigh-ZOutput DisabledActive
LLHDoutReadActive
L
1. X means don′t care (Must be in high or low states)
1)
X
1)
X
ABSOLUTE MAXIMUM RATINGS
ItemSymbolRatingsUnitRemark
Voltage on any pin relative to VssVIN,VOUT-0.5 to 7.0VVoltage on Vcc supply relative to VssVCC-0.5 to 7.0VPower DissipationPD1.0WStorage temperatureTSTG-65 to 150°C-
Operating TemperatureTA
Soldering temperature and timeTSOLDER260°C, 10sec (Lead Only)--
1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation should be
restricted to recommended operating condition. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
1)
X
LDinWriteActive
1)
High-ZDeselectedStandby
0 to 70°C K6T0808C1D-L
-40 to 85°C K6T0808C1D-P
Revision 1.0
November 1997
K6T0808C1D FamilyCMOS SRAM
-0.5
1)
Vcc+0.5V
3)
-0.8V
2)
V
RECOMMENDED DC OPERATING CONDITIONS
ItemSymbolMinTypMaxUnit
Supply voltageVcc4.55.05.5V
GroundVss000V
Input high voltageVIH2.2Input low voltageVIL
Note:
1. Commercial Product : TA=0 to 70°C, otherwise specified
Industrial Product : TA=-40 to 85°C, otherwise specified
2. Overshoot : VCC+3.0V in case of pulse width≤30ns
3. Undershoot : -3.0V in case of pulse width≤30ns
4. Overshoot and undershoot are sampled, not 100% tested
Input leakage currentILIVIN=Vss to Vcc-1-1µA
Output leakage currentILOCS=VIH or OE=VIH or WE=VIL, VIO=VSS to Vcc-1-1µA
Operating power supply current ICC IIO=0mA, CS=VIL, VIN=VIH or VIL, Read-510mA
Cycle time=1µs, 100% duty, IIO=0mA
ICC1
Average operating current
Output low voltageVOLIOL=2.1mA--0.4V
Output high voltageVOHIOH=-1.0mA2.4--V
Standby Current(TTL)ISBCS=VIH, Other inputs=VIH or VIL--1mA
Standby Current (CMOS)ISB1CS≥Vcc-0.2V, Other inputs=0~Vcc
CS≤0.2V, VIN≤0.2V, VIN≥Vcc -0.2V
ICC2Cycle time=Min,100% duty, IIO=0mA, CS=VIL, VIN=VIH or VIL-4560mA
Low Power-130µA
Low Low Power-0.25µA
Read-25
Write-20
mA
Revision 1.0
November 1997
K6T0808C1D FamilyCMOS SRAM
AC OPERATING CONDITIONS
TEST CONDITIONS (Test Load and Test Input/Output Reference)
Input pulse level : 0.8 to 2.4V
Input rising and falling time : 5ns
Input and output reference voltage : 1.5V
Output load (See right) :CL=100pF+1TTL
CL=50pF+1TTL
AC CHARACTERISTICS (Vcc=4.5~5.5V, K6T0808C1D-L Family:TA=0 to 70°C, K6T0808C1D-P Family:TA=-40 to 85°C)
Parameter ListSymbol
Read cycle timetRC55-70-ns
Address access timetAA-55-70ns
Chip select to outputtCO-55-70ns
Output enable to valid outputtOE-25-35ns
Read
Write
1. The parameter is tested with 50pF test load.
Chip select to low-Z outputtLZ10-10-ns
Output enable to low-Z outputtOLZ5-5-ns
Chip disable to high-Z outputtHZ020030ns
Output disable to high-Z outputtOHZ020030ns
Output hold from address changetOH10-10-ns
Write cycle timetWC55-70-ns
Chip select to end of writetCW45-60-ns
Address set-up timetAS0-0-ns
Address valid to end of writetAW45-60-ns
Write pulse widthtWP40-50-ns
Write recovery timetWR0-0-ns
Write to output high-ZtWHZ020025ns
Data to write time overlaptDW25-30-ns
Data hold from write time tDH0-0-ns
End write to output low-ZtOW5-5-ns
1)
CL
1. Including scope and jig capacitance
Speed Bins
551)ns
MinMaxMinMax
70ns
Units
DATA RETENTION CHARACTERISTICS
ItemSymbolTest ConditionMinTypMaxUnit
Vcc for data retentionVDRCS≥Vcc-0.2V2.0-5.5V
Data retention currentIDRVcc=3.0V, CS≥Vcc-0.2V
Data retention set-up timetSDR
Recovery timetRDR5--
See data retention waveform
L-Ver-115
LL-Ver-0.23
0--
Revision 1.0
November 1997
µA
ms
K6T0808C1D FamilyCMOS SRAM
TIMMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH)
tRC
Address
tAA
tCO
tOE
tAA
Data Valid
tRC
tOH
tHZ
tOHZ
Data Valid
tOH
Data Out
Previous Data Valid
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
CS
OE
tOLZ
Data out
High-Z
tLZ
NOTES (READ CYCLE)
1. tHZ and tOHZ are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage
levels.
2. At any given temperature and voltage condition, tHZ(Max.) is less than tLZ(Min.) both for a given device and from device to device
interconnection.
Revision 1.0
November 1997
K6T0808C1D FamilyCMOS SRAM
TIMING WAVEFORM OF WRITE CYCLE(1) (WE Controlled)
tWC
Address
CS
tAW
WE
tAS(3)
Data in
tWHZ
Data out
Data Undefined
TIMING WAVEFORM OF WRITE CYCLE(2)(CS Controlled)
Address
tAS(3)
CS
tCW(2)
tWP(1)
tDW
tWC
tCW(2)
tAW
tWP(1)
tWR(4)
tDH
Data Valid
tOW
tWR(4)
WE
tDW
Data in
Data out
NOTES (WRITE CYCLE)
1. A write occurs during the overlap of a low CS and a low WE. A write begins at the latest transition among CS going Low and WE
going low : A write end at the earliest transition among CS going high and WE going high, tWP is measured from the begining of write
to the end of write.
2. tCW is measured from the CS going low to end of write.
3. tAS is measured from the address valid to the beginning of write.
4. tWR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
High-Z
Data Valid
tDH
High-Z
DATA RETENTION WAVE FORM
CS controlled
VCC
4.5V
2.2V
VDR
tSDRtRDR
Data Retention Mode
CS
GND
CS≥VCC - 0.2V
Revision 1.0
November 1997
K6T0808C1D FamilyCMOS SRAM
PACKAGE DIMENSIONS
28 PIN DUAL INLINE PACKAGE(600mil)
#28
13.60±0.20
0.535±0.008
#1
0.46±0.10
1.65
( )
0.065
0.018±0.004
1.52±0.10
0.060±0.004
36.72
MAX
1.446
36.32±0.20
1.430±0.008
2.54
0.100
#15
#14
15.24
3.81±0.20
0.150±0.008
5.08
0.200
0.38
MIN
0.015
0.600
MAX
3.30±0.30
0.130±0.012
Units: millimeter(inch)
+0.10
0.25
-0.05+0.004
0.010
-0.002
0~15°
28 PIN PLASTIC SMALL OUTLINE PACKAGE(450mil)
#28
#1#14
18.69
MAX
0.736
18.29±0.20
0.720±0.008
0.89
( )
0.035
0.41±0.10
0.016±0.004
1.27
0.050
#15
11.81±0.30
0.465±0.012
2.59±0.20
0.102±0.008
0.05
MIN
0.002
3.00
0.118
8.38±0.20
0.330±0.008
MAX
+0.10
0.15
-0.05+0.004
0.006
-0.002
0.10 MAX
0.004 MAX
0~8°
11.43
0.450
1.02±0.20
0.040±0.008
Revision 1.0
November 1997
K6T0808C1D FamilyCMOS SRAM
PACKAGE DIMENSIONS
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4F)
13.40±0.20
0.528±0.008
11.80±0.10
0.465±0.004
0.55
0.0217
0~8°
+0.10
0.20
-0.05
+0.004
0.008
-0.002
0.25
TYP
0.010
0.45 ~0.75
0.018 ~0.030
#1
#28
#15#14
0.50
( )
0.020
0.15
0.006
+0.10
-0.05
+0.004
-0.002
MAX
8.40
0.331
1.00±0.10
0.039±0.004
1.20
MAX
0.047
Units: millimeter(inch)
0.10 MAX
0.004 MAX
8.00
0.315
0.05
0.002
0.425
( )
0.017
MIN
28 PIN THIN SMALL OUTLINE PACKAGE TYPE1 (0813.4R)
13.40±0.20
0.528±0.008
11.80±0.10
0.465±0.004
#15#14
#28
( )
0.55
0.0217
0~8°
+0.10
0.20
-0.05+0.004
0.008
-0.002
0.25
TYP
0.010
0.45 ~0.75
0.018 ~0.030
#1
0.15
0.006
0.50
0.020
+0.10
-0.05+0.004
-0.002
MAX
8.40
0.331
1.00±0.10
0.039±0.004
1.20
MAX
0.047
0.10 MAX
0.004 MAX
0.425
( )
0.017
8.00
0.315
0.05
MIN
0.002
Revision 1.0
November 1997
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