查询K6R1004C1D-JC10供应商
K6R1004V1D
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 1.0
Rev. 2.0
Rev. 3.0
History
Initial document.
Speed bin modify
Current modify
1. Final datasheet release
2. Delete 12ns speed bin.
3. Change Icc for Industrial mode.
I
CC(Industrial)
1. Delete UB
1. Add the Lead Free Package type.
Item Previous Current
8ns 100mA 90mA
10ns 85mA 75mA
,LB releated timing diagram.
Draft Data
May. 11. 2001
June. 18. 2001
September. 9. 2001
December. 18. 2001
June. 19. 2002
July. 26, 2004
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Rev. 3.0
July 2004
PRELIMINARY
PRELIMINARY
K6R1004V1D
1Mb Async. Fast SRAM Ordering Information
Org. Part Number VDD(V) Speed ( ns ) PKG Temp. & Power
for AT&T
CMOS SRAM
256K x4
128K x8
64K x16
K6R1004C1D-J(K)C(I) 10 5 10
K6R1004V1D-J(K)C(I) 08/10 3.3 8/10
K6R1008C1D-J(K,T,U)C(I) 10 5 10
K6R1008V1D-J(K,T,U)C(I) 08/10 3.3 8/10
K6R1016C1D-J(K,T,U,E)C(I) 10 5 10
K6R1016V1D-J(K,T,U,E)C(I) 08/10
3.3 8/10
J : 32-SOJ
K: 32-SOJ(LF)
J : 32-SOJ
K : 32-SOJ(LF)
T : 32-TSOP2
U : 32-TSOP2(LF)
J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
- 2 -
Rev. 3.0
July 2004
PRELIMINARY
PRELIMINARY
K6R1004V1D
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating //K6R1004V1D-08: 80mA(Max.)
K6R1004V1D-10: 65mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration :
K6R1004V1D-J : 32-SOJ-400
K6R1004V1D-K : 32-SOJ-400 (Lead-Free)
• Operating in Commercial and Industrial Temperature range.
The K6R1004V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits.
The K6R1004V1D uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using
SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
for AT&T
CMOS SRAM
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1 ~ I/O4
CS
WE
OE
Clk Gen.
Row Select
Data
Cont.
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
512x4 Columns
I/O Circuit &
Column Select
A10 A11 A12 A13 A14 A15
A9 A16 A17
1
N.C
2
0
A
A1
3
A2
4
A3
5
CS
6
I/O1
7
Vcc
Vss
I/O
WE
A4
A5
A6
A7
N.C
8
9
2
10
11
12
13
14
15
16
SOJ
PIN FUNCTION
Pin Name Pin Function
0 - A17 Address Inputs
A
WE Write Enable
CS
OE
1 ~ I/O4 Data Inputs/Outputs
I/O
CC Power(+3.3V)
V
V
SS Ground
N.C No Connection
Chip Select
Output Enable
17
A
32
A16
31
A15
30
A14
29
A13
28
OE
27
I/O4
26
Vss
25
Vcc
24
3
I/O
23
A12
22
A11
21
A10
20
A9
19
A8
18
N.C
17
- 3 -
Rev. 3.0
July 2004
PRELIMINARY
PRELIMINARY
K6R1004V1D
ABSOLUTE MAXIMUM RATINGS*
Parameter Symbol Rating Unit
Voltage on Any Pin Relative to V
Voltage on V
Power Dissipation P
Storage Temperature T
Operating Temperature Commercial T
* Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied.
Exposure to absolute maximum rating conditions for extended periods may affect reliability.
CC Supply Relative to VSS VCC -0.5 to 4.6 V
RECOMMENDED DC OPERATING CONDITIONS(TA=0 to 70°C)
Parameter
Supply Voltage V
Ground V
Input High Voltage V
Input Low Voltage V
* VIL(Min) = -2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
IH(Max) = VCC + 2.0V a.c (Pulse Width ≤ 8ns) for I ≤ 20mA.
** V
SS VIN, VOUT -0.5 to 4.6 V
d 1W
STG -65 to 150 °C
A 0 to 70 °C
Industrial T
Symbol
CC 3.0 3.3 3.6 V
SS 000V
IH 2.0 - VCC+0.3** V
IL -0.3* - 0.8 V
A -40 to 85 °C
Min
Typ Max Unit
for AT&T
CMOS SRAM
DC AND OPERATING CHARACTERISTICS*(TA=0 to 70°C, Vcc=3.3±0.3V, unless otherwise specified)
Parameter Symbol Test Conditions
Input Leakage Current I
Output Leakage Current I
Operating Current I
Standby Current I
Output Low Voltage Level V
Output High Voltage Level V
* The above parameters are also guaranteed at industrial temperature range.
LI VIN=VSS to VCC -2 2 µA
LO CS=VIH or OE=VIH or WE=VIL
VOUT=VSS to VCC
CC Min. Cycle, 100% Duty
SB Min. Cycle, CS=VIH -20mA
I
SB1 f=0MHz, CS≥VCC-0.2V,
OL IOL=8mA - 0.4 V
OH IOH=-4mA 2.4 - V
=VIL, VIN=VIH or VIL, IOUT=0mA
CS
IN≥VCC-0.2V or VIN≤0.2V
V
Com. 8ns - 80 mA
10ns - 65
Ind. 8ns - 90
10ns - 75
Min Max
-2 2 µA
-5
CAPACITANCE*(TA=25°C, f=1.0MHz)
Item Symbol Test Conditions TYP Max Unit
Input/Output Capacitance C
Input Capacitance C
* Capacitance is sampled and not 100% tested.
I/O VI/O=0V - 8 pF
IN VIN=0V - 6 pF
Unit
- 4 -
Rev. 3.0
July 2004
K6R1004V1D
AC CHARACTERISTICS(TA=0 to 70°C, VCC=3.3±0.3V, unless otherwise noted.)
TEST CONDITIONS
Parameter Val ue
Input Pulse Levels 0V to 3V
Input Rise and Fall Times 3ns
Input and Output timing Reference Levels 1.5V
Output Loads See below
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Output Loads(A)
OUT
D
RL = 50Ω
VL = 1.5V
Z
O = 50Ω
* Capacitive Load consists of all components of the
test environment.
30pF*
READ CYCLE*
Parameter Symbol
Read Cycle Time t
Address Access Time t
Chip Select to Output t
Output Enable to Valid Output t
Chip Enable to Low-Z Output t
Output Enable to Low-Z Output t
Chip Disable to High-Z Output t
Output Disable to High-Z Output
Output Hold from Address Change t
Chip Selection to Power Up Time t
Chip Selection to Power DownTime t
* The above parameters are also guaranteed at industrial temperature range.
RC 8-10-ns
AA -8-10ns
CO -8-10ns
OE -4-5ns
LZ 3-3-ns
OLZ 0-0-ns
HZ 0405
t
OHZ
OH 3-3-
PU 0-0-
PD -8-10ns
K6R1004V1D-08 K6R1004V1D-10
Min Max Min Max
0405
Output Loads(B)
for t
HZ, tLZ, tWHZ, tOW, tOLZ & tOHZ
OUT
D
353Ω
* Including Scope and Jig Capacitance
+3.3V
319Ω
5pF*
Unit
ns
ns
ns
ns
- 5 -
Rev. 3.0
July 2004
K6R1004V1D
WRITE CYCLE*
Parameter Symbol
Write Cycle Time t
Chip Select to End of Write t
Address Set-up Time t
Address Valid to End of Write t
Write Pulse Width(OE
Write Pulse Width(OE
Write Recovery Time t
Write to Output High-Z t
Data to Write Time Overlap t
Data Hold from Write Time t
End of Write to Output Low-Z t
* The above parameters are also guaranteed at industrial temperature range.
High) tWP 6-7-ns
Low) tWP1 8-10-ns
WC 8-10-
CW 6-7-
AS 0-0-ns
AW 6-7-ns
WR 0-0-ns
WHZ 0405ns
DW 4-5-ns
DH 0-0-
OW 3-3-ns
K6R1004V1D-08 K6R1004V1D-10
Min Max Min Max
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Unit
ns
ns
ns
TIMING DIAGRAMS
TIMING WAVEFORM OF READ CYCLE(1) (Address Controlled, CS=OE=VIL, WE=VIH )
tRC
Address
tOH
Data Out
Previous Valid Data
TIMING WAVEFORM OF READ CYCLE(2) (WE=VIH)
Address
tAA
CS
OE
tOLZ
Data out
High-Z
tLZ(4,5)
tAA
tRC
tCO
tOE
Valid Data
tHZ(3,4,5)
tOHZ
tDH
Valid Data
VCC
Current
ICC
ISB
tPU
50%
- 6 -
tPD
50%
Rev. 3.0
July 2004
K6R1004V1D
NOTES(READ CYCLE)
1. WE
is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
HZ and tOHZ are defined as the time at which the outputs achieve the open circuit condition and are not referenced to VOH or
V
OL levels.
4. At any given temperature and voltage condition, t
device.
5. Transition is measured ±200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
TIMING WAVEFORM OF WRITE CYCLE(1) (OE= Clock)
Address
OE
=VIL.
PRELIMINARY
PRELIMINARY
HZ(Max.) is less than tLZ(Min.) both for a given device and from device to
tWC
tAW
tCW(3)
tWR(5)
for AT&T
CMOS SRAM
CS
tAS(4)
WE
Data in
Data out
High-Z
tOHZ(6)
TIMING WAVEFORM OF WRITE CYCLE(2) (OE=Low Fixed)
Address
CS
tAS(4)
WE
Data in
Data out
High-Z
tAW
tWHZ(6)
tWC
tCW(3)
tWP(2)
tWP1(2)
tDW tDH
Vali d D a ta
High-Z(8)
tDW tDH
Valid Data
High-Z(8)
tWR(5)
tOW
(10)
(9)
- 7 -
Rev. 3.0
July 2004
K6R1004V1D
TIMING WAVEFORM OF WRITE CYCLE(3) (CS=Controlled)
Address
CS
tAS(4)
WE
Data in
Data out
NOTES(WRITE CYCLE)
1. All write cycle timing is referenced from the last valid address to the first transition address.
2. A write occurs during the overlap of a low CS
A write ends at the earliest transition CS
write.
3. t
CW is measured from the later of CS going low to end of write.
4. t
AS is measured from the address valid to the beginning of write.
5. t
WR is measured from the end of write to the address change. tWR applied in case a write ends as CS or WE going high.
6. If OE
, CS and WE are in the Read Mode during this period, the I/O pins are in the output low-Z state. Inputs of opposite phase
of the output must not be applied because bus contention can occur.
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
goes low simultaneously with WE going or after WE going low, the outputs remain high impedance state.
8. If CS
9. Dout is the read data of the new address.
10.When CS
applied.
High-Z
tLZ
High-Z
going high or WE going high. tWP is measured from the beginning of write to the end of
is low : I/O pins are in the output state. The input signals in the opposite phase leading to the output should not be
PRELIMINARY
PRELIMINARY
tWC
tAW
tCW(3)
tWP(2)
tDW
Valid Data
tWHZ(6)
and WE. A write begins at the latest transition CS going low and WE going low ;
tWR(5)
tDH
for AT&T
CMOS SRAM
High-Z
High-Z(8)
FUNCTIONAL DESCRIPTION
CS WE OE Mode I/O Pin Supply Current
H X X* Not Select High-Z I
L H H Output Disable High-Z ICC
L H L Read DOUT ICC
LLX Write DIN ICC
* X means Don′t Care.
- 8 -
SB, ISB1
Rev. 3.0
July 2004
K6R1004V1D
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
PACKAGE DIMENSIONS
32-SOJ-400
#32
11. 18 ±0.12
0.440 ±0.005
#1
0.95
( )
0.0375
0.43
0.017
+0.10
-0.05
+0.004
-0.002
21.36
MAX
0.841
20.95 ±0.12
0.825 ±0.005
1.27
0.050
0.71
0.028
+0.10
-0.05
+0.004
-0.002
#17
#16
1.30
( )
0.051
1.30
( )
0.051
Units:millimeters/Inches
10.16
0.400
0.69
MIN
0.027
3.76
0.148
MAX
0.10
0.004
9.40 ±0.25
0.370 ±0.010
+0.10
0.20
+0.004
0.008
MAX
-0.05
-0.002
- 9 -
Rev. 3.0
July 2004
Loading...