SAMSUNG K6R1004V1D Technical data
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K6R1004V1D
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating)
Operated at Commercial and Industrial Temperature Ranges.
Revision History
PRELIMINARY
PRELIMINARY
for AT&T
CMOS SRAM
Rev. No.
Rev. 0.0
Rev. 0.1
Rev. 0.2
Rev. 1.0
Rev. 2.0
Rev. 3.0
History
Initial document.
Speed bin modify
Current modify
1. Final datasheet release
2. Delete 12ns speed bin.
3. Change Icc for Industrial mode.
I
CC(Industrial)
1. Delete UB
1. Add the Lead Free Package type.
Item Previous Current
8ns 100mA 90mA
10ns 85mA 75mA
,LB releated timing diagram.
Draft Data
May. 11. 2001
June. 18. 2001
September. 9. 2001
December. 18. 2001
June. 19. 2002
July. 26, 2004
Remark
Preliminary
Preliminary
Preliminary
Final
Final
Final
The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the
specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 -
Rev. 3.0
July 2004
PRELIMINARY
PRELIMINARY
K6R1004V1D
1Mb Async. Fast SRAM Ordering Information
Org. Part Number VDD(V) Speed ( ns ) PKG Temp. & Power
for AT&T
CMOS SRAM
256K x4
128K x8
64K x16
K6R1004C1D-J(K)C(I) 10 5 10
K6R1004V1D-J(K)C(I) 08/10 3.3 8/10
K6R1008C1D-J(K,T,U)C(I) 10 5 10
K6R1008V1D-J(K,T,U)C(I) 08/10 3.3 8/10
K6R1016C1D-J(K,T,U,E)C(I) 10 5 10
K6R1016V1D-J(K,T,U,E)C(I) 08/10
3.3 8/10
J : 32-SOJ
K: 32-SOJ(LF)
J : 32-SOJ
K : 32-SOJ(LF)
T : 32-TSOP2
U : 32-TSOP2(LF)
J : 44-SOJ
K : 44-SOJ(LF)
T : 44-TSOP2
U : 44-TSOP2(LF)
E : 48-TBGA
C : Commercial Temperature
,Normal Power Range
I : Industrial Temperature
,Normal Power Range
- 2 -
Rev. 3.0
July 2004
PRELIMINARY
PRELIMINARY
K6R1004V1D
256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
GENERAL DESCRIPTIONFEATURES
• Fast Access Time 8,10ns(Max.)
• Low Power Dissipation
Standby (TTL) : 20mA(Max.)
(CMOS) : 5mA(Max.)
Operating //K6R1004V1D-08: 80mA(Max.)
K6R1004V1D-10: 65mA(Max.)
• Single 3.3±0.3V Power Supply
• TTL Compatible Inputs and Outputs
• Fully Static Operation
- No Clock or Refresh required
• Three State Outputs
• Center Power/Ground Pin Configuration
• Standard Pin Configuration :
K6R1004V1D-J : 32-SOJ-400
K6R1004V1D-K : 32-SOJ-400 (Lead-Free)
• Operating in Commercial and Industrial Temperature range.
The K6R1004V1D is a 1,048,576-bit high-speed Static Random
Access Memory organized as 262,144 words by 4 bits.
The K6R1004V1D uses 4 common input and output lines and
has an output enable pin which operates faster than address
access time at read cycle. The device is fabricated using
SAMSUNG′s advanced CMOS process and designed for
high-speed circuit technology. It is particularly well suited for
use in high-density high-speed system applications. The
K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
PIN CONFIGURATION(Top View)
for AT&T
CMOS SRAM
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A5
A6
A7
A8
I/O1 ~ I/O4
CS
WE
OE
Clk Gen.
Row Select
Data
Cont.
CLK
Gen.
Pre-Charge Circuit
Memory Array
512 Rows
512x4 Columns
I/O Circuit &
Column Select
A10 A11 A12 A13 A14 A15
A9 A16 A17
1
N.C
2
0
A
A1
3
A2
4
A3
5
CS
6
I/O1
7
Vcc
Vss
I/O
WE
A4
A5
A6
A7
N.C
8
9
2
10
11
12
13
14
15
16
SOJ
PIN FUNCTION
Pin Name Pin Function
0 - A17 Address Inputs
A
WE Write Enable
CS
OE
1 ~ I/O4 Data Inputs/Outputs
I/O
CC Power(+3.3V)
V
V
SS Ground
N.C No Connection
Chip Select
Output Enable
17
A
32
A16
31
A15
30
A14
29
A13
28
OE
27
I/O4
26
Vss
25
Vcc
24
3
I/O
23
A12
22
A11
21
A10
20
A9
19
A8
18
N.C
17
- 3 -
Rev. 3.0
July 2004
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