SAMSUNG K6R1004V1D Technical data
K6R1004C1D-JC10
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PRELIMINARY |
K6R1004V1D |
for AT&T |
CMOS SRAM |
Document Title
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
Revision History
Rev.No. |
History |
Rev. 0.0 |
Initial document. |
Rev. 0.1 |
Speed bin modify |
Rev. 0.2 |
Current modify |
Rev. 1.0 1. Final datasheet release
2.Delete 12ns speed bin.
3.Change Icc for Industrial mode.
Item |
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Previous |
Current |
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ICC(Industrial) |
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8ns |
100mA |
90mA |
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10ns |
85mA |
75mA |
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Draft Data |
Remark |
May. 11. 2001 |
Preliminary |
June. 18. 2001 |
Preliminary |
September. 9. 2001 |
Preliminary |
December. 18. 2001 |
Final |
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Rev. 2.0 |
1. |
Delete UB,LB releated timing diagram. |
June. 19. 2002 |
Final |
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Rev. 3.0 |
1. |
Add the Lead Free Package type. |
July. 26, 2004 |
Final |
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The attached data sheets are prepared and approved by SAMSUNG Electronics. SAMSUNG Electronics CO., LTD. reserve the right to change the specifications. SAMSUNG Electronics will evaluate and reply to your requests and questions on the parameters of this device. If you have any questions, please contact the SAMSUNG branch office near your office, call or contact Headquarters.
- 1 - |
Rev. 3.0 |
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July 2004 |
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PRELIMINARY |
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K6R1004V1D |
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for AT&T |
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CMOS SRAM |
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1Mb Async. Fast SRAM Ordering Information |
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Org. |
Part Number |
VDD(V) |
Speed ( ns ) |
PKG |
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Temp. & Power |
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256K x4 |
K6R1004C1D-J(K)C(I) 10 |
5 |
10 |
J : 32-SOJ |
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K6R1004V1D-J(K)C(I) 08/10 |
3.3 |
8/10 |
K: 32-SOJ(LF) |
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K6R1008C1D-J(K,T,U)C(I) 10 |
5 |
10 |
J : 32-SOJ |
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C : Commercial Temperature |
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128K x8 |
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K : 32-SOJ(LF) |
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,Normal Power Range |
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K6R1008V1D-J(K,T,U)C(I) 08/10 |
3.3 |
8/10 |
T : 32-TSOP2 |
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I : Industrial Temperature |
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U : 32-TSOP2(LF) |
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,Normal Power Range |
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K6R1016C1D-J(K,T,U,E)C(I) 10 |
5 |
10 |
J : 44-SOJ |
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64K x16 |
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K : 44-SOJ(LF) |
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K6R1016V1D-J(K,T,U,E)C(I) 08/10 |
3.3 |
8/10 |
T : 44-TSOP2 |
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U : 44-TSOP2(LF) |
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E : 48-TBGA |
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- 2 - |
Rev. 3.0 |
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July 2004 |
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PRELIMINARY |
K6R1004V1D |
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for AT&T |
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CMOS SRAM |
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256K x 4 Bit (with OE) High-Speed CMOS Static RAM(3.3V Operating)
FEATURES
•Fast Access Time 8,10ns(Max.)
•Low Power Dissipation
Standby (TTL) : 20mA(Max.) (CMOS) : 5mA(Max.)
Operating K6R1004V1D-08: 80mA(Max.) K6R1004V1D-10: 65mA(Max.)
•Single 3.3±0.3V Power Supply
•TTL Compatible Inputs and Outputs
•Fully Static Operation
-No Clock or Refresh required
•Three State Outputs
•Center Power/Ground Pin Configuration
•Standard Pin Configuration :
K6R1004V1D-J : 32-SOJ-400 K6R1004V1D-K : 32-SOJ-400 (Lead-Free)
• Operating in Commercial and Industrial Temperature range.
GENERAL DESCRIPTION
The K6R1004V1D is a 1,048,576-bit high-speed Static Random Access Memory organized as 262,144 words by 4 bits.
The K6R1004V1D uses 4 common input and output lines and has an output enable pin which operates faster than address access time at read cycle. The device is fabricated using SAMSUNG′s advanced CMOS process and designed for high-speed circuit technology. It is particularly well suited for use in high-density high-speed system applications. The K6R1004V1D is packaged in a 400 mil 32-pin plastic SOJ.
FUNCTIONAL BLOCK DIAGRAM
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Clk Gen. |
Pre-Charge Circuit |
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A0 |
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A1 |
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A2 |
Select |
512 Rows |
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A4 |
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A3 |
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Memory Array |
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A5 |
Row |
512x4 Columns |
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A6 |
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A7 |
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A8 |
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I/O1 ~ I/O4 |
Data |
I/O Circuit & |
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Cont. |
Column Select |
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CLK
Gen.
A9 A10 A11 A12 A13 A14 A15 A16 A17
CS
WE 
OE
PIN CONFIGURATION(Top View)
N.C |
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A17 |
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1 |
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32 |
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A0 |
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A16 |
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2 |
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31 |
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A1 |
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A15 |
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3 |
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30 |
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A2 |
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A14 |
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4 |
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29 |
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A3 |
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A13 |
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5 |
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28 |
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CS |
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6 |
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27 |
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OE |
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I/O1 |
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I/O4 |
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7 |
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26 |
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Vcc |
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Vss |
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8 |
SOJ |
25 |
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Vss |
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Vcc |
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9 |
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24 |
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I/O2 |
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I/O3 |
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10 |
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23 |
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A12 |
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WE |
11 |
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22 |
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A4 |
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A11 |
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12 |
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21 |
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A5 |
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A10 |
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13 |
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20 |
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A6 |
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A9 |
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14 |
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19 |
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A7 |
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A8 |
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15 |
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18 |
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N.C |
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N.C |
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16 |
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17 |
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PIN FUNCTION
Pin Name |
Pin Function |
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A0 - A17 |
Address Inputs |
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Write Enable |
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WE |
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Chip Select |
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CS |
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Output Enable |
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OE |
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I/O1 ~ I/O4 |
Data Inputs/Outputs |
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VCC |
Power(+3.3V) |
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VSS |
Ground |
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N.C |
No Connection |
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- 3 - |
Rev. 3.0 |
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July 2004 |
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