Datasheet K4S643232F Datasheet (SAMSUNG)

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K4S643232F CMOS SDRAM

2M x 32 SDRAM

512K x 32bit x 4 Banks

Synchronous DRAM

LVTTL

Revision 1.0

January 2002

Samsung Electronics reserves the right to change products or specification without notice.

- 1 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

Revision History

Revision 1.0 (January 16, 2002)

• Defined DC spec.

Revision 0.1 (September 03, 2001) - Preliminary

• Added K4S643232F-TC/L55

Revision 0.0 (September 03, 2001) - Target Spec

• Initial draft

- 2 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

512K x 32Bit x 4 Banks Synchronous DRAM

GENERAL DESCRIPTIONFEATURES

• 3.3V power supply

• LVTTL compatible with multiplexed address

• Four banks operation

• MRS cycle with address key programs

-. CAS latency ( 2 & 3)

-. Burst length (1, 2, 4, 8 & Full page)

-. Burst type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system
clock

• Burst read single-bit write operation

• DQM for masking

• Auto & self refresh

• 15.6us refresh duty cycle

The K4S643232F is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technol­ogy. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.

ORDERING INFORMATION

Part NO. Max Freq. Interface Package

K4S643232F-TC/L45 222MHz
K4S643232F-TC/L50 200MHz
K4S643232F-TC/L55 183MHz
K4S643232F-TC/L60 166MHz
K4S643232F-TC/L70 143MHz

LVTTL

86

TSOP(II)

FUNCTIONAL BLOCK DIAGRAM

Bank Select

Refresh Counter

Row Buffer

Address Register

CLK

ADD

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

Data Input Register

Row Decoder Col. Buffer

LCAS LWCBR

512K x 32
512K x 32
512K x 32
512K x 32

Column Decoder

Latency & Burst Length

Programming Register

LWE

LDQM

Sense AMP

Output BufferI/O Control

DQi

Timing Register

CLK CKE CS RAS CAS WE DQM

- 3 -

Samsung Electronics reserves the right to

*

change products or specification without
notice.

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

PIN CONFIGURATION (Top view)

VDD

DQ0

VDDQ

DQ1
DQ2

VSSQ

DQ3
DQ4

VDDQ

DQ5
DQ6

VSSQ

DQ7

N.C
VDD

DQM0

WE
CAS
RAS

CS

N.C
BA0
BA1

A10/AP

A0
A1
A2

DQM2

VDD

N.C

DQ16

VSSQ
DQ17
DQ18

VDDQ
DQ19
DQ20

VSSQ
DQ21
DQ22

VDDQ

DQ23

VDD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43

86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44

VSS
DQ15
VSSQ
DQ14
DQ13
VDDQ
DQ12
DQ11
VSSQ
DQ10
DQ9
VDDQ
DQ8
N.C
VSS
DQM1
N.C
N.C
CLK
CKE
A9
A8
A7
A6
A5
A4
A3
DQM3
VSS
N.C
DQ31
VDDQ
DQ30
DQ29
VSSQ
DQ28
DQ27
VDDQ
DQ26
DQ25
VSSQ
DQ24
VSS

86Pin TSOP (II)

(400mil x 875mil)

(0.5 mm Pin pitch)

- 4 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

PIN FUNCTION DESCRIPTION

Pin Name Input Function

CLK System clock Active on the positive going edge to sample all inputs.
CS Chip select

CKE Clock enable

A0 ~ A10 Address

BA0,1 Bank select address

RAS Row address strobe

CAS Column address strobe

WE Write enable

DQM0 ~ 3 Data input/output mask

DQ0 ~ 31 Data input/output Data inputs/outputs are multiplexed on the same pins.
VDD/VSS Power supply/ground Power and ground for the input buffers and the core logic.

VDDQ/VSSQ Data output power/ground

NC No Connection This pin is recommended to be left No connection on the device.

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.

Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.

Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.

Enables write operation and row precharge.
Latches data in starting from CAS, WE active.

Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

- 5 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss VIN, VOUT -1.0 ~ 4.6 V
Voltage on VDD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V
Storage temperature TSTG -55 ~ +150 °C
Power dissipation PD 1 W
Short circuit current IOS 50 mA

Note :

Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage VDD, VDDQ 3.0 3.3 3.6 V
Input logic high voltage VIH 2.0 3.0 VDDQ+0.3 V 1
Input logic low voltage VIL -0.3 0 0.8 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 - 10 uA 3

Notes :

1. VIH (max) = 5.6V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ,
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.

4. The VDD condition of K4S643232F-45/50/55/60 is 3.135V ~ 3.6V

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock CCLK - 4 pF
RAS, CAS, WE, CS, CKE, DQM CIN - 4.5 pF
Address CADD - 4.5 pF
DQ0 ~ DQ31 COUT - 6.5 pF

- 6 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, TA = 0 to 70°C, VIH(min)/VIL(max)=2.0V/0.8V)

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby Current in
power-down mode

Precharge Standby Current
in non power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down mode
(One Bank Active)

Operating Current
(Burst Mode)

Refresh Current ICC5 tRC ≥ tRC(min)

Self Refresh Current ICC6 CKE ≤ 0.2V

ICC1

ICC2P CKE ≤ VIL(max), tCC = 15ns 2
ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 2

ICC2N

ICC2NS

ICC3P CKE ≤ VIL(max), tCC = 15ns 4
ICC3PS CKE ≤ VIL(max), tCC = ∞ 4

ICC3N

ICC3NS

ICC4

Burst Length =1
tRC ≥ tRC(min), tCC ≥ tCC(min), Io = 0mA

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 15ns
Input signals are changed one time during 30ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

Io = 0 mA, Page Burst
All bank Activated, tCCD = tCCD(min)

CAS

Latency

-45 -50 -55 -60 -70

3 140 140 140 130 130
2 110

3 180 170 160 150 140
2 120
3 150 150 150 140 120
2 120

Speed

12

7

40

35

2 mA 4

450 uA 5

Unit Note

mA 2

mA

mA

mA

mA

mA 2

mA 3

Notes :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

2. Measured with outputs open.

3. Refresh period is 64ms.

4. K4S643232F-TC**

5. K4S643232F-TL**

- 7 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V ± 0.3V, TA = 0 to 70°C)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4/0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

Output

Notes :

3.3V

1200Ω

VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA

870Ω

1. The VDD condition of K4S643232F-45/50/55/60 is 3.135V ~ 3.6V

30pF

Output

Z0 = 50Ω

(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit

Vtt = 1.4V

50Ω

30pF

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

CAS Latency CL 3 2 3 2 3 2 3 2 3 2 CLK
CLK cycle time tCC(min) 4.5 10 5 10 5.5 10 6 10 7 10 ns
Row active to row active delay tRRD(min) 2 CLK 1
RAS to CAS delay tRCD(min) 4 2 3 2 3 2 3 2 3 2 CLK 1
Row precharge time tRP(min) 4 2 3 2 3 2 3 2 3 2 CLK 1

Row active time
Row cycle time

Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to new col.address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 3
Mode Register Set cycle time tMRS(min) 2 CLK

Number of valid
output data

CAS Latency=3 2
CAS Latency=2 1

tRAS(min) 9 5 8 5 7 5 7 5 7 5 CLK 1

tRAS(max) 100 us

tRC(min) 13 7 11 7 10 7 10 7 10 7 CLK 1

-45 -50 -55 -60 -70

Version

Unit Note

ea 4

Note :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.

- 8 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

Parameter Symbol

Row active to row active delay tRRD(min) 9 10 11 12 14 ns
RAS to CAS delay tRCD(min) 18 15 16.5 18 20 ns
Row precharge time tRP(min) 18 15 16.5 18 20 ns

Row active time
Row cycle time tRC(min) 58.5 55 55 60 70 ns

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

tRAS(min) 40.5 40 38.5 42 49 ns
tRAS(max) 100 us

-45 -50 -55 -60 -70

Version

Unit

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol

CLK cycle time

CLK to valid
output delay

Output data hold time tOH 2 - 2 - 2 - 2 - 2 - ns 2
CLK high pulse

width

CLK low
pulse width

Input setup time

Input hold time tSH 1 - 1 - 1 - 1 - 1 - ns 3
CLK to output in Low-Z tSLZ 1 - 1 - 1 - 1 - 1 - ns 2

CLK to output
in Hi-Z

CAS Latency=3
CAS Latency=2 10 10 10 10 10
CAS Latency=3
CAS Latency=2 - 6 - 6 - 6 - 6 - 6

CAS Latency=3
CAS Latency=2 3 - 3 - 3 - 3 - 3 ­CAS Latency=3
CAS Latency=2 3 - 3 - 3 - 3 - 3 ­CAS Latency=3
CAS Latency=2 2.5 - 2.5 - 2.5 - 2.5 - 2.5 -

CAS latency=3
CAS latency=2 - 6 - 6 - 6 - 6 - 6

tCC

tSAC

tCH

tCL

tSS

tSHZ

-45 -50 -55 -60 -70

Min Max Min Max Min Max Min Max Min Max

4.5
1000

- 4.0 - 4.5 - 5.0 - 5.5 - 5.5

1.75 - 2 - 2 - 2.5 - 3 -

1.75 - 2 - 2 - 2.5 - 3 -

1.2 - 1.5 - 1.5 - 1.5 - 1.75 -

- 4.0 - 4.5 - 5.0 - 5.5 - 5.5

5

1000

5.5
1000

6

1000

7

1000 ns 1

Unit Note

ns 1, 2

ns 3

ns 3

ns 3

ns -

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

- 9 -

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

SIMPLIFIED TRUTH TABLE

Command CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP

,

A9 ~ A0

Note

Register Mode register set H X L L L L X OP code 1,2

Refresh

Auto refresh

Self
refresh

Entry L 3

H

Exit L H

H

L L L H X X

L H H H

X X

3

3

H X X X 3
Bank active & row addr. H X L L H H X V Row address
Read &

column address

Write &
column address

Auto precharge disable

H X L H L H X V

L
Auto precharge enable H 4,5
Auto precharge disable

H X L H L L X V

L
Auto precharge enable H 4,5

Column
address

(A0 ~ A7)

Column
address

(A0 ~ A7)

4

4

Burst Stop H X L H H L X X 6

Precharge

Bank selection

H X L L H L X

V L

X

All banks X H

Clock suspend or
active power down

Entry H L

H X X X

L V V V

X

X

Exit L H X X X X X

Entry H L

Precharge power down mode

Exit L H

H X X X

L H H H

H X X X

X

X

X

L V V V

DQM H V X 7

No operation command H X

X

H X X X

X X

L H H H

(V=Valid, X=Don′t care, H=Logic high, L=Logic low)

Notes :

1. OP Code : Operand code
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.

4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

- 10

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address
Function

A8 A7 A6 A5 A4 A3 A2 A1 A0 BT = 0

A9

BA0 ~ BA1

RFU

Test Mode

0
0
1
1

0
1

0
1
0
1

Write Burst Length

A10/AP

RFU

Type

Mode Register Set

Reserved
Reserved
Reserved

Length

Burst

Single Bit

A9

W.B.L

0
0
0
0
1
1
1
1

A8 A7

TM

CAS Latency

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

A6 A5 A4 A3 A2 A1 A0

CAS Latency BT Burst Length

Latency
Reserved
Reserved

2

3
Reserved
Reserved
Reserved
Reserved

Burst Type

0

Sequential

1

Interleave

Type

0
0
0
0
1
1
1
1

Burst Length

0

0

0

1

1

0

1

1
0
0
1
1

Full Page Length : x32 (256)

Reserved

0

Reserved

1

Reserved

0

Full Page

1

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.

1
2
4
8

BT = 1

1
2
4

8
Reserved
Reserved
Reserved
Reserved

The device is now ready for normal operation.

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

- 11

Rev. 1.0 (Jan. 2002)

K4S643232F CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

A1 A0

0
0
1
1

0
1
0
1

0
1
2
3

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

A1 A0A2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0
1
0
1
0
1
0
1

0

1

1

2

2

3

3

4

4

5

5

6

6

7

7

0

Sequential Interleave

1
2
3
0

Sequential Interleave

2

3

3

4

4

5

5

6

6

7

7

0

0

1

1

2

2
3
0
1

4

5

5

6

6

7

7

0

0

1

1

2

2

3

3

4

3
0
1
2

6

7

7

0

0

1

1

2

2

3

3

4

4

5

5

6

0
1
2
3

0
1
2
3
4
5
6
7

2

1

3

0

0

3

1

2

6

5

7

4

4

7

5

6

1
0
3
2

3
2
1
0
7
6
5
4

2
3
0
1

4

5

5

4

6

7

7

6

0

1

1

0

2

3

3

2

3
2
1
0

6

7

7

6

4

5

5

4

2

3

3

2

0

1

1

0

- 12

Rev. 1.0 (Jan. 2002)