Samsung Electronics reserves the right to change products or specification without notice.
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REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
Revision History
Revision 1.1 (November 17th, 1999)
• Corrected typo in ordering information on page 3
Revision 1.0 (October, 1999)
• Changed part number from KM432S2030CT-G/F to K4S643232C-TC/TL according to re-organized code system
- 2 -
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
512K x 32Bit x 4 Banks Synchronous DRAM
GENERAL DESCRIPTIONFEATURES
• 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 15.6us refresh duty cycle
The K4S643232C is 67,108,864 bits synchronous high data
rate Dynamic RAM organized as 4 x 524,288 words by 32 bits,
fabricated with SAMSUNG′s high performance CMOS technology. Synchronous design allows precise cycle control with the
use of system clock. I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst length and programmable latencies allow the same device
to be useful for a variety of high bandwidth, high performance
memory system applications.
CLKSystem clockActive on the positive going edge to sample all inputs.
CSChip select
CKEClock enable
A0 ~ A10Address
BA0,1Bank select address
RASRow address strobe
CASColumn address strobe
WEWrite enable
DQM0 ~ 3Data input/output mask
DQ0 ~ 31Data input/outputData inputs/outputs are multiplexed on the same pins.
VDD/VSSPower supply/groundPower and ground for the input buffers and the core logic.
VDDQ/VSSQData output power/ground
NCNo ConnectionThis pin is recommended to be left No connection on the device.
Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and DQM.
Masks system clock to freeze operation from the next clock cycle.
CKE should be enabled at least one cycle prior to new command.
Disables input buffers for power down mode.
Row/column addresses are multiplexed on the same pins.
Row address : RA0 ~ RA10, Column address : CA0 ~ CA7
Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK with CAS low.
Enables column access.
Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tSHZ after the clock and masks the output.
Blocks data input when DQM active.
Isolated power supply and ground for the output buffers to provide improved noise
immunity.
ABSOLUTE MAXIMUM RATINGS
ParameterSymbolValueUnit
Voltage on any pin relative to VssVIN, VOUT-1.0 ~ 4.6V
Voltage on VDD supply relative to VssVDD, VDDQ-1.0 ~ 4.6V
Storage temperatureTSTG-55 ~ +150°C
Power dissipationPD1W
Short circuit currentIOS50mA
Note :
Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF = 1.4V ± 200mV)
(Fig. 2) AC output load circuit (Fig. 1) DC output load circuit
Vtt = 1.4V
50Ω
*1
50pF
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
ParameterSymbol
CAS LatencyCL3232323232CLK
CLK cycle timetCC(min)5.5-6-7-8101012ns
Row active to row active delaytRRD(min)2CLK1
RAS to CAS delaytRCD(min)3-3-3-3222CLK1
Row precharge timetRP(min)3-3-3-3222CLK1
Row active time
Row cycle time
Row cycle time in Auto refreshtRFC(min)12-12-10-9776CLK1,6
Last data in to row prechargetRDL(min)2CLK2, 5
Last data in to new col.address delaytCDL(min)1CLK2
Last data in to burst stoptBDL(min)1CLK2
Col. address to col. address delaytCCD(min)1CLK
Mode Register Set cycle timetMRS(min)2CLK
Number of valid output data
CAS Latency=32
CAS Latency=21
tRAS(min)7-7-7-6554CLK1
tRAS(max)100us
tRC(min)10-10-10-9776CLK1
-55-60-70-80-10
Version
UnitNote
ea4
Note :
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then
rounding off to the next higher integer. Refer to the following ns-unit based AC table.
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REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
ParameterSymbol
CLK cycle timetCC(min)5.567810ns
Row active to row active delaytRRD(min)1112141620ns
RAS to CAS delaytRCD(min)16.518212020ns
Row precharge timetRP(min)16.518212020ns
Row active time
Row cycle timetRC(min)5560707070ns
Row cycle time in Auto refreshtRFC(min)6672707070ns
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket
code "NV". From the next generation, tRDL will be only 2CLK for every clock frequency.
6. A new command should be issued after self refersh exit followed by tRFC.
tRAS(min)38.542494848ns
tRAS(max)100us
-55-60-70-80-10
Version
Unit
AC CHARACTERISTICS (AC operating conditions unless otherwise noted)
ParameterSymbol
CLK cycle time
CLK to valid
output delay
Output datatOH2-2.5-2.5-2.5 -2.5- ns2
CLK high pulse width
CLK low pulse width
Input setup time
Input hold timetSH1-1-1-1-1- ns3
CLK to output in Low-ZtSLZ1-1-1-1-1-ns2
CLK to output
in Hi-Z
CAS Latency=3
CAS Latency=2---1012
CAS Latency=3
CAS Latency=2-------6 -8
CAS Latency=3
CAS Latency=2-CAS Latency=3
CAS Latency=2-CAS Latency=3
CAS Latency=2--
CAS Latency=3
CAS Latency=2------- 6-8
tCC
tSAC
tCH
tCL
tSS
tSHZ
-55-60-70-80-10
MinMaxMinMaxMinMaxMinMax MinMax
5.5
1000
-5-5.5-5.5-6-6
2-2.5
2-2.5
1.5-1.5
-5-5.5-5.5 -6-6
6
1000
-
-
-
7
1000
-3-3-3.5-ns3
-3-3-3.5-ns3
1.75
-
-
8
-2-2.5-ns3
1000
10
1000ns1
Unit Note
ns1, 2
ns
Note :
1. Parameters depend on programmed CAS latency.
2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.
3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.
- 8 -
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
SIMPLIFIED TRUTH TABLE
CommandCKEn-1CKEnCSRASCASWEDQMBA0,1A10/AP
RegisterMode register setHXLLLLXOP code1,2
Auto refresh
Refresh
Bank active & row addr.HXLLHHXVRow address
Read &
column address
Write &
column address
Burst StopHXLHHLXX6
Precharge
Clock suspend or
active power down
Precharge power down mode
DQMHVX7
No operation commandHX
(V=Valid, X=Don′t care, H=Logic high, L=Logic low)
Notes :
1. OP Code : Operand code
A0 ~ A10 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Self
refresh
Auto precharge disable
Auto precharge enableH4,5
Auto precharge disable
Auto precharge enableH4,5
Bank selection
All banksXH
EntryL3
ExitLH
EntryHL
ExitLHXXXXX
EntryHL
ExitLH
H
HXLHLHXV
HXLHLLXV
HXLLHLX
H
LLLHXX
LHHH
HXXX3
HXXX
LVVV
HXXX
LHHH
HXXX
LVVV
X
HXXX
LHHH
XX
L
L
VL
X
X
X
X
X
XX
,
A9 ~ A0
Column
address
(A0 ~ A7)
Column
address
(A0 ~ A7)
X
Note
3
3
4
4
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REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
MODE REGISTER FIELD TABLE TO PROGRAM MODES
Register Programmed with MRS
Address
Function
A8A7A6A5A4A3A2A1A0BT = 0
A9
BA0 ~ BA1
RFU
Test Mode
0
0
1
1
0
1
0
1
0
1
Write Burst Length
A10/AP
RFU
Type
Mode Register Set
Reserved
Reserved
Reserved
Length
Burst
Single Bit
A9
W.B.L
0
0
0
0
1
1
1
1
A8A7
TM
CAS Latency
0
0
0
1
1
0
1
1
0
0
0
1
1
0
1
1
A6A5A4A3A2A1A0
CAS LatencyBTBurst Length
Latency
Reserved
Reserved
2
3
Reserved
Reserved
Reserved
Reserved
Burst Type
0
Sequential
1
Interleave
Type
0
0
0
0
1
1
1
1
Burst Length
0
0
0
1
1
0
1
1
0
0
1
1
Full Page Length : x32 (256)
Reserved
0
Reserved
1
Reserved
0
Full Page
1
POWER UP SEQUENCE
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.
3. Issue precharge commands for all banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.
1
2
4
8
BT = 1
1
2
4
8
Reserved
Reserved
Reserved
Reserved
The device is now ready for normal operation.
Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.
2. RFU (Reserved for future use) should stay "0" during MRS cycle.
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REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
BURST SEQUENCE (BURST LENGTH = 4)
Initial Address
A1A0
0
0
1
1
0
1
0
1
0
1
2
3
BURST SEQUENCE (BURST LENGTH = 8)
Initial Address
A1A0A2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
1
2
2
3
3
4
4
5
5
6
6
7
7
0
SequentialInterleave
1
2
3
0
SequentialInterleave
2
3
3
4
4
5
5
6
6
7
7
0
0
1
1
2
2
3
0
1
4
5
5
6
6
7
7
0
0
1
1
2
2
3
3
4
3
0
1
2
6
7
7
0
0
1
1
2
2
3
3
4
4
5
5
6
0
1
2
3
0
1
2
3
4
5
6
7
2
1
3
0
0
3
1
2
6
5
7
4
4
7
5
6
1
0
3
2
3
2
1
0
7
6
5
4
2
3
0
1
4
5
5
4
6
7
7
6
0
1
1
0
2
3
3
2
3
2
1
0
6
7
7
6
4
5
5
4
2
3
3
2
0
1
1
0
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REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
DEVICE OPERATIONS
CLOCK (CLK)
The clock input is used as the reference for all SDRAM operations. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
VIL and VIH. During operation with CKE high all inputs are
assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and ICC specifications.
CLOCK ENABLE (CKE)
The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are thesame as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is frozen as long as the CKE remains low. All other inputs are ignored
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + tSS" before the high going edge
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.
NOP and DEVICE DESELECT
When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than single clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS high. CS high disables the command decoder so that RAS,
CAS, WE and all the address inputs are ignored.
POWER-UP
SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.
1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.
2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.
3. Issue precharge commands for both banks of the devices.
4. Issue 2 or more auto-refresh commands.
5. Issue a mode register set command to initialize the mode reg ister.
cf.) Sequence of 4 & 5 is regardless of the order.
BANK ADDRESSES (BA0 ~ BA1)
This SDRAM is organized as four independent banks of 524,288
words x 32 bits memory arrays. The BA0 ~ BA1 inputs are
latched at the time of assertion of RAS and CAS to select the
bank to be used for the operation. The bank addresses BA0 ~
BA1 are latched at bank active, read, write, mode register set
and precharge operations.
ADDRESS INPUTS (A0 ~ A10)
The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A0 ~ A10).
The 11 bit row addresses are latched along with RAS and BA0 ~
BA1 during bank activate command. The 8 bit column addresses
are latched along with CAS, WE and BA0 ~ BA1 during read or
write command.
The device is now ready for normal operation.
- 12
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
DEVICE OPERATIONS (Continued)
MODE REGISTER SET (MRS)
The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS,
RAS, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A0 ~ A10 and BA0 ~ BA1 in the same cycle as CS,
RAS, CAS and WE going low is the data written in the mode
register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A0 ~ A2, burst type uses
A3, CAS latency (read latency from column address) use A4 ~
A6, vendor specific options or test mode use A7 ~ A8, A10/AP
and BA0 ~ BA1. The write burst length is programmed using A9.
A7 ~ A8, A10/AP and BA0 ~ BA1 must be set to low for normal
SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies.
BANK ACTIVATE
The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS and CS with desired row
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of tRCD(min) from the time
of bank activation. tRCD is an internal timing parameter of
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing tRCD(min) with cycle time of the clock and then rounding
off the result to the next higher integer. The SDRAM has four
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of four banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before another bank can be sensed
reliably. tRRD(min) specifies the minimum time required between
activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to
tRCD specification. The minimum time required for the bank to be
active to initiate sensing and restoring the complete row of
dynamic cells is determined by tRAS(min). Every SDRAM bank
activate command must satisfy tRAS(min) specification before a
precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by tRAS(max). The number of cycles for both tRAS(min) and
tRAS(max) can be calculated similar to tRCD specification.
BURST READ
The burst read command is used to access burst of data on consecutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS and CAS
with WE being high on the positive edge of the clock. The bank
must be active for at least tRCD(min) before the burst read command is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read command is determined by the mode register which is already programmed. The burst read can be initiated on any column
address of the active row. The address wraps around if the initial
address does not start from a boundary such that number of outputs from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.
BURST WRITE
The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS, CAS and WE with valid
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be completed yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank tRDL after the
last data input to be written into the active row. See DQM
OPERATION also.
- 13
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
DEVICE OPERATIONS (Continued)
DQM OPERATION
The DQM is used to mask input and output operations. It works
similar to OE during read operation and inhibits writing during
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.
PRECHARGE
The precharge operation is performed on an active bank by
asserting low on CS, RAS, WE and A10/AP with valid BA0 ~ BA1
of the bank to be precharged. The precharge command can be
asserted anytime after tRAS(min) is satisfied from the bank active
command in the desired bank. tRP is defined as the minimum
number of clock cycles required to complete row precharge is
calculated by dividing tRP with clock cycle time and rounding up
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by tRAS(max). Therefore, each
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when all banks are in idle state.
AUTO PRECHARGE
The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
tRAS(min) and "tRP" for the programmed burst length and CAS
latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A10/AP. If
burst read or burst write by asserting high on A10/AP, the bank is
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.
BOTH BANKS PRECHARGE
Both banks can be precharged at the same time by using Precharge all command. Asserting low on CS, RAS, and WE with
high on A10/AP after all banks have satisfied tRAS(min) requirement, performs precharge on all banks. At the end of tRP after
performing precharge to all the banks, both banks are in idle
state.
AUTO REFRESH
The storage cells of SDRAM need to be refreshed every 64ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS,
RAS and CAS with high on CKE and WE. The auto refresh command can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by tRFC(min). The minimum number of
clock cycles required can be calculated by driving tRFC with
clock cycle time and them rounding up to the next higher integer.
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. All banks will be in the idle
state at the end of auto refresh operation. The auto refresh is the
preferred refresh mode when the SDRAM is being used for normal data transactions. The auto refresh cycle can be performed
once in 15.6us or a burst of 4096 auto refresh cycles once in
64ms.
SELF REFRESH
The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from all banks idle state by
asserting low on CS, RAS, CAS and CKE with high on WE.
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of tRFC before the SDRAM reaches idle state to
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 4096
auto refresh cycles immediately after exiting in self refresh
mode.
- 14
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
BASIC FEATURE AND FUNCTION DESCRIPTIONS
1. CLOCK Suspend
1) Clock Suspended During Write (BL=4
CLK
CMD
CKE
Internal
CKE
DQ(CL2)
DQ(CL3)
2. DQM Operation
1) Write Mask (BL=4)
CLK
CMD
DQM
DQ(CL2)
DQ(CL3)
WR
Masked by CKE
D0D1D2D3
D0D1D2D3
Not Written
WR
Masked byDQM
D0D1D3
D0D1D3
2) Clock Suspended During Read (BL=4)
RD
Masked by CKE
D0
Q0Q1Q2
Q0Q1
Suspended Dout
2) Read Mask (BL=4)
RD
Masked by DQM
Hi-Z
Q0Q2Q3
Hi-Z
Q1
Q3
Q2Q3
Q2Q3
DQM to Data-in Mask = 0DQM to Data-out Mask = 2
3) DQM with Clock Suspended (Full Page Read)
CLK
CMD
CKE
DQM
DQ(CL2)
DQ(CL3)
*Note : 1. CKE to CLK disable/enable = 1CLK.
2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"
3. DQM masks both data-in and data-out.
RD
Q0Q4Q7Q8Q2
Note 2
Hi-Z
Hi-Z
- 15
Hi-Z
Hi-Z
Hi-Z
Q3Q6Q7Q1
Hi-Z
Q6
Q5
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
3. CAS Interrupt (I)
1) Read interrupted by Read (BL=4)
CLK
CMD
ADD
DQ(CL2)
DQ(CL3)
2) Write interrupted by Write (BL=2)
CLK
CMD
ADD
DQ
RDRD
AB
tCCD
Note 2
WR WR
tCCD Note 2
AB
DA0DB1DB0
tCDL
Note 3
QA0QB1 QB2 QB3QB0
Note 1
QA0QB1 QB2 QB3QB0
3) Write interrupted by Read (BL=2)
WRRD
tCCD Note 2
AB
DQ(CL2)
DQ(CL3)
DA0QB1QB0
DA0QB1QB0
tCDL
Note 3
*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.
By "CAS Interrupt", to stop burst read/write by CAS access ; read and write.
2. tCCD: CAS to CAS delay. (=1CLK)
3. tCDL: Last data in to new column address delay. (=1CLK)
- 16
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
4. CAS Interrupt (II) : Read Interrupted by Write & DQM
(a) CL=2, BL=4
CLK
i) CMD
DQM
DQ
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
(b) CL=3, BL=4
CLK
i) CMD
DQM
WR
D1D2RDD3
D0
RDWR
Hi-Z
RDWR
RDWR
WR
D1D2D3D0
Hi-Z
Hi-Z
Q0D1D2D3D0
Note 1
D1D2D3D0
DQD1D2RDD3
ii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iii) CMD
DQM
DQ
iv) CMD
DQM
DQ
*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.
D0
RDWR
D1D2D3D0
RDWR
D1D2D3D0
RDWR
Hi-Z
RDWR
Q0
D1D2D3D0
Hi-Z
Note 1
D1D2D3D0
- 17
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
5. Write Interrupted by Precharge & DQM
CLK
1. To prevent bus contention, DQM should be issued which makes at least one gap between data in and data out.
*Note :
2. To inhibit invalid write, DQM should be issued.
3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only another bank precharge of four banks operation.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency.
6. Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
CMD
DQM
DQ
WR
D0D1D2
WR
D0D1D2
Note 2
D3
Masked by DQM
D3
tRDL
Note 1,4
PRE
PRE
Note 3,4
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
RDPRE
Q0Q1Q2
Q0Q1Q2Q3
Note 2
Q3
1
2
7. Auto Precharge
1) Normal Write (BL=4)
CLK
CMD
DQ
*Note : 1. tRDL : Last data in to row precharge delay
2. Number of valid output data after row precharge : 1, 2 for CAS Latency = 2, 3 respectively.
3. The row active command of the precharge bank can be issued after tRP from this point.
The new read/write command of other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/another bank is illegal.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
WR
D0D1D2
D3
Note 3,4
Auto Precharge Starts
2) Normal Read (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
- 18
RD
D0D1D2D3
D0D1D2D3
Note 3
Auto Precharge Starts
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
8. Burst Stop & Interrupted by Precharge
9. MRS
1) Normal Write (BL=4)
CLK
CMD
DQ
3) Read Interrupted by Precharge (BL=4)
CLK
CMD
DQ(CL2)
DQ(CL3)
WR
D0D1D2
tRDL Note 1,5
RDPRE
Q0Q1
PRE
D3
Note 3
1
Q0Q1
2) Write Burst Stop (BL=8)
CLK
CMD
DQMDQM
DQ
4) Read Burst Stop (BL=4)
CLK
CMD
DQ(CL2)
2
DQ(CL3)
WRSTOP
D0D1D2
RDSTOP
D3
Q0Q1
Q0Q1
D4D5
tBDL Note 2
1
2
1) Mode Register Set
CLK
CMD
*Note : 1. tRDL : 1 CLK
2. tBDL : 1 CLK ; Last data in to burst stop delay.
Read or write burst stop command is valid at every burst length.
3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.
4. PRE : All banks precharge if necessary.
MRS can be issued only at all banks precharge state.
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code "NV"
. From the next generation, tRDL will be only 2CLK for every clock frequency
Note 4
PRE
tRP2CLK
MRSACT
- 19
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
10. Clock Suspend Exit & Power Down Exit
1) Clock Suspend (=Active Power Down) Exit
CLK
CKE
Internal
CLK
Note 1
CMD
11. Auto Refresh & Self Refresh
1) Auto Refresh & Self Refresh
CLK
CMD
PRE
CKE
2) Self Refresh
Note 6
CLK
CMD
PRE
Note 3
Note 4
tRPtRFC
Note 4
2) Power Down (=Precharge Power Down) Exit
CLK
tSS
CKE
Note 2Internal
CLK
RD
¡ó
AR
¡ó
¡ó
¡ó
¡ó
¡ó
CMD
Note 5
CMD
SRCMD
NOP
tSS
ACT
CKE
tRPtRFC
¡ó
*Note : 1. Active power down : one or more banks active state.
2. Precharge power down : all banks precharge state.
3. The auto refresh is the same as CBR refresh of conventional DRAM.
No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.
4. Before executing auto/self refresh command, all banks must be idle state.
5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.
6. During self refresh mode, refresh interval and refresh operation are perfomed internally.
After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted.
Before/After self refresh mode, burst auto refresh cycle (4096 cycles) is recommended.
- 20
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
12. About Burst Type Control
Basic
MODE
Random
MODE
Sequential Counting
Interleave Counting
Random column Access
tCCD = 1 CLK
13. About Burst Length Control
At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=1, 2, 4, 8 and full page.
At MRS A3 = "1". See the BURST SEQUENCE TABLE. (BL=4, 8)
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting
Every cycle Read/Write Command with random column address can realize Random
Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.
Basic
MODE
Special
MODE
Random
MODE
Interrupt
MODE
1
2
4
8
Full Page
BRSW
Burst Stop
RAS Interrupt
(Interrupted by Precharge)
CAS Interrupt
At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = "001".
At auto precharge, tRAS should not be violated.
At MRS A2,1,0 = "010".
At MRS A2,1,0 = "011".
At MRS A2,1,0 = "111".
Wrap around mode(Infinite burst length) should be stopped by burst stop
Ras interrupt or CAS interrupt
At MRS A9 = "1".
Read burst =1, 2, 4, 8, full page write Burst =1
At auto precharge of write, tRAS should not be violated.
tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.
Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
tRDL= 2 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.
During read/write burst with auto precharge, RAS interrupt can not be issued.
Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.
- 21
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
IDLE
Row
Active
Read
Write
Read with
Auto
Precharge
Write with
Auto
Precharge
Pre-
charging
CSRASCASWEBAADDRACTIONNote
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
H
L
X
H
H
L
H
L
X
H
H
L
H
H
X
H
L
X
H
L
H
L
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
H
L
H
L
X
X
H
L
X
X
X
X
H
L
X
X
X
X
H
L
X
H
L
X
X
X
BA
BA
BA
X
OP code
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
X
X
X
X
BA
BA
BA
X
X
X
CA, A10/AP
RA
A10/AP
X
OP code
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
CA, A10/AP
RA
A10/AP
X
X
X
X
CA, A10/AP
RA, RA10
X
X
X
X
CA, A10/AP
RA, RA10
X
X
X
X
CA
RA
A10/AP
NOP
NOP
ILLEGAL
ILLEGAL
Row (& Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
Begin Read ; latch CA ; determine AP
Begin Write ; latch CA ; determine AP
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRP
NOP --> Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRPL
2
2
4
5
5
2
2
3
2
3
3
2
3
2
2
2
2
2
4
- 22
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 1)
Current
State
Row
Activating
Refreshing
Mode
Register
Accessing
CSRASCASWEBAADDRACTIONNote
L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L
L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L
L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X
X
X
H
L
X
H
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
X
BA
BA
BA
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CA
RA
A10/AP
X
X
X
X
X
X
X
X
X
X
X
ILLEGAL
NOP --> Row Active after tRCD
NOP --> Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRFC
NOP --> Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after 2 clocks
NOP --> Idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL
2
2
2
2
Abbreviations : RA = Row Address BA = Bank Address
NOP = No Operation Command CA = Column Address AP = Auto Precharge
*Note : 1. All entries assume the CKE was active (High) during the precharge clcok and the current clock cycle.
2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.
3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.
4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).
5. Illegal if any bank is not idle.
- 23
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
FUNCTION TRUTH TABLE (TABLE 2)
Current
State
Self
Refresh
All
Banks
Precharge
Power
Down
All
Banks
Idle
Any State
other than
Listed
above
Abbreviations : ABI = All Banks Idle, RA = Row Address
CKE
(n-1)
H
H
H
H
H
H
H
H
H
H
H
H
CKE
n
X
L
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
H
H
H
L
X
H
H
H
H
H
L
H
L
L
L
L
L
L
L
L
H
L
H
L
CSRASCASWEADDRACTIONNote
X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X
X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X
X
X
H
H
L
X
X
X
X
H
H
L
X
X
X
X
H
H
L
H
L
L
X
X
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
RA
X
OP Code
X
X
X
X
X
INVALID
Exit Self Refresh --> Idle after tRFC (ABI)
Exit Self Refresh --> Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend
6
6
7
7
8
8
8
9
9
*Note : 6. CKE low to high transition is asynchronous.
7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + tSS must be satisfied before any command other than exit.
8. Power down and self refresh can be entered only from the both banks idle state.
9. Must be a legal command.
- 24
REV. 1.1 Nov. '99
K4S643232C
Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1
tCH
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
tSH
tCL
tRAS
tRC
tSH
HIGH
tSS
tRP
tCCD
tCC
CKE
*Note 1
CS
tRCD
tSH
RAS
tSS
CAS
CMOS SDRAM
ADDR
BA0 ~BA1
A10/AP
DQ
WE
DQM
tSH
tSS
BSBSBSBSBSBS
Ra
Row ActiveReadWriteReadRow Active
tSS
*Note 2,3*Note 2*Note 2
tRAC
tSAC
tSLZ
tOH
*Note 2,3*Note 2,3 *Note 4
tSH
tSS
tSH
tSS
tSS
tSH
*Note 4*Note 3*Note 3*Note 3
QcDbQa
Precharge
RbCcCbCaRa
Rb
- 25
: Don't care
REV. 1.1 Nov. '99
K4S643232C
*Note : 1. All input expect CKE & DQM can be don't care when CS is high at the CLK high going edge.
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CMOS SDRAM
2. Bank active & read/write are controlled by BA0~BA1.
BA0
BA1
0
0
0
1
1
0
1
1
3. Enable and disable auto precharge function are controlled by A10/AP in read/write command
Active & Read/Write
Bank A
Bank B
Bank C
Bank D
A10/AP
4. A10/AP and BA0~BA1 control bank precharge when precharge command is asserted.
A10/AP
BA0
BA1
0
0
0
1
1
0
0
1
1
1
BA0
0
0
0
0
1
0
1
0
x
1
Disable auto precharge, leave bank A active at end of burst.
0
Disable auto precharge, leave bank B active at end of burst.
1
Disable auto precharge, leave bank C active at end of burst.
0
Disable auto precharge, leave bank D active at end of burst.
1
Enable auto precharge, precharge bank A at end of burst.
0
Enable auto precharge, precharge bank B at end of burst.
1
Enable auto precharge, precharge bank C at end of burst.
0
Enable auto precharge, precharge bank D at end of burst.
1
BA1
Precharge
0
Bank A
0
Bank B
1
Bank C
1
Bank D
x
All Banks
Operation
- 26
REV. 1.1 Nov. '99
K4S643232C
Power Up Sequence
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CKE
CS
High level is necessary
CMOS SDRAM
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
RAS
CAS
ADDR
BA0
BA1
A10/AP
DQ
High-Z
tRPtRC
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Key
RAa
RAa
WE
DQM
∼
∼
∼
∼
∼
∼
High level is necessary
PrechargeAuto RefreshAuto RefreshMode Register Set
(All Banks)
- 27
REV. 1.1 Nov. '99
Row Active
(A-Bank)
: Don't care
K4S643232C
Read & Write Cycle at Same Bank @Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CMOS SDRAM
ADDR
A10/AP
DQ
CKE
CS
RAS
CAS
BA0
BA1
CL=2
CL=3
HIGH
*Note 1
tRC
tRCD
*Note 2
RaCaRbCb
RaRb
tOH
tRAC
*Note 3
tRAC
*Note 3
Qa0 Qa1 Qa2 Qa3
tSAC
tOH
Qa0 Qa1 Qa2 Qa3
tSAC
tSHZ
*Note 4
tSHZ
*Note 4
Db0 Db1 Db2 Db3
Db0 Db1 Db2 Db3
tRDL
*Note 5
tRDL
*Note 5
WE
DQM
Row Active
(A-Bank)
*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.
2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.
3. Access time from Row active command. tCC *(tRCD + CAS latency - 1) + tSAC
4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst)
5. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(A-Bank)
- 28
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
REV. 1.1 Nov. '99
K4S643232C
Page Read & Write Cycle at Same Bank @Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CMOS SDRAM
ADDR
A10/AP
DQ
CKE
CS
RAS
CAS
BA0
BA1
CL=2
HIGH
tRCD
RaCaCbCcCd
Ra
Qa0 Qa1 Qb0 Qb1
Qb2
Dc0 Dc1 Dd0 Dd1
*Note 2
tRDL
*Note 4
CL=3
WE
DQM
Row Active
(A-Bank)
*Note :
Qa0 Qa1 Qb0 Qb1
*Note 1*Note 3
Read
(A-Bank)
1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.
2. Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency
*Note : 1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
3.For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency
(A-Bank)
(B-Bank)
Write
Write
(B-Bank)
Row Active
(C-Bank)
Row Active
(D-Bank)
(C-Bank)
Write
(D-Bank)
Write
- 31
*Note 3
tRDL
*Note 1
Precharge
(All Banks)
: Don't care
REV. 1.1 Nov. '99
K4S643232C
Read & Write Cycle at Different Bank @Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CMOS SDRAM
ADDR
A10/AP
DQ
CKE
CS
RAS
CAS
BA0
BA1
CL=2
RAa
RAa
RDbCAa
RBb
QAa0 QAa1 QAa2 QAa3
HIGH
CDb RBc
RAc
DDb0 DDb1 DDb2 DDb3
tCDL
CBc
*Note 1
QBc0 QBc1 QBc2
CL=3
WE
DQM
QAa0 QAa1 QAa2 QAa3
Row Active
(A-Bank)
*Note :1. tCDL should be met to complete write.
Read
(A-Bank)
Precharge
(A-Bank)
Row Active
(D-Bank)
DDb0 DDb1 DDb2 DDb3
Write
(D-Bank)
Precharge
(B-Bank)
QBc0 QBc1
Read
(B-Bank)
: Don't care
- 32
REV. 1.1 Nov. '99
K4S643232C
Read & Write Cycle with Auto Precharge I @Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CMOS SDRAM
CKE
CS
RAS
CAS
ADDR
BA0
BA1
A10/AP
DQ
(CL=2)
DQ
(CL=3)
RAa
RAa
RBb CAa
RBb
HIGH
QAa0 QAa1 QAa2 QAa3
QAa0 QAa1 QAa2 QAa3
CBb
DBb0 DBb1 DBb2 DBb3
DBb0 DBb1 DBb2 DBb3
WE
DQM
Row Active
(A-Bank)
Row Active
*Note :
1. tRCD should be controlled to meet minimum tRAS before internal precharge start.
(In the case of Burst Length=1 & 2, BRSW mode and Block write)
Read with
Auto Precharge
(A-Bank)
(B-Bank)
Auto Precharge
Start Point
(A-Bank)
Write with
Auto Precharge
(B-Bank)
Auto Precharge
Start Point
(B-Bank)
: Don′t care
- 33
REV. 1.1 Nov. '99
K4S643232C
Read & Write Cycle with Auto Precharge II @Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CMOS SDRAM
ADDR
A10/AP
DQ
CKE
CS
RAS
CAS
BA0
BA1
CL=2
CL=3
RaRbCa
RaRb
HIGH
Qa0Qa1Qb0Qb1
Qa0Qa1Qb0Qb1
Qb2
Qb3
Qb2Qb3
RaCb
Ra
Ca
Da0Da1
Da0Da1
WE
DQM
Row Active
(A-Bank)
*Note:
Read with
Auto Pre
charge
(A-Bank)
Row Active
(B-Bank)
* When Read(Write) command with auto precharge is issued at A-Bank after A and B Bank activation.
- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .
- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.
Read without Auto
precharge(B-Bank)
Auto Precharge
Start Point
(A-Bank)*
- 34
Precharge
(B-Bank)
Row Active
(A-Bank)
Auto Precharge
REV. 1.1 Nov. '99
Write with
(A-Bank)
: Don't care
K4S643232C
Read & Write Cycle with Auto Precharge III @Burst Length=4
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
CMOS SDRAM
ADDR
A10/AP
DQ
CKE
CS
RAS
CAS
BA0
BA1
CL=2
RaCa
Ra
HIGH
Rb
Qa0Qa1Qa2Qa3
CbRb
Qb0Qb1Qb2Qb3
CL=3
WE
DQM
Row Active
(A-Bank)
*Note :
Qa0Qa1Qa2Qa3
*
Read with
Auto Precharge
(A-Bank)
* Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point
*Note : 1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. About the valid DQs after burst stop, it is same as the case of RAS interrupt.
Both cases are illustrated above timing diagram. See the label 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".
1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.
2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding memory cell. It is defined by AC
parameter of tRDL. DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst.
Input data after Row precharge cycle will be masked internally.
3. Burst stop is valid at every burst length.
4. For -55/60/70/80/10, tRDL=1CLK product can be supported within restricted amounts and it will be distinguished by bucket code
"NV". From the next generation, tRDL will be only 2CLK for every clock frequency.
Burst Stop
- 38
Write
(A-Bank)
Precharge
(A-Bank)
: Don't care
REV. 1.1 Nov. '99
K4S643232C
Burst Read Single bit Write Cycle @Burst Length=2
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
CLOCK
*Note 1
CKE
CS
RAS
CAS
CMOS SDRAM
HIGH
*Note 2
ADDR
A10/AP
DQ
BA0
BA1
CL=2
CL=3
WE
DQM
RAaCAa RBb CAbRCcCBcCCd
RAcRAaRBb
Row Active
(A-Bank)
DAa0
DAa0
Row Active
(B-Bank)
QAb0 QAb1
QAb0 QAb1DBc0
Row Active
(C-Bank)
DBc0QCd0 QCd1
Read
(C-Bank)
QCd0 QCd1
Precharge
(C-Bank)
Write
(A-Bank)
*Note :1. BRSW modes is enabled by setting A9 "High" at MRS (Mode Register Set).
At the BRSW Mode, the burst length at write is fixed to "1" regardless of programmed burst length.
2. When BRSW write command with auto precharge is executed, keep it in mind that tRAS should not be violated.
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.
Read with
Auto Precharge
(A-Bank)
Write with
Auto Precharge
(B-Bank)
- 39
: Don't care
REV. 1.1 Nov. '99
K4S643232C
Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4
CMOS SDRAM
CLOCK
CKE
CS
RAS
CAS
ADDR
BA
A10/AP
DQ
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
tSS
*Note 1
∼
∼
∼
∼
∼
∼
*Note 3
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
*Note 2
∼
∼
tSS
RaCa
Ra
tSS
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
*Note 2
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Qa0
Qa1
tSHZ
Qa2
WE
DQM
∼
∼
∼
∼
∼
∼
∼
∼
Precharge
Power-down
Entry
Precharge
Power-down
*Note :1. Both banks should be in idle state prior to entering precharge power down mode.
2. CKE should be set high at least 1CLK + tss prior to Row active command.
3. Can not violate minimum refresh specification. (64ms)
Exit
Row Active
Active
Power-down
Entry
∼
∼
∼
∼
∼
∼
∼
∼
Power-down
- 40
Read
Active
Exit
Precharge
: Don ¡Çt Care
REV. 1.1 Nov. '99
K4S643232C
Self Refresh Entry & Exit Cycle
CMOS SDRAM
CLOCK
CKE
CS
RAS
CAS
ADDR
BA0~BA1
A10/AP
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
*Note 2
*Note 1
tSS
∼
∼
∼
∼
*Note 3
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
*Note 4
*Note 5
∼
∼
tRFCmin
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
*Note 6
*Note 7
DQ
WE
DQM
Self Refresh Entry
*Note :
TO ENTER SELF REFRESH MODE
1. CS, RAS & CAS with CKE should be low at the same clcok cycle.
2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.
3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum tRAS is required before exit from self refresh.
TO EXIT SELF REFRESH MODE
4. System colck restart and be stable before returning CKE high.
5. CS starts from high.
6. Minimum tRFC is required after CKE going high to complete self refresh exit.
7. 4K cycle of burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh.
Hi-Z
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
Hi-Z
Self Refresh ExitAuto Refresh
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
: Don't care
- 41
REV. 1.1 Nov. '99
K4S643232C
CMOS SDRAM
CLOCK
CKE
CS
RAS
CAS
ADDR
DQ
WE
Mode Register Set Cycle
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
HIGH
*Note 2
*Note 1
*Note 3
KeyRa
Hi-Z
Auto Refresh Cycle
0 1 2 3 4 5 6 7 8 9 10
∼
∼
∼
HIGH
tRFC
Hi-Z
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
∼
DQM
∼
∼
¡ó
∼
∼
¡ó
MRSAuto Refresh
* All banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.
MODE REGISTER SET CYCLE
*Note :1. CS, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.
2. Minimum 2 clock cycles should be met before new RAS activation.
3. Please refer to Mode Register Set table.
New
Command
New Command
: Don't care
- 42
REV. 1.1 Nov. '99
K4S643232CCMOS SDRAM
PACKAGE DIMENSIONS
86-TSOP2-400F
Unit : Millimeters
0.10
0.004
MAX
#86
#1
0.61
( )
0.024
0.20
22.62
0.891
22.22
0.875
+0.10
-0.03
MAX
± 0.10
± 0.004
0.50
0.0197
#44
#43
0.21
0.008
MIN
0~8°C
0.45~0.75
0.50
0.018~0.030
0.020
( )
0.25
TYP
0.010
0.400
1.20
0.047
10.16
0.125
0.005
MAX
0.05
0.010
+0.075
-0.035
+0.003
-0.001
11.76±0.20
0.463±0.008
± 0.05
± 0.002
1.00
0.039
± 0.10
± 0.004
- 43
REV. 1.1 Nov. '99
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