K4S560832D CMOS SDRAM
Rev. 0.0 May. 2002
The K4S560832D is 268,435,456 bits synchronous high data rate
Dynamic RAM organized as 4 x 8,392,608 words by 8bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTIONFEATURES
FUNCTIONAL BLOCK DIAGRAM
8M x 8Bit x 4 Banks Synchronous DRAM
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S560832D-NC/L7C 133MHz(CL=2)
LVTTL
54pin
sTSOP(II)
K4S560832D-NC/L75 133MHz(CL=3)
K4S560832D-NC/L1H 100MHz(CL=2)
K4S560832D-NC/L1L 100MHz(CL=3)
Bank Select
Data Input Register
8M x 8
8M x 8
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
8M x 8
8M x 8
Timing Register
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