Samsung K4S561632E-TCL70, K4S561632E-TCL60, K4S560832E-TC75, K4S560432E-TC75, K4S561632E-TC70 Datasheet
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SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 September. 2003
SDRAM 256Mb E-die (x4, x8, x16)
256Mb E-die SDRAM Specification
Revision 1.3
September. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 September. 2003
SDRAM 256Mb E-die (x4, x8, x16)
Revision History
Revision 1.0 (May. 2003)
- First release.
Revision 1.1 (June. 2003)
- Correct Typo
Revision 1.2 (June. 2003)
- Added 166MHz speed bin in x16
Revision 1.3 (September. 2003)
- Corrected typo in ordering information.
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 September. 2003
SDRAM 256Mb E-die (x4, x8, x16)
Part No. Orgainization Max Freq. Interface Package
K4S560432E-TC(L)75 64M x 4 133MHz LVTTL 54pin TSOP
K4S560832E-TC(L)75 32M x 8 133MHz LVTTL 54pin TSOP
K4S561632E-TC(L)60/75 16M x 16 166MHz LVTTL 54pin TSOP
The K4S560432E / K4S560832E / K4S561632E is 268,435,456 bits synchronous high data rate Dynamic RAM organized as 4 x
16,785,216 / 4 x 8,392,608 / 4 x 4,196,304 words by 4bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high
bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for masking
• Auto & self refresh
• 64ms refresh period (8K Cycle)
GENERAL DESCRIPTION
FEATURES
16M x 4Bit x 4 Banks / 8M x 8Bit x 4 Banks / 4M x 16Bit x 4 Banks SDRAM
Ordering Information
Row & Column address configuration
Organization Row Address Column Address
64Mx4 A0~A12 A0-A9, A11
32Mx8 A0~A12 A0-A9
16Mx16 A0~A12 A0-A8
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 September. 2003
SDRAM 256Mb E-die (x4, x8, x16)
11.76±0.20
0.463±0.008
0.002
0.05
MIN
0.008
0.21
± 0.002
± 0.05
0.020
0.50
(
)
0.005
-0.001
+0.003
0.125
-0.035
+0.075
0.400
10.16
0.45~0.75
0.018~0.030
0.010
0.25
TYP
0~8°C
#54
#28
#1
#27
0.004
0.10
MAX
0.028
0.71
( )
0.012
0.30
0.0315
0.80
0.047
1.20
MAX
0.039
1.00
± 0.004
± 0.10
0.891
22.62
MAX
0.875
22.22
± 0.004
± 0.10
+0.10
-0.05
+0.004
-0.002
54Pin TSOP Package Dimension
Package Physical Dimension
SDRAM 256Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.3 September. 2003
SDRAM 256Mb E-die (x4, x8, x16)
FUNCTIONAL BLOCK DIAGRAM
Bank Select
Data Input Register
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
16M x 4 / 8M x 8 / 4M x 16
16M x 4 / 8M x 8 / 4M x 16
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
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