SAMSUNG K4S511633C-YL Technical data
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K4S511633C-YL/N/P
Mobile SDRAM
(VDD/VDDQ 3.0V/3.0V or 3.3V/3.3V)
CMOS SDRAM
32Mx16
54CSP 1/CS
Revision 1.2
December 2002
Rev. 1.2 Dec. 2002
K4S511633C-YL/N/P
8M x 16Bit x 4 Banks Mobile SDRAM
CMOS SDRAM
FEATURES
• 3.0V power supply
• LVCMOS compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (1 & 2 & 3)
-. Burst length (1, 2, 4, 8 & Full page)
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system
clock.
• Burst read single-bit write operation
• DQM for masking
• Auto & self refresh
• 64ms refresh period (8K cycle)
• 1 /CS Support.
• Commercial Temperature Operation (-25°C ~ 70°C).
Extended Temperature Operation (-25°C ~ 85°C).
Industrial Temperature Operation (-40°C ~ 85°C).
• 54balls DDP CSP
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The K4S511633C is 536,870,912 bits synchronous high data
rate Dynamic RAM organized as 4 x 8,388,608 words by 16bits,
fabricated with SAMSUNG's high performance CMOS technology.
Synchronous design allows precise cycle control with the use of
system clock I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable burst length and
programmable latencies allow the same device to be useful for a
variety of high bandwidth, high performance memory system
applications.
ORDERING INFORMATION
Part No. Max Freq. Interface Package
K4S511633C-YL/N80
K4S511633C-YL/N1H 100MHz(CL=2)
K4S511633C-YL/N1L 100MHz(CL=3)
- YN : Low Power, Operating Temp : -25°C ~ 85°C.
- YL : Low Power, Operating Temp : -25°C ~ 70°C.
- YP : Low Power, Operating Temp : -40°C ~ 85°C.
Note :
1. In case of 33MHz Frequency, CL1 can be supported.
125MHz(CL=3)
100MHz(CL=2)
LVCMOS 54 CSP
*1
CLK
ADD
Data Input Register
Bank Select
Refresh Counter
Row Buffer
Address Register
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS RAS CAS WE DQM
Row Decoder Col. Buffer
Latency & Burst Length
Programming Register
LCAS LWCBR
Timing Register
8M x 16
8M x 16
8M x 16
8M x 16
Column Decoder
LWE
LDQM
Sense AMP
Samsung Electronics reserves the right to
*
change products or specification without
notice.
Output BufferI/O Control
DQi
Rev. 1.2 Dec. 2002
K4S511633C-YL/N/P
Package Dimension and Pin Configuration
< Bottom View*1 > < Top View*2 >
E
1
5 2 16 3489 7
A
B
C
D
1
D
E
F
G
H
J
CMOS SDRAM
54Ball(6x9) CSP
1 2 3 7 8 9
A VSS DQ15 VSSQ VDDQ DQ0 VDD
e
D
D/2
B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1
C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3
D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5
E DQ8 NC VSS VDD LDQM DQ7
F UDQM CLK CKE CAS RAS WE
G A12 A11 A9 BA0 BA1 CS
H A8 A7 A6 A0 A1 A10
J VSS A5 A4 A3 A2 VDD
Max. 0.20
*2: Top View
Encapsulant
*1: Bottom View
< Top View*2 >
E
E/2
b
#A1 Ball Origin Indicator
K4 S511633C-XXXX
SA MSUNG Week
Pin Name Pin Function
CLK System Clock
CS Chip Select
CKE Clock Enable
A0 ~ A12 Address
BA0 ~ BA1 Bank Select Address
A
A1
z
RAS Row Address Strobe
CAS Column Address Strobe
WE Write Enable
L(U)DQM Data Input/Output Mask
DQ0 ~ 15 Data Input/Output
VDD /VSS Power Supply/Ground
VDDQ/VSSQ Data Output Power/Ground
[Unit:mm]
Symbol Min Typ Max
A 1.00 1.10 1.30
A
1
E - 9.50 -
E
1
D - 15.50 -
D
1
e - 0.80 b 0.40 0.45 0.50
z - - 0.10
0.27 0.32 0.37
- 6.40 -
- 6.40 -
Rev. 1.2 Dec. 2002
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