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K4S511632M |
CMOS SDRAM |
512Mbit SDRAM
8M x 16bit x 4 Banks Synchronous DRAM LVTTL
Revision 0.3
May. 2002
Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.3 May. 2002
K4S511632M |
CMOS SDRAM |
Revision History
Revision 0.0 (Mar. 2001)
Revision 0.1 (Aug. 2001)
Defined target DC characteristics.
Revision 0.2 (Dec. 2001)
•Changed "Target" to "Preliminary".
•Redefined DC characteristics.
Revision 0.3 (May. 2002)
•Changed "Preliminary" to "Final".
Rev. 0.3 May. 2002
K4S511632M |
CMOS SDRAM |
8M x 16Bit x 4 Banks Synchronous DRAM
FEATURES
•JEDEC standard 3.3V power supply
•LVTTL compatible with multiplexed address
•Four banks operation
•MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4, 8 & Full page) -. Burst type (Sequential & Interleave)
•All inputs are sampled at the positive going edge of the system clock.
•Burst read single-bit write operation
•DQM for masking
•Auto & self refresh
•64ms refresh period (8K cycle)
GENERAL DESCRIPTION
The K4S511632M is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16bits, fabricated with SAMSUNG's high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to be useful for a variety of high bandwidth, high performance memory system applications.
ORDERING INFORMATION
Part No. |
Max Freq. |
Interface |
Package |
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K4S511632M-TC/TL75 |
133MHz(CL=3) |
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54pin |
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K4S511632M-TC/TL1H |
100MHz(CL=2) |
LVTTL |
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TSOP(II) |
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K4S511632M-TC/TL1L |
100MHz(CL=3) |
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FUNCTIONAL BLOCK DIAGRAM
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Data Input Register |
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Bank Select |
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Address |
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CounterRefresh |
BufferRow |
DecoderRow |
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8M x 16 |
AMPSense |
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8M x 16 |
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8M x 16 |
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CLK |
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8M x 16 |
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Register |
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LRAS |
LCBR |
Buffer.Col |
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ADD |
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Column Decoder |
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Latency & Burst Length |
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LCKE |
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Programming Register |
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LRAS |
LCBR |
LWE |
LCAS |
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LWCBR |
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Timing Register |
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CLK |
CKE |
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CS |
RAS |
CAS |
WE |
DQM |
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I/O |
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LWE |
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Control |
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LDQM |
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Output |
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DQi |
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Buffer |
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LDQM
*Samsung Electronics reserves the right to change products or specification without notice.
Rev. 0.3 May. 2002
K4S511632M |
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CMOS SDRAM |
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PIN CONFIGURATION (Top view) |
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VDD |
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1 |
54 |
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VSS |
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DQ0 |
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2 |
53 |
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DQ15 |
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VDDQ |
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3 |
52 |
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VSSQ |
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DQ1 |
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4 |
51 |
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DQ14 |
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DQ2 |
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5 |
50 |
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DQ13 |
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VSSQ |
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6 |
49 |
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VDDQ |
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DQ3 |
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7 |
48 |
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DQ12 |
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DQ4 |
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8 |
47 |
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DQ11 |
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VDDQ |
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9 |
46 |
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VSSQ |
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DQ5 |
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10 |
45 |
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DQ10 |
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DQ6 |
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11 |
44 |
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DQ9 |
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VSSQ |
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12 |
43 |
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VDDQ |
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DQ7 |
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13 |
42 |
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DQ8 |
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VDD |
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14 |
41 |
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VSS |
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LDQM |
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15 |
40 |
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N.C/RFU |
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WE |
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16 |
39 |
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UDQM |
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CAS |
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17 |
38 |
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CLK |
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RAS |
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18 |
37 |
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CKE |
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CS |
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19 |
36 |
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A12 |
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BA0 |
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20 |
35 |
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A11 |
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BA1 |
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21 |
34 |
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A9 |
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A10/AP |
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22 |
33 |
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A8 |
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A0 |
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23 |
32 |
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A7 |
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A1 |
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24 |
31 |
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A6 |
54Pin TSOP (II) |
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A2 |
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25 |
30 |
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A5 |
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(400mil x 875mil) |
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A3 |
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26 |
29 |
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A4 |
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(0.8 mm Pin pitch) |
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VDD |
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27 |
28 |
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VSS |
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PIN FUNCTION DESCRIPTION
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Pin |
Name |
Input Function |
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CLK |
System clock |
Active on the positive going edge to sample all inputs. |
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Disables or enables device operation by masking or enabling all inputs except |
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CS |
Chip select |
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CLK, CKE and DQM |
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Masks system clock to freeze operation from the next clock cycle. |
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CKE |
Clock enable |
CKE should be enabled at least one cycle prior to new command. |
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Disable input buffers for power down in standby. |
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A0 ~ A12 |
Address |
Row/column addresses are multiplexed on the same pins. |
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Row address : RA0 ~ RA12, Column address : CA0 ~ CA9 |
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BA0 ~ BA1 |
Bank select address |
Selects bank to be activated during row address latch time. |
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Selects bank for read/write during column address latch time. |
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Latches row addresses on the positive going edge of the CLK with RAS low. |
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RAS |
Row address strobe |
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Enables row access & precharge. |
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Latches column addresses on the positive going edge of the CLK with CAS low. |
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CAS |
Column address strobe |
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Enables column access. |
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Enables write operation and row precharge. |
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WE |
Write enable |
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Latches data in starting from CAS, WE active. |
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DQM |
Data input/output mask |
Makes data output Hi-Z, tSHZ after the clock and masks the output. |
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Blocks data input when DQM active. |
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DQ0 ~ 15 |
Data input/output |
Data inputs/outputs are multiplexed on the same pins. |
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VDD/VSS |
Power supply/ground |
Power and ground for the input buffers and the core logic. |
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VDDQ/VSSQ |
Data output power/ground |
Isolated power supply and ground for the output buffers to provide improved noise |
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immunity. |
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N.C/RFU |
No connection |
This pin is recommended to be left No Connection on the device. |
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/reserved for future use |
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Rev. 0.3 May. 2002