SAMSUNG K4S51153LF Technical data

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K4S51153LF - Y(P)C/L/F

8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA

FEATURES

• VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system clock.

• Burst read single-bit write operation.

• Special Function Support.

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

• DQM for masking.

• Auto refresh.

• 64ms refresh period (8K cycle).

• Commercial Temperature Operation (-25°C ~ 70°C).

• 2 /CS Support.

• 2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).

Mobile SDRAM

GENERAL DESCRIPTION

The K4S51153LF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.

ORDERING INFORMATION

Part No. Max Freq. Interface Package

K4S51163LF-Y(P)C/L/F75 133MHz(CL3), 111MHz(CL2)

K4S51163LF-Y(P)C/L/F1H 111MHz(CL2)

K4S51163LF-Y(P)C/L/F1L 111MHz(CL=3)*1, 83MHz(CL2)

- Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C)

NOTES :

1. In case of 40MHz Frequency , CL1 can be supported.

2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur pose, such as medical, aerospace, nuclear, military, vehicular or undersea repe ater use.

LVCMOS

54 FBGA Pb

(Pb Free)

Address configuration

Organization Bank Row Column Address

32M x16 BA0,BA1 A0 - A12 A0 - A8

September 2004

K4S51153LF - Y(P)C/L/F

FUNCTIONAL BLOCK DIAGRAM

CLK, /CAS, /RAS,

/WE, DQM, CKE

/CS1

/CS0

Mobile SDRAM

16Mx16

DQ0~DQ15

A0~A12, BA0, BA1

September 2004

K4S51153LF - Y(P)C/L/F

Package Dimension and Pin Configuration

Mobile SDRAM

< Top View

>< Bottom View*1 >

A B C D

E F G H J

Substrate(2Layer)

521634897

E/2

*2: Top View

*1: Bottom View

< Top View*2 >

#A1 Ball Origin Indicator

K4S51153LF

SEC Week

XXXX

54Ball(6x9) FBGA

123789 A VSS DQ15 VSSQ VDDQ DQ0 VDD B DQ14 DQ13 VDDQ VSSQ DQ2 DQ1

D/2

C DQ12 DQ11 VSSQ VDDQ DQ4 DQ3 D DQ10 DQ9 VDDQ VSSQ DQ6 DQ5 EDQ8CS1 F UDQM CLK CKE CAS G A12 A11 A9 BA0 BA1 CS0 HA8A7A6A0A1A10 J VSS A5 A4 A3 A2 VDD

Pin Name Pin Function

CLK System Clock

0 ~ 1 Chip Select

CKE Clock Enable

0 ~ A12 Address

0 ~ BA1 Bank Select Address

RAS CAS

L(U)DQM Data Input/Output Mask

0 ~ 15 Data Input/Output

DQ V

DD/VSS Power Supply/Ground

DDQ/VSSQ Data Output Power/Ground

Symbol Min Typ Max

A 1.00 1.10 1.20

E-11.5-

D - 10.0 -

e - 0.80 b 0.45 0.50 0.55 z--0.10

VSS VDD LDQM DQ7

RAS WE

Row Address Strobe

Column Address Strobe

Write Enable

[Unit:mm]

0.27 0.32 0.37

-6.40-

September 2004

K4S51153LF - Y(P)C/L/F

Mobile SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to V Voltage on V

DD supply relative to Vss VDD, VDDQ -1.0 ~ 3.6 V

ss VIN, VOUT -1.0 ~ 3.6 V

Storage temperature T Power dissipation P Short circuit current I

NOTES:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

STG -55 ~ +150 °C

D 1.0 W

OS 50 mA

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70°C )

Parameter Symbol Min Typ Max Unit Note

VDD 2.3 2.5 2.7 V

Supply voltage

Input logic high voltage VIH 0.8 x VDDQ - VDDQ + 0.3 V 2 Input logic low voltage VIL -0.3 0 0.3 V 3 Output logic high voltage VOH VDDQ -0.2 - - V IOH = -0.1mA Output logic low voltage VOL - - 0.2 V IOL = 0.1mA Input leakage current ILI -2 - 2 uA 4

NOTES :

1. Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products. Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).

2. VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns.

3. VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.

4. Any input 0V ≤ VIN ≤ VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.

5. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

VDDQ

2.3 2.5 2.7 V

1.65 - 2.7 V 1

CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)

Pin Symbol Min Max Unit Note

Clock CCLK 3.0 6.0 pF RAS, CAS, WE, CKE CIN 3.0 6.0 pF CS CIN 1.5 3.0 pF DQM CIN 3.0 6.0 pF Address CADD 3.0 6.0 pF DQ0 ~ DQ15 COUT 6.0 10.0 pF

September 2004

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