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K4S51153LF - Y(P)C/L/F |
Mobile SDRAM |
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8M x 16Bit x 4 Banks Mobile SDRAM in 54FBGA |
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FEATURES
•VDD/VDDQ = 2.5V/2.5V or 2.5V/1.8V.
•LVCMOS compatible with multiplexed address.
•Four banks operation.
•MRS cycle with address key programs.
-. CAS latency (1, 2 & 3).
-. Burst length (1, 2, 4, 8 & Full page). -. Burst type (Sequential & Interleave).
•EMRS cycle with address key programs.
•All inputs are sampled at the positive going edge of the system clock.
•Burst read single-bit write operation.
•Special Function Support.
-. PASR (Partial Array Self Refresh).
-. Internal TCSR (Temperature Compensated Self Refresh)
•DQM for masking.
•Auto refresh.
•64ms refresh period (8K cycle).
•Commercial Temperature Operation (-25°C ~ 70°C).
•2 /CS Support.
•2Chips DDP 54Balls FBGA( -YXXX -Pb, -PXXX -Pb Free).
GENERAL DESCRIPTION
The K4S51153LF is 536,870,912 bits synchronous high data rate Dynamic RAM organized as 4 x 8,388,608 words by 16 bits, fabricated with SAMSUNG’s high performance CMOS technology. Synchronous design allows precise cycle control with the use of system clock and I/O transactions are possible on every clock cycle. Range of operating frequencies, programmable burst lengths and programmable latencies allow the same device to be useful for a variety of high bandwidth and high performance memory system applications.
ORDERING INFORMATION
Part No. |
Max Freq. |
Interface |
Package |
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K4S51163LF-Y(P)C/L/F75 |
133MHz(CL3), 111MHz(CL2) |
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54 FBGA Pb |
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LVCMOS |
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K4S51163LF-Y(P)C/L/F1H |
111MHz(CL2) |
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(Pb Free) |
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K4S51163LF-Y(P)C/L/F1L |
111MHz(CL=3)*1, 83MHz(CL2) |
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- Y(P)C/L/F : Normal / Low Power, Commercial Temperature(-25°C ~ 70°C)
NOTES :
1.In case of 40MHz Frequency, CL1 can be supported.
2.Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake. Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific pur pose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.
Address configuration
Organization |
Bank |
Row |
Column Address |
32M x16 |
BA0,BA1 |
A0 - A12 |
A0 - A8 |
1 |
September 2004 |
K4S51153LF - Y(P)C/L/F |
Mobile SDRAM |
FUNCTIONAL BLOCK DIAGRAM
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CLK, /CAS, /RAS, |
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/WE, DQM, CKE |
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16Mx16 |
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/CS1 |
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16Mx16
/CS0
DQ0~DQ15
A0~A12, BA0, BA1
2 |
September 2004 |
K4S51153LF - Y(P)C/L/F |
Mobile SDRAM |
Package Dimension and Pin Configuration
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< Bottom View*1 > |
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E1 |
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9 |
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E |
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D/2 |
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E/2 |
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*2: Top View
A
A1
Substrate(2Layer) |
b |
z |
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*1: Bottom View
< Top View*2 >
#A1 Ball Origin Indicator
XXXX Week SEC
K4S51153LF
< Top View*2 >
54Ball(6x9) FBGA
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1 |
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2 |
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3 |
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7 |
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8 |
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9 |
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A |
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VSS |
DQ15 |
VSSQ |
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VDDQ |
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DQ0 |
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VDD |
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B |
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DQ14 |
DQ13 |
VDDQ |
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VSSQ |
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DQ2 |
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DQ1 |
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C |
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DQ12 |
DQ11 |
VSSQ |
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VDDQ |
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DQ4 |
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DQ3 |
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D |
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DQ10 |
DQ9 |
VDDQ |
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VSSQ |
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DQ6 |
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DQ5 |
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E |
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DQ8 |
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CS1 |
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VSS |
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VDD |
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LDQM |
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DQ7 |
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F |
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UDQM |
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CLK |
CKE |
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CAS |
RAS |
WE |
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G |
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A12 |
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A11 |
A9 |
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BA0 |
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BA1 |
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CS0 |
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H |
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A8 |
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A7 |
A6 |
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A0 |
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A1 |
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A10 |
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J |
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VSS |
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A5 |
A4 |
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A3 |
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A2 |
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VDD |
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Pin Name |
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Pin Function |
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CLK |
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System Clock |
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0 ~ 1 |
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Chip Select |
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CS |
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CKE |
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Clock Enable |
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A0 ~ A12 |
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Address |
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BA0 ~ BA1 |
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Bank Select Address |
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Row Address Strobe |
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RAS |
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Column Address Strobe |
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CAS |
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Write Enable |
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WE |
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L(U)DQM |
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Data Input/Output Mask |
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DQ0 ~ 15 |
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Data Input/Output |
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VDD/VSS |
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Power Supply/Ground |
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VDDQ/VSSQ |
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Data Output Power/Ground |
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[Unit:mm] |
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Symbol |
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Min |
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Typ |
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Max |
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A |
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1.00 |
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1.10 |
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1.20 |
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A1 |
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0.27 |
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0.32 |
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0.37 |
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E |
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11.5 |
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E1 |
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6.40 |
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10.0 |
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D1 |
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6.40 |
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0.80 |
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0.45 |
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0.50 |
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0.55 |
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z |
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0.10 |
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3 |
September 2004 |
K4S51153LF - Y(P)C/L/F |
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Mobile SDRAM |
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ABSOLUTE MAXIMUM RATINGS |
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Parameter |
Symbol |
Value |
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Unit |
Voltage on any pin relative to Vss |
VIN, VOUT |
-1.0 ~ 3.6 |
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V |
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Voltage on VDD supply relative to Vss |
VDD, VDDQ |
-1.0 ~ 3.6 |
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V |
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Storage temperature |
TSTG |
-55 ~ +150 |
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°C |
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Power dissipation |
PD |
1.0 |
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W |
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Short circuit current |
IOS |
50 |
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mA |
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NOTES:
Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 70°C )
Parameter |
Symbol |
Min |
Typ |
Max |
Unit |
Note |
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VDD |
2.3 |
2.5 |
2.7 |
V |
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Supply voltage |
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VDDQ |
2.3 |
2.5 |
2.7 |
V |
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1.65 |
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2.7 |
V |
1 |
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Input logic high voltage |
VIH |
0.8 x VDDQ |
- |
VDDQ + 0.3 |
V |
2 |
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Input logic low voltage |
VIL |
-0.3 |
0 |
0.3 |
V |
3 |
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Output logic high voltage |
VOH |
VDDQ -0.2 |
- |
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V |
IOH = -0.1mA |
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Output logic low voltage |
VOL |
- |
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0.2 |
V |
IOL = 0.1mA |
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Input leakage current |
ILI |
-2 |
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2 |
uA |
4 |
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NOTES :
1.Samsung can support VDDQ 2.5V(in general case) and 1.8V(in specific case) for VDD 2.5V products. Please contact to the memory marketing team in Samsung Electronics when considering the use of VDDQ 1.8V(Min 1.65V).
2.VIH (max) = 3.0V AC.The overshoot voltage duration is ≤ 3ns.
3.VIL (min) = -1.0V AC. The undershoot voltage duration is ≤ 3ns.
4.Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.
5.Dout is disabled, 0V ≤ VOUT ≤ VDDQ.
CAPACITANCE (VDD = 2.5V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)
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Pin |
Symbol |
Min |
Max |
Unit |
Note |
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Clock |
CCLK |
3.0 |
6.0 |
pF |
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CKE |
CIN |
3.0 |
6.0 |
pF |
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RAS, |
CAS, |
WE, |
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CIN |
1.5 |
3.0 |
pF |
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CS |
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DQM |
CIN |
3.0 |
6.0 |
pF |
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Address |
CADD |
3.0 |
6.0 |
pF |
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DQ0 ~ DQ15 |
COUT |
6.0 |
10.0 |
pF |
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4 |
September 2004 |