Datasheet K4S283233F Datasheet (SAMSUNG)

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K4S283233F - F(H)E/N/G/C/L/F

1M x 32Bit x 4 Banks Mobile SDRAM in 90FBGA

FEATURES

• 3.0V & 3.3V power supply.

• LVCMOS compatible with multiplexed address.

• Four banks operation.

• MRS cycle with address key programs.

-. CAS latency (1, 2 & 3).

-. Burst length (1, 2, 4, 8 & Full page).

-. Burst type (Sequential & Interleave).

• EMRS cycle with address key programs.

• All inputs are sampled at the positive going edge of the system
clock.

• Burst read single-bit write operation.

• Special Function Support.

-. PASR (Partial Array Self Refresh).

-. Internal TCSR (Temperature Compensated Self Refresh)

• DQM for masking.

• Auto refresh.

• 64ms refresh period (4K cycle).

• Commercial Temperature Operation (-25°C ~ 70°C).

• Extended Temperature Operation (-25°C ~ 85°C).

• 90Balls FBGA with 0.8mm ball pitch
( -FXXX : Leaded, -HXXX : Lead Free).

Mobile-SDRAM

GENERAL DESCRIPTION

The K4S283233F is 134,217,728 bits synchronous high data
rate Dynamic RAM organized as 4 x 1,048,576 words by 32 bits,
fabricated with SAMSUNG’s high performance CMOS technol­ogy. Synchronous design allows precise cycle control with the
use of system clock and I/O transactions are possible on every
clock cycle. Range of operating frequencies, programmable
burst lengths and programmable latencies allow the same
device to be useful for a variety of high bandwidth and high per­formance memory system applications.

ORDERING INFORMATION

Part No. Max Freq. Interface Package

K4S283233F-F(H)E/N/G/C/L/F60 166MHz(CL=3)
K4S283233F-F(H)E/N/G/C/L/F75 133MHz(CL=3)
K4S283233F-F(H)E/N/G/C/L/F1H 105MHz(CL=2)
K4S283233F-F(H)E/N/G/C/L/F1L

- F(H)E/N/G : Normal / Low/ Low Power, Extended Temperature(-25°C ~ 85°C)

- F(H)C/L/F : Normal / Low / Low Power, Commercial Temperature(-25°C ~ 70°C)

NOTES :

1. In case of 40MHz Frequency , CL1 can be supported.

2. Samsung are not designed or manufactured for use in a device or system that is used under circumstance in which human life is potentially at stake.
Please contact to the memory marketing team in samsung electronics when considering the use of a product contained herein for any specific
purpose, such as medical, aerospace, nuclear, military, vehicular or undersea repeater use.

105MHz(CL=3)

*1

LVCMOS

90 FBGA

Leaded (Lead Free)

February 2004

K4S283233F - F(H)E/N/G/C/L/F

FUNCTIONAL BLOCK DIAGRAM

Bank Select

Mobile-SDRAM

LWE

Data Input Register

LDQM

CLK

ADD

LCKE

Refresh Counter

Row Buffer

Address Register

LRAS

LCBR

LRAS LCBR LWE LDQM

CLK CKE CS

Row Decoder Col. Buffer

LCAS LWCBR

Timing Register

RAS CAS WE DQM

1M x 32
1M x 32
1M x 32
1M x 32

Column Decoder

Latency & Burst Length

Programming Register

Sense AMP

Output BufferI/O Control

DQi

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Package Dimension and Pin Configuration

1

D

Substrate(2Layer)

< Bottom View*1 >

A
B
C
D

E

F
G
H

J
K

L

M

N
P
R

#A1 Ball Origin Indicator

E

1

521634897

E

< Top View*2 >

E/2

e

z

b

SAMSUNG Week

K4S283233F-XXXX

A1

Mobile-SDRAM

*2

< Top View

90Ball(6x15) FBGA

123789
A DQ26 DQ24 V
BDQ28V

SSQ DQ27 DQ25 DQ22 DQ20 VDDQ

CV

D

DVSSQ DQ29 DQ30 DQ17 DQ18 VDDQ
EVDDQ DQ31 NC NC DQ16 VSSQ
FVSS DQM3 A3 A2 DQM2 VDD
GA4A5A6A10A0A1
H A7 A8 NC NC BA1 A11
J CLK CKE A9 BA0 CS
KDQM1 NC NC CAS WE DQM0

D/2

DDQ DQ8 VSS VDD DQ7 VSSQ

LV
MVSSQ DQ10 DQ9 DQ6 DQ5 VDDQ
NVSSQ DQ12 DQ14 DQ1 DQ3 VDDQ
PDQ11VDDQ VSSQ VDDQ VSSQ DQ4
R DQ13 DQ15 V

Pin Name Pin Function

CLK System Clock

A

CS

CKE Clock Enable

A

0 ~ A11 Address

BA

0 ~ BA1 Bank Select Address

RAS
CAS

WE

DQM

0 ~ DQM3 Data Input/Output Mask

0 ~ 31 Data Input/Output

DQ

V

DD/VSS Power Supply/Ground

V

DDQ/VSSQ Data Output Power/Ground

DDQ VSSQ VDDQ VSSQ DQ19

>

SS VDD DQ23 DQ21

RAS

SS VDD DQ0 DQ2

Chip Select

Row Address Strobe

Column Address Strobe

Write Enable

[Unit:mm]

Symbol Min Typ Max

A - 1.10 1.20

A

1

E-8.00-

E

1

D - 13.00 -

D

1

e-0.80­b 0.40 0.45 0.50
z--0.10

0.30 0.35 0.40

-6.40-

-11.20-

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Mobile-SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to V
Voltage on V

DD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V

ss VIN, VOUT -1.0 ~ 4.6 V

Storage temperature T
Power dissipation P
Short circuit current I

NOTES:

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

STG -55 ~ +150 °C

D 1.0 W

OS 50 mA

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter Symbol Min Typ Max Unit Note

Supply voltage

Input logic high voltage VIH 2.2 3.0 VDDQ + 0.3 V 1
Input logic low voltage VIL -0.3 0 0.5 V 2
Output logic high voltage VOH 2.4 - - V IOH = -2mA
Output logic low voltage VOL - - 0.4 V IOL = 2mA
Input leakage current ILI -10 - 10 uA 3

NOTES :

1. VIH (max) = 5.3V AC.The overshoot voltage duration is ≤ 3ns.

2. VIL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ VIN ≤ VDDQ.
Input leakage currents include Hi-Z output leakage for all bi-directional buffers with tri-state outputs.

4. Dout is disabled, 0V ≤ VOUT ≤ VDDQ.

VDD 2.7 3.0 3.6 V

VDDQ 2.7 3.0 3.6 V

CAPACITANCE

Clock CCLK - 4.0 pF
RAS, CAS, WE, CS, CKE CIN - 4.0 pF
DQM CIN - 4.0 pF
Address CADD - 4.0 pF
DQ0 ~ DQ31 COUT - 6.0 pF

(VDD = 3.0V & 3.3V, TA = 23°C, f = 1MHz, VREF =0.9V ± 50 mV)

Pin Symbol Min Max Unit Note

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Mobile-SDRAM

DC CHARACTERISTICS

Recommended operating conditions (Voltage referenced to VSS = 0V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby Current
in power-down mode

Precharge Standby Current
in non power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down mode
(One Bank Active)

Operating Current
(Burst Mode)

Version

-60 -75 -1H -1L

Burst length = 1

ICC1

t

RC ≥ tRC(min)

I

O = 0 mA

ICC2P CKE ≤ VIL(max), tCC = 10ns 0.5

ICC2PS CKE & CLK ≤ VIL(max), tCC = ∞ 0.5

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC2N

Input signals are changed one time during
20ns

ICC2NS

ICC3PS CKE & CLK ≤ VIL(max), tCC = ∞ 5

ICC3NS

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

ICC3P CKE ≤ VIL(max), tCC = 10ns 5

CKE ≥ VIH(min), CS ≥ VIH(min), tCC = 10ns

ICC3N

Input signals are changed one time during
20ns

CKE ≥ VIH(min), CLK ≤ VIL(max), tCC = ∞
Input signals are stable

100 85 85 80 mA 1

16

26 mA

22 mA

IO = 0 mA

Page burst

ICC4

4Banks Activated
t

CCD = 2CLKs

110 85 80 80 mA 1

Unit Note

mA

mA

8

mA

Refresh Current ICC5 tRC ≥ tRC(min) 180 160 150 130 mA 2

-E/C 1500

-N/L 800 5

Self Refresh Current ICC6 CKE ≤ 0.2V

-G/F

NOTES:

1. Measured with outputs open.

2. Refresh period is 64ms.

3. Internal TCSR can be supported.
In commercial Temp : Max 40°C/Max 70°C, In extended Temp : Max 40°C/Max 85°C

4. K4S283233F-F(H)E/C**

5. K4S283233F-F(H)N/L**

6. K4S283233F-F(H)G/F**

7. Unless otherwise noted, input swing IeveI is CMOS(VIH /VIL=VDDQ/VSSQ).

Internal TCSR Max 40 Max 85/70 °C 3

Full Array 500 800
1/2 of Full Array 460 650
1/4 of Full Array 440 550

uA

uA 6

4

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Mobile-SDRAM

AC OPERATING TEST CONDITIONS(VDD = 2.7V ∼ 3.6V, TA = -25 to 85°C for Extended, -25 to 70°C for Commercial)

Parameter Value Unit

AC input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr/tf = 1/1 ns
Output timing measurement reference level 1.4 V
Output load condition See Figure 2

VDDQ

1200Ω

Output

870Ω

VOH (DC) = 2.4V, IOH = -2mA
VOL (DC) = 0.4V, IOL = 2mA

30pF

Figure 1. DC Output Load Circuit

Output

Z0=50Ω

Figure 2. AC Output Load Circuit

Vtt=0.5 x VDDQ

50Ω

30pF

February 2004

K4S283233F - F(H)E/N/G/C/L/F

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Mobile-SDRAM

Parameter Symbol

Row active to row active delay tRRD(min) 12 15 19 19 ns 1
RAS to CAS delay tRCD(min) 18 19 19 24 ns 1
Row precharge time tRP(min) 18 19 19 24 ns 1

Row active time

Row cycle time tRC(min) 60 64 69 84 ns 1
Last data in to row precharge tRDL(min) 2 CLK 2
Last data in to Active delay tDAL(min) tRDL + tRP - 3
Last data in to new col. address delay tCDL(min) 1 CLK 2
Last data in to burst stop tBDL(min) 1 CLK 2
Col. address to col. address delay tCCD(min) 1 CLK 4
Number of valid output data CAS latency=3 2
Number of valid output data CAS latency=2 - 1
Number of valid output data CAS latency=1 - 0

NOTES:

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next
higher integer.

2. Minimum delay is required to complete write.

3. Minimum tRDL=2CLK and tDAL(= tRDL + tRP) is required to complete both of last data write command(tRDL) and prech arge command(tRP).

4. All parts allow every cycle column address change.

5. In case of row precharge interrupt, auto precharge and read burst stop.

tRAS(min) 42 45 50 60 ns 1

tRAS(max) 100 us

-60 -75 -1H -1L

Version

Unit Note

ea 5

February 2004

K4S283233F - F(H)E/N/G/C/L/F

AC CHARACTERISTICS(AC operating conditions unless otherwise noted)

Mobile-SDRAM

Parameter Symbol

CAS latency=3 tCC 6.0

CLK cycle time

CLK to valid output delay

Output data hold time

CLK high pulse width tCH 2.5 2.5 3 3 ns 3
CLK low pulse width tCL 2.5 2.5 3 3 ns 3
Input setup time tSS 2.0 2.0 2.5 2.5 ns 3
Input hold time tSH 1.0 1.0 1.5 1.5 ns 3
CLK to output in Low-Z tSLZ 1 1 1 1 ns 2

CLK to output in Hi-Z

CAS latency=2 tCC - 9.5 9.5 12
CAS latency=1 tCC - - - 25
CAS latency=3 tSAC 5.4 6 7 7
CAS latency=2 tSAC - 7 7 8
CAS latency=1 tSAC - - - 20
CAS latency=3 tOH 2.5 2.5 2.5 2.5
CAS latency=2 tOH - 2.5 2.5 2.5
CAS latency=1 tOH - - - 2.5

CAS latency=3
CAS latency=2 - 7 7 8

tSHZ

- 60 - 75 -1H -1L

Min Max Min Max Min Max Min Max

7.5

1000

5.4 6 7 7

1000

9.5
1000

9.5
1000 ns 1

Unit Note

ns 1,2

ns 2

ns

CAS latency=1 - - - 20

NOTES :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf) = 1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Mobile-SDRAM

SIMPLIFIED TRUTH TABLE

XL V V V

X

A11,

A9 ~ A0

Address
(A0~A7)

Address
(A0~A7)

X

Note

3

3

4

4

COMMAND CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP

Register Mode Register Set H X L L L L X OP CODE 1, 2

Refresh

Auto Refresh

Self
Refresh

Entry L 3

H

Exit L H

H

L L L H X X

L H H H
H X X X 3

X X

Bank Active & Row Addr. H X L L H H X V Row Address
Read &

Column Address

Write &
Column Address

Auto Precharge Disable
Auto Precharge Enable H 4, 5

H X L H L H X V

Auto Precharge Disable
Auto Precharge Enable H 4, 5

H X L H L L X V

L Column

L Column

Burst Stop H X L H H L X X 6

Precharge

Clock Suspend or

Bank Selection
All Banks X H

Entry H L

H X L L H L X

H X X X

V L

X

Active Power Down

Exit L H X X X X X

Entry H L
Precharge Power Down
Mode

Exit L H

H X X X
L H H H
H X X X
L V V V

X

X

DQM H X V X 7

No Operation Command H X

(V=V alid, X=Don′t Care, H=Logic High, L=Logic Low)

NOTES :

1. OP Code : Operand Code
A0 ~ A11 & BA0 ~ BA1 : Program keys . (@MRS)

2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 CLK cycles of MRS.

3. Auto refresh functions are the same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.

Partial self refresh can be issued only after setting partial self refresh mode of EMRS.

4. BA0 ~ BA1 : Bank select addresses.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at tRP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at the positive going edge of CLK masks the data-in at that same CLK in write operation (W ri te DQM latency is 0), but i n read opera tion,
it makes the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2).

H X X X
L H H H

X X

February 2004

K4S283233F - F(H)E/N/G/C/L/F

A. MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with Normal MRS

Address

BA0 ~ BA1

A11 ~ A10/AP

A9

*2

A8 A7 A6 A5 A4 A3 A2 A1 A0

Mobile-SDRAM

Function

"0" Setting for

Normal MRS

RFU

*1

W.B.L Test Mode CAS Latency BT Burst Length

Normal MRS Mode

Test Mode CAS Latency Burst Type Burst Length

A8 A7 Type A6 A5 A4 Latency A3 Type A2 A1 A0 BT=0 BT=1

0 0 Mode Register Set 0 0 0 Reserved 0 Sequential 0 0 0 1 1
0 1 Reserved 0 0 1 1 1 Interleave 0 0 1 2 2
1 0 Reserved 0 1 0 2 Mode Select 0 1 0 4 4
1 1 Reserved 0 1 1 3 BA1 BA0 Mode 0 1 1 8 8

Write Burst Length 1 0 0 Reserved

A9 Length 1 0 1 Reserved 1 0 1 Reserved Reserved

0 Burst 1 1 0 Reserved 1 1 0 Reserved Reserved
1 Single Bit 1 1 1 Reserved 1 1 1 Full Page Reserved

Register Programmed with Extended MRS

Address BA1 BA0 A11 ~ A10/AP A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Function Mode Select

RFU

*1

0 0

Setting

for Nor-

mal MRS

DS

1 0 0 Reserved Reserved

Full Page Length x32 : 128Mb(256)

RFU

*1

PASR

EMRS for PASR(Partial Array Self Ref.) & DS(Driver Strength)

Mode Select Driver Strength PASR

BA1 BA0 Mode A6 A5 Driver Strength A2 A1 A0 Size of Refreshed

0 0 Normal MRS 0 0 Full 0 0 0 Full Array
0 1 Reserved 0 1 1/2 0 0 1 1/2 of Full Array
1 0 EMRS for Mobile SDRAM 1 0 Reserved 0 1 0 1/4 of Full Array
1 1 Reserved 1 1 Reserved 0 1 1 Reserved

Reserved Address 1 0 0 Reserved

A11~A10/AP A9 A8 A7 A4 A3 1 0 1 Reserved

0 0 0 0 0 0

NOTES:

1. RFU(Reserved for future use) should stay "0" during MRS cycle.

2. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

1 1 0 Reserved
1 1 1 Reserved

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Mobile-SDRAM

Partial Array Self Refresh

1. In order to save power consumption, Mobile SDRAM has PASR option.

2. Mobile SDRAM supports 3 kinds of PASR in self refresh mode Full Array, 1/2 of Full Array and 1/4 of Full Array.

BA1=0
BA0=0

BA1=1
BA0=0

BA1=0
BA0=1

BA1=1
BA0=1

BA1=0
BA0=0

BA1=1
BA0=0

- Full Array - 1/2 Array

BA1=0
BA0=1

BA1=1
BA0=1

BA1=0
BA0=0

BA1=1
BA0=0

BA1=0
BA0=1

BA1=1
BA0=1

- 1/4 Array

Partial Self Refresh Area

Temperature Compensated Self Refresh

1. In order to save power consumption, Mobile-DRAM includes the internal temperature sensor and control units to control the self
refresh cycle automatically according to the two temperature range : Max 40 °C and Max 85 °C(for Extended), Max 70 °C(for
Commercial).

2. If the EMRS for external TCSR is issued by the controller, this EMRS code for TCSR is ignored.

Self Refresh Current (Icc6)

Temperature Range

Max 85/70 °C

Max 40 °C 500 460 440

- E/C - N/L

1500 800

Full Array 1/2 of Full Array 1/4 of Full Array

800 650 550

- G/F

Unit

uA

B. POWER UP SEQUENCE

1. Apply power and attempt to maintain CKE at a high state and all other inputs may be undefined.

- Apply VDD before or at the same time as VDDQ.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.

6. Issue a extended mode register set command to define DS or PASR operating type of the device after normal MRS.

EMRS cycle is not mandatory and the EMRS command needs to be issued only when DS or PASR is used.
The default state without EMRS command issued is the full driver strength and full array refreshed.
The device is now ready for the operation selected by EMRS.
For operating with DS or PASR, set DS or PASR mode in EMRS setting stage.
In order to adjust another mode in the state of DS or PASR mode, additional EMRS set is required but power up sequence is not
needed again at this time. In that case, all banks have to be in idle state prior to adjusting EMRS set.

February 2004

K4S283233F - F(H)E/N/G/C/L/F

Mobile-SDRAM

C. BURST SEQUENCE

1. BURST LENGTH = 4

Initial Address

A1 A0

0 0 0 1 2 3 0 1 2 3
0 1 1 2 3 0 1 0 3 2
1 0 2 3 0 1 2 3 0 1
1 1 3 0 1 2 3 2 1 0

Sequential Interleave

2. BURST LENGTH = 8

Initial Address

A2 A1 A0

0 0 0 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
0 0 1 1 2 3 4 5 6 7 0 1 0 3 2 5 4 7 6
0 1 0 2 3 4 5 6 7 0 1 2 3 0 1 6 7 4 5
0 1 1 3 4 5 6 7 0 1 2 3 2 1 0 7 6 5 4
1 0 0 4 5 6 7 0 1 2 3 4 5 6 7 0 1 2 3
1 0 1 5 6 7 0 1 2 3 4 5 4 7 6 1 0 3 2
1 1 0 6 7 0 1 2 3 4 5 6 7 4 5 2 3 0 1
1 1 1 7 0 1 2 3 4 5 6 7 6 5 4 3 2 1 0

Sequential Interleave

February 2004