Samsung K4S281632E-TCL75, K4S281632E-TCL60, K4S281632E-TC75, K4S280432E-TC75, K4S280832E-TCL75 Datasheet
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SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May. 2003
* Samsung Electronics reserves the right to change products or specification without notice.
128Mb E-die SDRAM Specification
Revision 1.2
May. 2003
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May. 2003
Revision History
Revision 1.0 (Nov. 2002)
- First release.
Revision 1.1 (Apr. 2003)
- x4/x8/x16 Merged spec.
Revision 1.2 (May. 2003)
- Delete -TC(L)7C
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May. 2003
Part No. Orgainization Max Freq. Interface Package
K4S280432E-TC(L)75 32Mb x 4 133MHz LVTTL 54pin TSOP(II)
K4S280832E-TC(L)75 16Mb x 8 133MHz LVTTL 54pin TSOP(II)
K4S281632E-TC(L)60/75 8Mb x 16 166MHz LVTTL 54pin TSOP(II)
The K4S280432E / K4S280832E / K4S281632E is 134,217,728 bits synchronous high data rate Dynamic RAM organized as 4 x
8,388,608 words by 4 bits / 4 x 4,194,304 words by 8 bits / 4 x 2,097,152 words by 16 bits, fabricated with SAMSUNG′s high perfor-
mance CMOS technology. Synchronous design allows precise cycle control with the use of system clock I/O transactions are possible
on every clock cycle. Range of operating frequencies, programmable burst length and programmable latencies allow the same device to
be useful for a variety of high bandwidth, high performance memory system applications.
• JEDEC standard 3.3V power supply
• LVTTL compatible with multiplexed address
• Four banks operation
• MRS cycle with address key programs
-. CAS latency (2 & 3)
-. Burst length (1, 2, 4 & 8 )
-. Burst type (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the system clock.
• Burst read single-bit write operation
• DQM (x4,x8) & L(U)DQM (x16) for maskin
• Auto & self refresh
• 64ms refresh period (4K Cycle)
GENERAL DESCRIPTION
FEATURES
8M x 4Bit x 4 Banks / 4M x 8Bit x 4 Banks / 2M x 16Bit x 4 Banks SDRAM
Ordering Information
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May. 2003
11.76±0.20
0.463±0.008
0.002
0.05
MIN
0.008
0.21
± 0.002
± 0.05
0.020
0.50
(
)
0.005
-0.001
+0.003
0.125
-0.035
+0.075
0.400
10.16
0.45~0.75
0.018~0.030
0.010
0.25
TYP
0~8°C
#54
#28
#1
#27
0.004
0.10
MAX
0.028
0.71
( )
0.012
0.30
0.0315
0.80
0.047
1.20
MAX
0.039
1.00
± 0.004
± 0.10
0.891
22.62
MAX
0.875
22.22
± 0.004
± 0.10
+0.10
-0.05
+0.004
-0.002
54Pin TSOP(II) Package Dimension
Package Physical Dimension
SDRAM 128Mb E-die (x4, x8, x16)
CMOS SDRAM
Rev. 1.2 May. 2003
Bank Select
Data Input Register
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Sense AMP
Output BufferI/O Control
Column Decoder
Latency & Burst Length
Programming Register
Address Register
Row Buffer
Refresh Counter
Row Decoder Col. Buffer
LRAS
LCBR
LCKE
LRAS LCBR LWE LDQM
CLK CKE CS
RAS CAS WE L(U)DQM
LWE
LDQM
DQi
CLK
ADD
LCAS LWCBR
8M x 4 / 4M x 8 / 2M x 16
8M x 4 / 4M x 8 / 2M x 16
Timing Register
* Samsung Electronics reserves the right to change products or specification without notice.
FUNCTIONAL BLOCK DIAGRAM
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