Datasheet K4S161622D-TI Datasheet (SAMSUNG)

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K4S161622D-TI/E CMOS SDRAM

1M x 16 SDRAM

512K x 16bit x 2 Banks

Synchronous DRAM

LVTTL

Industrial/ExtendedTemperature

Revision 1.2

Jan 2003

Samsung Electronics reserves the right to change products or specification without notice.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

Revision History

Revision 1.0 (June 1999)

• Define Industrial Temperature spec of K4S161622D

Revision 1.1 (June 2001)

• Add Industrial Temperature Specification.

Revision 1.2 (Jan 2003)

• Changed VDD condition of High speed (over 166MHz) from 3.135V~ 3.6V to 3.0V ~ 3.0V.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

512K x 16Bit x 2 Banks Synchronous DRAM

GENERAL DESCRIPTIONFEATURES

• 3.3V power supply

• LVTTL compatible with multiplexed address

• Dual banks operation

• MRS cycle with address key programs

-. CAS Latency ( 2 & 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system
clock

Burst Read Single-bit Write operation

•

•

DQM for masking
Auto & self refresh

•

• 15.6us refresh duty cycle (2K/32ms)

• Extended temperature range : -25°C to +85°C

• Industrial temperature range : -40°C to +85°C

FUNCTIONAL BLOCK DIAGRAM

The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol­ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem­ory system applications.

ORDERING INFORMATION

Part NO. MAX Freq. Interface Package

K4S161622D-TI/E50 200MHz
K4S161622D-TI/E55 183MHz

K4S161622D-TI/E60 166MHz

K4S161622D-TI/E70 143MHz
K4S161622D-TI/E80 125MHz
K4S161622D-TI/E10 100MHz

K4S161622D-TI* : Industrial, Normal
K4S161622D-TE* : Extended, Normal

LVTTL

50

TSOP(II)

Data Input Register

Bank Select

Refresh Counter

Row Buffer

Address Register

CLK

ADD

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS

* Samsung Electronics reserves the right to change products or specification without notice.

Row Decoder Col. Buffer

512K x 16

512K x 16

Column Decoder

Latency & Burst Length

Programming Register

LCAS LWCBR

Timing Register

RAS CAS WE L(U)DQM

Sense AMP

LWE

LDQM

Output BufferI/O Control

DQi

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

PIN CONFIGURATION (TOP VIEW)

VDD

LDQM

A10/AP

PIN FUNCTION DESCRIPTION

DQ0
DQ1

V

DQ2
DQ3

DDQ

V

DQ4
DQ5

V

DQ6
DQ7

DDQ

V

CAS
RAS

V

SSQ

SSQ

WE

CS
BA

A0
A1
A2
A3

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VSS
DQ15
DQ14

SSQ

V
DQ13
DQ12

DDQ

V
DQ11
DQ10

SSQ

V
DQ9
DQ8

DDQ

V
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4

SS

V

50PIN TSOP (II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

Pin Name Input Function

CLK System Clock Active on the positive going edge to sample all inputs.
CS

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

CKE Clock Enable

CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

A

0 ~ A10/AP Address

BA Bank Select Address

RAS

CAS

WE

Row Address Strobe

Column Address Strobe

Write Enable

L(U)DQM Data Input/Output Mask

DQ

0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.

DD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.

V
V

DDQ/VSSQ Data Output Power/Ground

N.C/RFU

No Connection/
Reserved for Future Use

Row / column addresses are multiplexed on the same pins.
Row address : RA

0 ~ RA10, column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS
Enables column access.

Enables write operation and row precharge.
Latches data in starting from CAS

Makes data output Hi-Z, t

SHZ after the clock and masks the output.

, WE active.

Blocks data input when L(U)DQM active.

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

This pin is recommended to be left No Connection on the device.

low.

low.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss V
Voltage on V

DD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature T
Power dissipation P
Short circuit current I

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage V
Input logic high votlage V
Input logic low voltage V
Output logic high voltage V
Output logic low voltage V
Input leakage current I

Note :

:

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. V

IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V

IN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

DD, VDDQ 3.0 3.3 3.6 V

IH 2.0 3.0 VDDQ+0.3 V 1

IL -0.3 0 0.8 V 2
OH 2.4 - - V IOH = -2mA
OL --0.4VIOL = 2mA
LI -10 - 10 uA 3

IN, VOUT -1.0 ~ 4.6 V

STG -55 ~ +150 °C

D 1W

OS 50 mA

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock C

RAS

, CAS, WE, CS, CKE, L(U)DQM CIN 24pF

Address C

0 ~ DQ15 COUT 35pF

DQ

CLK 24pF

ADD 24pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between V
Decoupling Capacitance between V

Note :

1. VDD and VDDQ pins are separated each other.
All V

DD pins are connected in chip. All VDDQ pins are connected in chip.

2. V

SS and VSSQ pins are separated each other

All V

SS pins are connected in chip. All VSSQ pins are connected in chip.

DD and VSS CDC1 0.1 + 0.01 uF
DDQ and VSSQ CDC2 0.1 + 0.01 uF

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, Extended TA = -25 to +85°C , Industri a l TA = -40 to +85°C)

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby Current
in power-down mode

Precharge Standby Current
in non power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down mode
(One Bank Active)

Operating Current
(Burst Mode)

CAS

Latency

Burst Length =1

I

CC1

I

CC2PCKE≤VIL(max), tCC = 15ns 2

I

CC2PS CKE & CLK≤VIL(max), tCC = ∞ 2

I

CC2N

t

RC≥tRC(min)

I

o = 0 mA

IH(min), CS≥VIH(min), tCC = 15ns

CKE≥V
Input signals are changed one time during

-50 -55 -60 -70 -80 -10

3 125 120 115 105 95 85
2 ---95 95 80

Version

30ns

IH(min), CLK≤VIL(max), tCC = ∞

CC2NS

I

I

CC3PCKE≤VIL(max), tCC = 15ns 3

I

CC3PS CKE & CLK≤VIL(max), tCC = ∞ 3

I

CC3N

CKE≥V
Input signals are stable

IH(min), CS≥VIH(min), tCC = 15ns

CKE≥V
Input signals are changed one time during
30ns

IH(min), CLK≤VIL(max), tCC = ∞

I

CC3NS

I

CC4

CKE≥V
Input signals are stable

Io = 0 mA
Page Burst 2Banks Activated
t

CCD = 2CLKs

3 160 155 150 140 130 115

2 ---115 115 100

Unit Note

mA 2

mA

15

mA

5

mA

25 mA

15 mA

mA 2

Refresh Current I

Self Refresh Current I

Note :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

CC5 tRC≥tRC(min)

CC6 CKE≤0.2V 1 mA

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

3 110 105 100 90 90 80

mA 3

2 ---90 90 80

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V

*2

, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)

Parameter Value Unit

Input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

3.3V

1200Ω

Output

870Ω

50pF

V
V

OL (DC) = 0.4V, IOL = 2mA

*2

Output

Z0=50Ω

OH (DC) = 2.4V, IOH = -2mA

(Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit

Note :

1. The DC/AC Test Output Load of K4S161622D-50/55/60/70 is 30pF.

Vtt=1.4V

50Ω

50pF

*1

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

-50 -55 -60 -70 -80 -10

CAS Latency CL 323232323232CLK
CLK cycle time t

Row active to row active delay t
RAS

to CAS delay tRCD(min) 333332323222CLK 1

Row precharge time t
Row active time
Row cycle time

Last data in to row precharge t
Last data in to new col.address delay t
Last data in to burst stop t
Col. address to col. address delay t
Mode Register Set cycle time t

Number of valid output
data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

CAS Latency=3 2
CAS Latency=2 1

CC(min) 5105.5106107108101012ns

RRD(min)

RP(min) 333332323222CLK 1

t

RAS(min) 877775756554CLK 1
RAS(max) 100 us

t

RC(min)1110101010 7 10 7 9 7 7 6 CLK 1

t

RDL(min) 1 CLK 2, 5
CDL(min) 1CLK2

BDL(min) 1CLK2
CCD(min) 1CLK
MRS(min) 2CLK

rounding off to the next higher integer. Refer to the following clock unit based AC conversion table

Version

2

Unit Note

CLK 1

ea 4

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

Parameter

CLK cycle time t
Row active to row active delay t
RAS

to CAS delay tRCD(min) 15 16.5 18 20 20 20 ns
Row precharge time t
Row active time t

Row cycle time t

Symbol Version

-50 -55 -60 -70 -80 -10

CC(min) 55.56 7 8 10ns
RRD(min) 10 11 12 14 16 20 ns

RP(min) 15 16.5 18 20 20 20 ns
RAS(min) 40 38.5 42 49 48 48 ns
RAS(max) 100 us

t

RC(min)55556069 70 70ns

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J".
From the next generation, tRDL will be only 2CLK for every clock frequency.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol

CLK cycle time

CAS Latency=3
CAS Latency=2 10 - - 10 10 12

CLK to valid
output delay

CAS Latency=3
CAS Latency=2 -6-6-6-6-6 -8

Output data t
CLK high pulse

width

CLK low pulse
width

Input setup time

CAS Latency=3
CAS Latency=2 3 3 3
CAS Latency=3
CAS Latency=2 3 3 3
CAS Latency=3

CAS Latency=2 2 2 2 2
Input hold time t
CLK to output in Low-Z t

CLK to output
in Hi-Z

CAS Latency=3

CAS Latency=2 -6-6-6-6- 6-8

t

CC

t

SAC

OH 2 - 2 - 2.5 - 2.5 - 2.5 - 2.5 - ns 2

t

CH

t

CL

t

SS

SH 1-1-1-1-1-1- ns3

SLZ 1-1-1-1-1-1-ns2

t

SHZ

-50 -55 -60 -70 -80 -10

Min Max Min Max Min Max Min Max Min Max Min Max

5

1000

5.5
1000

6

1000

7

1000

8

1000

10

-4.5-5-5.5-5.5-6-6

2

2

1.5

2

-

2

-

1.5

-

2.5

-

-

-

-3-3-3.5-ns3

2.5

-3-3-3.5-ns3

1.5

1.75

-

-2-2.5-ns3

-4.5- 5 -5.5-5.5 -6 - 6

Unit

Unit Note

1000 ns 1

ns 1, 2

ns

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~ A0 Note

Register Mode Register Set H X L L L L X OP CODE 1, 2

Refresh

Auto Refresh

Self
Refresh

Entry L 3

H

Exit L H

H

LL LHX X

LHHH

XX

3

3

HX XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Read &

Column Address

Write &
Column Address

Auto Precharge Disable

HXLHLHXV

Auto Precharge Enable H 4, 5
Auto Precharge Disable

HXLHLLXV

Auto Precharge Enable H 4, 5

Column

L

Address

0~A7)

(A

Column

L

Address

0~A7)

(A

4

4

Burst Stop H X L H H L X X 6

Precharge

Bank Selection

HXLLHLX

VL

X

Both Banks X H

Clock Suspend or
Active Power Down

Entry H L

HX XX

LVVV

X

X

Exit L H X X X X X

Entry H L

Precharge Power Down Mode

Exit L H

HX XX

LHHH

HX XX

X

X

X

LVVV
DQM H V X 7

No Operation Command H X

X

HX XX

XX

LHHH

(V=V alid, X=Don′t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code
A

0 ~ A10/AP, BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.

4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A

10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at t

RP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address
Function

BA

RFU

A

10/AP

RFU

A9

W.B.L

A

8 A7

TM

A

6 A5 A4 A3 A2 A1 A0

CAS Latency BT Burst Length

Test Mode

A8 A7 A6 A5 A4 A3 A2 A1 A0 BT = 0

0

0

1

0

0

1

1

1

Write Burst Length

A9

0
1

Type

Mode Register Set

Reserved
Reserved
Reserved

Length

Burst

Single Bit

0
0
0
0
1
1
1
1

CAS Latency

0

0

1

0

0

1

1

1

0

0

1

0

0

1

1

1

Latency

Reserved

­2
3

Reserved
Reserved
Reserved
Reserved

Burst Type

Type

0

Sequential

1

Interleave

Full Page Length : x4 (1024), x8 (512), x16 (256)

0
0
0
0
1
1
1
1

Burst Length

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

Reserved
Reserved
Reserved
Full Page

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

1
2
4
8

BT = 1

1
2
4

8
Reserved
Reserved
Reserved
Reserved

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

A1 A0

0
0
1
1

0
1
0
1

0
1
2
3

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

A1 A0A2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0

0
1
0
1
0
1
0
1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

0

Sequential Interleave

1
2
3
0

Sequential Interleave

2

3

3

4

4

5

5

6

6

7

7

0

0

1

1

2

2
3
0
1

4

5

5

6

6

7

7

0

0

1

1

2

2

3

3

4

3
0
1
2

6

7

7

0

0

1

1

2

2

3

3

4

4

5

5

6

0
1
2
3

1

0
1
2
3
4
5
6
7

2

0

3

3

0

2

1

5

6

4

7

7

4

6

5

1
0
3
2

3
2
1
0
7
6
5
4

2
3
0
1

5

4

4

5

7

6

6

7

1

0

0

1

3

2

2

3

3
2
1
0

7

6

6

7

5

4

4

5

3

2

2

3

1

0

0

1

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM opera­tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
V

IL and VIH. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and I

CC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro­zen as long as the CKE remains low. All other input s are ignore d
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + t
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.

SS" before the high going edge

ADDRESS INPUTS (A0 ~ A10/AP)

: In case x 4

The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 11 address input pins (A
AP).

The 11 bit row addresses are latched along with RAS and

BA during bank activate command. The 10 bit column
addresses are latched along with CAS
or write command.

, WE and BA during read

: In case x 8

The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 11 address input pins (A
AP). The 11 bit row addresses are latched along with RAS
BA during bank activate command. The 9 bit column addresses
are latched along with CAS
command.

, WE and BA during read or write

: In case x 16

The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A
AP). The 11 bit row addresses are latched along with RAS
BA during bank activate command. The 8 bit column addresses
are latched along with CAS
command.

, WE and BA during read or write

0 ~ A10/

0 ~ A10/

and

0 ~ A10/

and

BANK ADDRESS (BA)

: In case x 4

This SDRAM is organized as two independent banks of
2,097,152 words x 4 bits memory arrays. The BA input is latched
at the time of assertion of RAS
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.

: In case x 8

This SDRAM is organized as two independent banks of
1,048,576 words x 8 bits memory arrays. The BA input is latched
at the time of assertion of RAS
used for the operation. The bank select BA
active, read, write, mode register set and precharge operations.

: In case x 16

This SDRAM is organized as two independent banks of 524,288
words x 16 bits memory arrays. The BA input is latched at the
time of assertion of RAS
for the operation. The bank select BA is latched at bank active,
read, write, mode register set and precharge operations.

and CAS to select the bank to be

and CAS to select the bank to be

is latched at bank

and CAS to select the bank to be used

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin­gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS

high. CS high disables the command decoder so that RAS,

CAS

, WE and all the address inputs are ignored.

POWER-UP

SDRAMs must be powered up and initialized in a pre­defined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.

3. Issue precharge commands for both banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode reg­ ister.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DEVICE OPERATIONS (Continued)

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS
RAS

, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A

, CAS and WE going low is the data written in the mode

RAS

0 ~ A10/AP and BA in the same cycle as CS,

register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A

3, CAS latency (read latency from column address) uses A4 ~

A

6, vendor specific options or test mode use A7 ~ A8, A10/AP

A
and BA. The write burst length is programmed using A

10/AP, BA must be set to low for normal SDRAM operation.

A

0 ~ A2, burst type uses

9. A7 ~ A8,

Refer to the table for specific codes for various burst length,
burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of t

RCD

of bank activation. t

is an internal timing parameter of
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing t

RCD(min) with cycle time of the clock and then rounding

off the result to the next higher integer. The SDRAM has two
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of two banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before the other bank can be sensed
reliably. t

RRD(min) specifies the minimum time required between

activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to

RCD specification. The minimum time required for the bank to be

t

and CS with desired row

RCD(min) from the time

active to initiate sensing and restoring the complete row of
dynamic cells is determined by t
activate command must satisfy t

RAS(min). Every SDRAM bank

RAS(min) specification before a

precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by t

RAS(max). The number of cycles for both tRAS(min) and

RAS(max) can be calculated similar to tRCD specification.

t

,

BURST READ

The burst read command is used to access burst of data on con­secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS
with WE being high on the positive edge of the clock. The bank
must be active for at least t

RCD(min) before the burst read com-

mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com­mand is determined by the mode register which is already pro­grammed. The burst read can be initiated on any column
address of the active row. The address wrap s around if the initial
address does not start from a boundary such that number of out­puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com­pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank t
last data input to be written into the active row. See DQM
OPERA T ION also.

, CAS and WE with valid

and CAS

RDL after the

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DEVICE OPERATIONS (Continued)

DQM OPERATION

The DQM is used to mask input and output operations. It works
similar to OE
write operation. The read latency is two cycles from DQM and
zero cycle for write, which means DQM masking occurs two
cycles later in read cycle and occurs in the same cycle during
write cycle. DQM operation is synchronous with the clock. The
DQM signal is important during burst interruptions of write with
read or precharge in the SDRAM. Due to asynchronous nature
of the internal write, the DQM operation is critical to avoid
unwanted or incomplete writes when the complete burst write is
not required. Please refer to DQM timing diagram also.

during read operation and inhibits writing during

PRECHARGE

The precharge operation is performed on an active bank by
asserting low on CS
bank to be precharged. The precharge command can be
asserted anytime after t
command in the desired bank. t
number of clock cycles required to complete row precharge is
calculated by dividing t
to the next higher integer. Care should be taken to make sure
that burst write is completed or DQM is used to inhibit writing
before precharge command is asserted. The maximum time any
bank can be active is specified by t
bank activate command. At the end of precharge, the bank
enters the idle state and is ready to be activated again. Entry to
Power down, Auto refresh, Self refresh and Mode register set
etc. is possible only when both banks are in idle state.

, RAS, WE and A10/AP with valid BA of the

RAS(min) is satisfied from the bank active

RP is defined as the minimum

RP with clock cycle time and rounding up

RAS(max). Therefore, each

AUTO PRECHARGE

The precharge operation can also be performed by using auto
precharge. The SDRAM internally generates the timing to satisfy
t

RAS(min) and "tRP" for the programmed burst length and CAS

latency. The auto precharge command is issued at the same
time as burst read or burst write by asserting high on A
burst read or burst write by asserting high on A
left active until a new command is asserted. Once auto
precahrge command is given, no new commands are possible to
that particular bank until the bank achieves idle state.

10/AP, the bank is

10/AP. If

BOTH BANKS PRECHARGE

Both banks can be precharged at the same time by using pre­charge all command. Asserting low on CS
high on A
requirement, performs precharge on both banks. At the end of
t

RP after performing precharge to all the banks, both banks are

in idle state.

10/AP after both banks have satisfied tRAS(min)

, RAS, and WE with

AUTO REFRESH

The storage cells of SDRAM need to be refreshed every 32ms
to maintain data. An auto refresh cycle accomplishes refresh of
a single row of storage cells. The internal counter increments
automatically on every auto refresh cycle to refresh all the rows.
An auto refresh command is issued by asserting low on CS
RAS

and CAS with high on CKE and WE. The auto refresh com­mand can only be asserted with both banks being in idle state
and the device is not in power down mode (CKE is high in the
previous cycle). The time required to complete the auto refresh
operation is specified by t
clock cycles required can be calculated by driving t
clock cycle time and them rounding up to the next higher integer .
The auto refresh command must be followed by NOP's until the
auto refresh operation is completed. Both banks will be in the
idle state at the end of auto refresh operation. The auto refresh
is the preferred refresh mode when the SDRAM is being used
for normal data transactions. The auto refresh cycle can be per­formed once in 15.6us or a burst of 2048 auto refresh cycles
once in 32ms.

RFC(min). The minimum number of

RFC with

SELF REFRESH

The self refresh is another refresh mode available in the
SDRAM. The self refresh is the preferred refresh mode for data
retention and low power operation of SDRAM. In self refresh
mode, the SDRAM disables the internal clock and all the input
buffers except CKE. The refresh addressing and timing are
internally generated to reduce power consumption.
The self refresh mode is entered from both banks idle state by
asserting low on CS
Once the self refresh mode is entered, only CKE state being low
matters, all the other inputs including the clock are ignored in
order to remain in the self refresh mode.
The self refresh is exited by restarting the external clock and
then asserting high on CKE. This must be followed by NOP's for
a minimum time of t
begin normal operation. If the system uses burst auto refresh
during normal operation, it is recommended to use burst 2048
auto refresh cycles immediately after exiting in self refresh
mode.

, RAS, CAS and CKE with high on WE.

RFC before the SDRAM reaches idle state to

,

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

BASIC FEATURE AND FUNCTION DESCRIPTIONS

1. CLOCK Suspend

1) Clock Suspended During Write (BL=4)

CLK

CMD

CKE

Internal

CKE

DQ(CL2)
DQ(CL3)

2. DQM Operation

1) Write Mask (BL=4)

CLK

CMD
DQM

DQ(CL2)
DQ(CL3)

WR

Masked by CKE

D0 D1 D2 D3
D0 D1 D2 D3

Not Written

WR

Masked by DQM

D0 D1 D3
D0 D1 D3

2) Clock Suspended During Read (BL=4)

RD

Masked by CKE

D0

Q0 Q1 Q2

Q0 Q1

Suspended Dout

2) Read Mask (BL=4)

RD

Masked by DQM

Hi-Z

Q0 Q2 Q3

Hi-Z

Q1

Q3
Q2 Q3

Q2 Q3

DQM to Data-in Mask = 0 DQM to Data-out Mask = 2

3) DQM with Clock Suspended (Full Page Read)
CLK

CMD

CKE

DQM

DQ(CL2)
DQ(CL3)

*Note : 1. CKE to CLK disable/enable = 1CLK.

2. DQM makes data out Hi-Z after 2CLKs which should masked by CKE " L"

3. DQM masks both data-in and data-out.

RD

Q0 Q4 Q7 Q8Q2

Note 2

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Hi-Z

Q3 Q6 Q7Q1

Hi-Z

Q6
Q5

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

3. CAS Interrupt (I)

1) Read interrupted by Read (BL=4)

CLK

CMD

ADD

DQ(CL2)

RD RD

A B

QA0 QB1 QB2 QB3QB0

DQ(CL3)

tCCD
Note 2

2) Write interrupted by Write (BL=2)
CLK

CMD

ADD

DQ

WR WR

tCCD Note 2

A B

DA0 DB1DB0

tCDL
Note 3

Note 1

QA0 QB1 QB2 QB3QB0

3) Write interrupted by Read (BL=2)

WR RD

tCCD Note 2

A B

DQ(CL2)
DQ(CL3)

DA0 QB1QB0
DA0 QB1QB0

tCDL
Note 3

*Note : 1. By " Interrupt", It is meant to stop burst read/write by external command before the end of burst.

By "CAS

2. t

3. t

Interrupt", to stop burst read/write by CAS access ; read and write.

CCD : CAS to CAS delay. (=1CLK)
CDL : Last data in to new column address delay. (=1CLK)

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

4. CAS Interrupt (II) : Read Interrupted by Write & DQM

(a) CL=2, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

DQM

DQ

iii) CMD

DQM

DQ

iv) CMD

DQM

DQ

(b) CL=3, BL=4

CLK

i) CMD

DQM

DQ

ii) CMD

WR

D1 D2RDD3

D0

RD WR

Hi-Z

RD WR

RD WR

WR

D0

RD WR

D1 D2 D3D0

Hi-Z

Hi-Z

Q0 D1 D2 D3D0

Note 1

D1 D2RDD3

D1 D2 D3D0

DQM

Q0

D1 D2 D3D0

Hi-Z

D1 D2 D3D0

D

Hi-Z

Note 1

0

D1D2D

D1 D2 D3D0

3

DQ

iii) CMD

DQM

DQ

iii) CMD

DQM

DQ

iv) CMD

DQM

DQ

*Note : 1. To prevent bus contention, there should be at least one gap between data in and data out.

RD WR

RD WR

RD WR

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

5. Write Interrupted by Precharge & DQM

CLK

Note 3

CMD

DQM

WR

PRE

Note 2

DQ

*Note : 2. To inhibit invalid write, DQM should be issued.

3. This precharge command and burst write command should be of the same bank, otherwise it is not precharge
interrupt but only the other bank precharge of dual banks operation.

D0 D1 D2

D3

Masked by DQM

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

6. Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

2) Normal Read (BL=4)

CLK

CMD

DQ(CL2)

DQ(CL3)

7. Auto Precharge

1) Normal Write (BL=4)
CLK

CMD

DQ

2) Normal Read (BL=4)

WR PRE

D0 D1 D2

RD PRE

WR

D0 D1 D2

D3

tRDL
Note 2

Q0 Q1 Q2

Q0 Q1 Q2 Q3

D3

Note 3
Auto Precharge Starts

Q3

1

Note 2

2

CLK

CMD

DQ(CL2)

DQ(CL3)

*Note : 1. t

RDL

: Last data in to row precharge delay

2. Number of valid output data after row precharge : 0, 1, 2 for CAS Latency =1, 2, 3 respectively.

3. The row active command of the precharge bank can be issued after tRP from this point.

The new read/write command of the other activated bank can be issued from this point.
At burst read/write with auto precharge, CAS interrupt of the same/other bank is illegal.

RD

Q0 Q1 Q2

Q0 Q1 Q2

Note 3
Auto Precharge Starts

Q3

Q3

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

8. Burst Stop & Interrupted by Precharge

9. MRS

1) Normal Write (BL=4)

CLK

CMD

WR PRE

DQM

DQ

D0 D1 D2

tRDL Note 1

3) Read Interrupted by Precharge (BL=4)

CLK

CMD

DQ(CL2)

RD PRE

Q0 Q1

DQ(CL3)

D3

1

Note 3

Q0 Q1

2) Write Burst Stop (BL=8)
CLK

CMD

WR STOP

DQM

DQ

D0 D1 D2

D3

tBDL Note 2

D4 D5

4) Read Burst Stop (BL=4)

CLK

CMD

DQ(CL2)

2

DQ(CL3)

RD STOP

Q0 Q1

1

Note 3

Q0 Q1

2

1) Mode Register Set
CLK

*Note : 1. t

2. t

CMD

RDL

: 1 CLK

BDL : 1 CLK ; Last data in to burst stop delay .

Note 4

PRE

tRP tMRS = 2CLK

MRS ACT

Read or write burst stop command is valid at every burst length.

3. Number of valid output data after row precharge or burst stop : 1, 2 for CAS latency= 2, 3 respectiviely.

4. PRE : Both banks precharge if necessary.

MRS can be issued only at both banks precharge state.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

10. Clock Suspend Exit & Power Down Exit

1) Clock Suspend (=Active Power Down) Exit

CLK

CKE

Internal

CLK

Note 1

CMD

11. Auto Refresh & Self Refresh

1) Auto Refresh & Self Refresh

CLK

CMD

PRE

CKE

2) Self Refresh

Note 6

CLK

CMD

PRE

Note 3

Note 4

tRP tRFC

Note 4

2) Power Down (=Precharge Power Down)

tSS

Internal

RD

¡ó

AR CMD

¡ó
¡ó

¡ó

¡ó

SR

CLK

CKE

CLK

CMD

Note 5

Note 2

CMD

NOP

tSS

ACT

CKE

¡ó

tRP tRFC

¡ó

*Note : 1. Active power down : one or both banks active state.

2. Precharge power down : both banks precharge state.

3. The auto refresh is the same as CBR refresh of conventional DRAM.

No precharge commands are required after auto refresh command.
During tRFC from auto refresh command, any other command can not be accepted.

4. Before executing auto/self refresh command, both banks must be idle state.

5. MRS, Bank Active, Auto/Self Refresh, Power Down Mode Entry.

6. During self refresh mode, refresh interval and refresh operation are perfomed internally.

After self refresh entry, self refresh mode is kept while CKE is low.
During self refresh mode, all inputs expect CKE will be don't cared, and outputs will be in Hi-Z state.
For the time interval of tRFC from self refresh exit command, any other command can not be accepted. Before/Afte r self refresh mode , burst
auto refresh cycle (2048 cycles) is recommended.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

12. About Burst Type Control

Basic

MODE

Random

MODE

Sequential Counting

Interleave Counting

Random column Access

t

CCD = 1 CLK

13. About Burst Length Control

1

Basic

MODE

Special
MODE

Random

MODE

Interrupt

MODE

(Interrupted by Precharge)

2

4
8

Full Page

BRSW

Burst Stop

RAS

Interrupt

CAS Interrupt

At MRS A3 = "0". See the BURST SEQUENCE TABLE. (BL=4,8)
BL=1, 2, 4, 8 and full page.At Full page wrap-around.

At MRS A
BL=4, 8. At BL=1, 2 Interleave Counting = Sequential Counting

Every cycle Read/Write Command with random column address can realize
Random Column Access.
That is similar to Extended Data Out (EDO) Operation of conventional DRAM.

At MRS A2,1,0 = "000".
At auto precharge, tRAS should not be violated.

At MRS A
At auto precharge, tRAS should not be violated.

At MRS A2,1,0 = "010".
At MRS A
At MRS A

Wrap around mode(Infinite burst length)should be stopped by burst stop,
RAS interrupt or CAS interrupt.

At MRS A
Read burst=1,2,4,8,full page Write burst=1
At auto precharge of write, tRAS should not be violate

tBDL= 1, Valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively
Using burst stop command, any burst length control is possible.

Before the end of burst, Row precharge command of the same bank stops read/write
burst with Row precharge.
t
During read/write burst with auto precharge, RAS interrupt can not be issued.

Before the end of burst, new read/write stops read/write burst and starts new
read/write burst.
During read/write burst with auto precharge, CAS interrupt can not be issued.

3 = "1". See the BURST SEQUENCE TABLE. (BL=4,8)

2,1,0 = "001".

2,1,0 = "011".
2,1,0 = "111".

9 = "1".

RDL= 1 with DQM, valid DQ after burst stop is 1, 2 for CAS latency 2, 3 respectively.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

IDLE

Row

Active

Read

Write

Read with

Auto

Precharge

Write with

Auto

Precharge

Pre-

charging

CS RAS CAS WE BA ADDR ACTION Note

NOP

H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L
H
L
L
L
L
L

X
H
H
H
L
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
H
L
L
L
X
H
H
H
L
L
X
H
H
H
L
L
X
H
H
H
L
L

X
H
H
L
H
H
L
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
L
H
H
L
X
H
H
L
H
L
X
H
H
L
H
L
X
H
H
L
H
H

X

H

L
X

H

L

H

L
X

H

L

H

L

H

L
X
X

H

L

H

L

H

L
X
X

H

L

H

L

H

L
X
X

H

L
X
X
X
X

H

L
X
X
X
X

H

L
X

H

L

X
X

X
BA
BA
BA

X

OP code

X

X

X
BA
BA
BA
BA

X

X

X

X
BA
BA
BA
BA

X

X

X

X
BA
BA
BA
BA

X

X

X

X
BA
BA

X

X

X

X
BA
BA

X

X

X

X
BA
BA
BA

X
X
X

CA, A10/AP

RA

A10/AP

X

OP code

X
X

X
CA, A10/AP
CA, A10/AP

RA

10/AP

A

X

X

X

X
CA, A

10/AP

CA, A10/AP

RA

A10/AP

X

X

X

X
CA, A10/AP
CA, A10/AP

RA

A10/AP

X

X

X

X
CA, A10/AP

10

RA, RA

X

X

X

X
CA, A10/AP

RA, RA10

X

X

X

X

CA
RA

A10/AP

NOP
ILLEGAL
ILLEGAL
Row (& Bank) Active ; Latch RA
NOP
Auto Refresh or Self Refresh
Mode Register Access
NOP
NOP
ILLEGAL
Begin Read ; latch CA ; determine AP
Begin Write ; latch CA ; determine AP
ILLEGAL
Precharge
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New Read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, Precharge timing for Reads
ILLEGAL
NOP (Continue Burst to End --> Row Active)
NOP (Continue Burst to End --> Row Active)
Term burst --> Row active
Term burst, New read, Determine AP
Term burst, New Write, Determine AP
ILLEGAL
Term burst, precharge timing for Writes
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Continue Burst to End --> Precharge)
NOP (Continue Burst to End --> Precharge)
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after t
NOP --> Idle after tRP
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after tRPL

RP

2
2

4
5
5

2

2

3
2

3
3
2
3

2

2

2
2
2
4

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

FUNCTION TRUTH TABLE (TABLE 1)

Current

State

Row

Activating

Refreshing

Mode

Register

Accessing

Abbreviations : RA = Row Address BA = Bank Address
NOP = No Operation Command CA = Column Address AP = Auto Precharge

CS RAS CAS WE BA ADDR ACTION Note

L
H
L
L
L
L
L
L
H
L
L
L
L
H
L
L
L
L

L
X
H
H
H
L
L
L
X
H
H
L
L
X
H
H
H
L

L
X
H
H
L
H
H
L
X
H
L
H
L
X
H
H
L
X

X
X

H

L
X

H

L
X
X
X
X
X
X
X

H

L
X
X

X
X
X

X
BA
BA
BA

X

X

X

X

X

X

X

X

X

X

X

X
X
X

X
CA
RA

A10/AP

X

X

X

X

X

X

X

X

X

X

X

ILLEGAL
NOP --> Row Active after t
NOP --> Row Active after tRCD
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after t
NOP --> Idle after tRFC
ILLEGAL
ILLEGAL
ILLEGAL
NOP --> Idle after 2 clocks
NOP --> Idle after 2 clocks
ILLEGAL
ILLEGAL
ILLEGAL

RCD

RFC

2
2
2
2

*Note : 1. All entries assume the CKE was active (High) during the precharge clock and the current clock cycle.

2. Illegal to bank in specified state ; Function may be Iegal in the bank indicated by BA, depending on the
state of that bank.

3. Must satisfy bus contention, bus turn around, and/or write recovery requirements.

4. NOP to bank precharging or in idle state. May precharge bank indicated by BA (and A10/AP).

5. Illegal if any bank is not idle.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

FUNCTION TRUTH TABLE (TABLE 2)

Current

State

Self

Refresh

All

Banks

Precharge

Power

Down

All

Banks

Idle

Any State
other than

Listed
above

Abbreviations : ABI = All Banks Idle, RA = Row Address

CKE
(n-1)

CKE

n
H
L
L
L
L
L
L
H
L
L
L
L
L
L
H
H
H
H
H
H
H
H
L
H
H
L
L

X

H

H

H

H

H

L

X

H

H

H

H

H

L

H

L

L

L

L

L

L

L

L

H

L

H

L

CS RAS CAS WE ADDR ACTION Note

X
H
L
L
L
L
X
X
H
L
L
L
L
X
X
H
L
L
L
L
L
L
X
X
X
X
X

X
X
H
H
H
L
X
X
X
H
H
H
L
X
X
X
H
H
H
L
L
L
X
X
X
X
X

X
X
H
H

L
X
X
X
X
H
H

L
X
X
X
X
H
H

L
H

L

L
X
X
X
X
X

X

X
H
L
X
X
X
X
X
H
L
X
X
X
X
X
H
L
X
H
H
L
X
X
X
X
X

X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X

RA

X

OP Code

X
X
X
X
X

INVALID
Exit Self Refresh --> Idle after tRFC (ABI)
Exit Self Refresh --> Idle after tRFC (ABI)
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Self Refresh)
INVALID
Exit Power Down --> ABI
Exit Power Down --> ABI
ILLEGAL
ILLEGAL
ILLEGAL
NOP (Maintain Low Power Mode)
Refer to Table 1
Enter Power Down
Enter Power Down
ILLEGAL
ILLEGAL
Row (& Bank) Active
Enter Self Refresh
Mode Register Access
NOP
Refer to Operations in Table 1
Begin Clock Suspend next cycle
Exit Clock Suspend next cycle
Maintain Clcok Suspend

6
6

7
7

8
8

8

9
9

*Note : 6. CKE low to high transition is asynchronous.

7. CKE low to high transition is asynchronous if restarts internal clock.
A minimum setup time 1CLK + t

8. Power down and self refresh can be entered only from the both banks idle state.

9. Must be a legal command.

SS must be satisfied before any command other than exit.

Rev 1.2 Jan '03

K4S161622D-TI/E

Single Bit Read-Write-Read Cycle(Same Page) @CAS Latency=3, Burst Length=1

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

10/AP

A

12

0

tCC

*Note 1

tRCD

tSH

tSS

tSH

tSS

BS BS BS BS BS BS

Ra

tCH

3

4

56

tCL

tRAS
tRC

tSH

tSS

*Note 2,3*Note 2 *Note 2

7

8

HIGH

tSH

tSS

tSH

*Note 2,3 *Note 2,3 *Note 4

9

tSS

tCCD

10

11

12 13

tRP

*Note 4*Note 3*Note 3*Note 3

14

RbCcCbCaRa

Rb

15

16 17

18

19

DQ

WE

DQM

tRAC

Row Active Read Write Read Row Active

tSAC

tSLZ

tOH

tSH

tSS

tSS

tSH

QcDbQa

tSS

tSH

Precharge

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

*Note : 1. All inputs expect CKE & DQM can be don ¡Çt care when CS is high at the CLK high going edge.

0

12

2. Bank active & read/write are controlled by BA.

3. Enable and disable auto precharge function are controlled by A10/AP in read/write command.

3

BA

CMOS SDRAM

4

56

Active & Read/Write
0
1

Bank A
Bank B

7

8

10

9

11

12 13

14

15

16 17

18

19

0

1

A10/AP

0
0
1

BA

0

Disable auto precharge, leave bank A active at end of burst.

1

Disable auto precharge, leave bank B active at end of burst.

0

Enable auto precharge, precharge bank A at end of burst.

1

Enable auto precharge, precharge bank B at end of burst.

BA

0
1
X

Precharge

Bank A
Bank B

Both Banks

A10/AP

4. A10/AP and BA control bank precharge when precharge command is asserted.

Operation

Rev 1.1 Jun '01

K4S161622D-TI/E

Power Up Sequence

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

12

0

High level is necessary

tRP tRC

3

4

56

7

8

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

10

9

11

12 13

∼

∼

∼

∼

∼

∼

tRC

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

14

15

16 17

Key

RAa

RAa

18

19

DQ

WE

DQM

High-Z

High level is necessary

Precharge Auto Refresh Auto Refresh Mode Register Set
(All Banks)

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

Rev 1.1 Jun '01

Row Active

(A-Bank)

: Don't care

K4S161622D-TI/E

Read & Write Cycle at Same Bank @Burst Length=4

CMOS SDRAM

CLOCK

CKE

RAS

CAS

ADDR

10/AP

A

DQ

CS

BA

CL=2

0

12

3

4

56

7

8

10

9

11

12 13

HIGH

*Note 1

tRC

tRCD

*Note 2

Ra Ca0 Rb Cb0

Ra Rb

tOH

Qa0 Qa1 Qa2 Qa3

tRAC

*Note 3

tSAC

tSHZ

*Note 4

14

15

16 17

Db0 Db1 Db2 Db3

18

tRDL

19

CL=3

WE

DQM

tOH

tRAC

*Note 3

Row Active

(A-Bank)

*Note : 1. Minimum row cycle times is required to complete internal DRAM operation.

2. Row precharge can interrupt burst on any cycle. [CAS Latency - 1] number of valid output data
is available after Row precharge. Last valid output will be Hi-Z(tSHZ) after the clcok.

3. Access time from Row active command. t

4. Ouput will be Hi-Z after the end of burst. (1, 2, 4, 8 & Full page bit burst wrap-around).

Read

(A-Bank)

Qa0 Qa1 Qa2 Qa3

tSAC

Precharge

(A-Bank)

CC *(tRCD + CAS latency - 1) + tSAC

*Note 4

tSHZ

Row Active

(A-Bank)

Db0 Db1 Db2 Db3

Write

(A-Bank)

tRDL

Precharge

(A-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Page Read & Write Cycle at Same Bank @Burst Length=4

CMOS SDRAM

CLOCK

CKE

RAS

CAS

ADDR

10/AP

A

DQ

CS

BA

CL=2

0

12

3

4

56

7

8

10

9

11

12 13

HIGH

tRCD

Ra Ca0 Cb0 Cc0 Cd0

Ra

Qa0 Qa1 Qb0 Qb1

Qb2

Dc0 Dc1 Dd0 Dd1

14

15

tRDL

16 17

*Note 2

18

19

CL=3

WE

DQM

Row Active

(A-Bank)

*Note :

Qa0 Qa1 Qb0 Qb1

*Note 1 *Note 3

Read

(A-Bank)

1. To write data before burst read ends, DQM should be asserted three cycle prior to write
command to avoid bus contention.

2. Row precharge will interrupt writing. Last data input, t

3. DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.

Read

(A-Bank)

RDL before Row precharge, will be written.

Dc0 Dc1 Dd0 Dd1

tCDL

Write

(A-Bank)

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Page Read Cycle at Different Bank @Burst Length=4

CMOS SDRAM

CLOCK

CKE

RAS

CAS

ADDR

A

10/AP

DQ

CS

BA

CL=2

CL=3

12

0

*Note 1

RAa RBb

RAa RBb

CAa

3

4

56

7

8

10

9

11

12 13

14

15

16 17

18

19

HIGH

*Note 2

CBb CBd

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

QAa0 QAa1 QAa2 QAa3 QBb0 QBb1 QBb2 QBb3 QAc0 QAc1 QBd0 QBd1 QAe0 QAe1

CAc CAe

WE

DQM

Row Active

(A-Bank)

*Note :

Row Active

(B-Bank)

Read

(A-Bank)

1. CS

can be don't cared when RAS, CAS and WE are high at the clock high going dege.

2. To interrupt a burst read by row precharge, both the read and the precharge banks must be the same.

Read

(B-Bank)

Read

(A-Bank)

Read

(B-Bank)

Read

(A-Bank)

Rev 1.1 Jun '01

Precharge

(A-Bank)

: Don't care

K4S161622D-TI/E

Page Write Cycle at Different Bank @Burst Length=4

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

0

12

3

4

56

7

8

10

9

11

12 13

HIGH

RAa CAa CBb CAc CBd

RAa

RBb

RBb

14

15

16 17

*Note 2

18

19

DQ

WE

DQM

Row Active

(A-Bank)

*Note :

DAa0 DAa1 DAa2 DAa3 DBb0 DBb1 DBb2 DBb3 DAc0 DAc1 DBd0 DBd1

tCDL

Row Active

(B-Bank)

Write

(A-Bank)

1. To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.

2. To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.

Write

(B-Bank)

Write

(A-Bank)

Write

(B-Bank)

tRDL

*Note 1

Precharge

(Both Banks)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Read & Write Cycle at Different Bank @Burst Length=4

CMOS SDRAM

CLOCK

CKE

RAS

CAS

ADDR

10/AP

A

DQ

CS

BA

CL=2

CL=3

0

12

3

4

56

7

8

10

9

11

12 13

14

HIGH

RAa CAa RBb CBb RAc CAc

RAcRAa RBb

QAa0 QAa1 QAa2 QAa3

QAa0 QAa1 QAa2 QAa3

DBb0 DBb1 DBb2 DBb3

DBb0 DBb1 DBb2 DBb3

15

tCDL

16 17

*Note 1

18

19

QAc0 QAc1 QAc2

QAc0 QAc1

WE

DQM

Row Active

(A-Bank)

*Note :

Read

(A-Bank)

Row Active

(B-Bank)

1. t

CDL should be met to complete write.

Precharge

(A-Bank)

Write

(B-Bank)

Row Active

Read

(A-Bank)

(A-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Read & Write Cycle with Auto Precharge I @Burst Length=4

CMOS SDRAM

CLOCK

CKE

RAS

CAS

ADDR

A

10/AP

DQ

CS

BA

CL=2

CL=3

12

0

Ra Rb Ca

Ra Rb

3

4

56

Qa0 Qa1 Qb0 Qb1

7

8

Cb

Qa0 Qa1 Qb0 Qb1

9

HIGH

10

Qb2

11

12 13

Qb3

Qb2

Qb3

14

Ra

Ra

15

16 17

18

19

Ca

Da0 Da1

Da0 Da1

WE

DQM

Row Active

(A-Bank)

*Note:

Read with

Auto Pre

charge

(A-Bank)

Row Active

(B-Bank)

* When Read(Write) command with auto precharge is issued at A-Bank af ter A and B Bank activation.

- if Read(Write) command without auto precharge is issued at B-Bank before A Bank auto precharge starts, A Bank
auto precharge will start at B Bank read command input point .

- any command can not be issued at A Bank during tRP after A Bank auto precharge starts.

Read without Auto
precharge(B-Bank)

Auto Precharge

Start Point

(A-Bank)*

Precharge

(B-Bank)

Row Active

(A-Bank)

Write with

Auto Precharge

(A-Bank)

Rev 1.1 Jun '01

: Don't care

K4S161622D-TI/E

Read & Write Cycle with Auto Precharge II @Burst Length=4

CMOS SDRAM

CLOCK

CKE

RAS

CAS

ADDR

A

10/AP

DQ

CS

BA

CL=2

CL=3

12

0

Ra Ca

Ra

3

4

56

Qa0 Qa1 Qa2 Qa3

7

8

9

HIGH

Rb

Rb

Qa0 Qa1 Qa2 Qa3

10

Cb

11

12 13

14

Qb0 Qb1 Qb2 Qb3

Qb0 Qb1 Qb2 Qb3

15

16 17

18

19

WE

DQM

Row Active

(A-Bank)

*Note :

*

Read with

Auto Precharge

(A-Bank)

* Any command to A-bank is not allowed in this period.
tRP is determined from at auto precharge start point

Auto Precharge

Start Point

(A-Bank)

Row Active

(B-Bank)

Read with

Auto Precharge

(B-Bank)

Auto Precharge

Start Point

(B-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Clock Suspension & DQM Operation Cycle @CAS Latency=2, Burst Length=4

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

12

0

Ra Ca Cb Cc

Ra

3

4

56

7

8

10

9

11

12 13

14

15

16 17

18

19

DQ

WE

DQM

Row Active Clock

*Note : 1. DQM is needed to prevent bus contention.

Read

Suspension

Qa3Qa2Qa1Qa0

tSHZ

Read Write

tSHZ

*Note 1

Read DQM

Write

Dc2Dc0Qb1Qb0

Write
DQM

Clock

Suspension

Rev 1.1 Jun '01

DQM

: Don't care

K4S161622D-TI/E

CMOS SDRAM

Read Interrupted by Precharge Command & Read Burst Stop Cycle @Burst Length=Full page

CLOCK

CKE

RAS

CAS

ADDR

A

10/AP

DQ

CS

BA

CL=2

CL=3

0

12

3

4

56

7

8

9

HIGH

RAa CAa CAb

RAa

QAa0 QAa1 QAa2 QAa3 QAa4

QAa0 QAa1 QAa2 QAa3 QAa4

10

11

12 13

1

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

*Note 2

2

14

15

16 17

QAb0 QAb1 QAb2 QAb3 QAb4 QAb5

18

1

19

2

WE

DQM

Row Active

(A-Bank)

*Note :

(A-Bank)

Burst StopRead

1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. About the valid DQs after burst stop, it is same as the case of RAS
Both cases are illustrated above timing diagram. See the label 0. 1, 2 on them.
But at burst write, Burst stop and RAS interrupt should be compared carefully.
Refer the timing diagram of "Full page write burst stop cycle".

3. Burst stop is valid at every burst length.

Read

(A-Bank)

interrupt.

Precharge

(A-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

CMOS SDRAM

Write Interrupted by Precharge Command & Write Burst Stop Cycle @ Burst Length=Full page

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

DQ

0

12

3

4

56

7

8

9

HIGH

RAa CAa CAb

RAa

tBDL

DAa0 DAa1 DAa2 DAa3 DAa4

10

11

12 13

DAb0 DAb1 DAb2 DAb3 DAb4 DAb5

14

15

16 17

tRDL

*Note 2

18

19

WE

DQM

Row Active

(A-Bank)

*Note :

Write

(A-Bank)

1. At full page mode, burst is wrap-around at the end of burst. So auto precharge is impossible.

2. Data-in at the cycle of interrupted by precharge can not be written into the corresponding
memory cell. It is defined by AC parameter of t
DQM at write interrupted by precharge command is needed to prevent invalid write.
DQM should mask invalid input data on precharge command cycle when asserting precharge
before end of burst. Input data after Row precharge cycle will be masked internally.

3. Burst stop is valid at every burst length.

Burst Stop

RDL.

Write

(A-Bank)

Precharge

(A-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Burst Read Single bit Write Cycle @Burst Length=2

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

DQ

CL=2

CL=3

12

0

*Note 1

RAa CAa RBb CAb RAc CBc CAd

3

4

56

DAa0

DAa0

7

QAb0 QAb1

8

10

9

11

12 13

HIGH

RAcRAa RBb

DBc0 QAd0 QAd1

QAb0 QAb1 DBc0

*Note 2

14

15

16 17

18

19

QAd0 QAd1

WE

DQM

Row Active

(A-Bank)

*Note :

Row Active

(B-Bank)

Write

(A-Bank)

1. BRSW modes is enabled by setting A
At the BRSW Mode, the burst length at write is fixed to "1" regaredless of programmed burst length.

2. When BRSW write command with auto precharge is executed, keep it in mind that t
Auto precharge is executed at the burst-end cycle, so in the case of BRSW write command,
the next cycle starts the precharge.

Read with

Auto Precharge

(A-Bank)

9 "High" at MRS (Mode Register Set).

Row Active

(A-Bank)

Read

(A-Bank)

Write with

Auto Precharge

(B-Bank)

RAS should not be violated.

Precharge

(A-Bank)

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Active/Precharge Power Down Mode @CAS Latency=2, Burst Length=4

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

DQ

0

12

tSS

*Note 1

3

∼

∼

∼

∼

∼

∼

*Note 3

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

4

*Note 2

56

Ra Ca

Ra

7

8

tSS

10

9

∼

∼

tSS

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

11

*Note 2

12 13

Qa0

14

Qa1

15

tSHZ

16 17

Qa2

18

19

WE

DQM

*Note :

∼

∼

∼

∼

∼

∼

∼

∼

Precharge

Power-down

Entry

Power-down

1. Both banks should be in idle state prior to entering precharge power down mode .

2. CKE should be set high at least 1CLK + tss prior to Row active command.

3. Can not violate minimum refresh specification. (32ms)

Precharge

Exit

Row Active

Active

Power-down

Entry

∼

∼

∼

∼

∼

∼

∼

∼

Active

Power-down

Exit

Read

Precharge

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

Self Refresh Entry & Exit Cycle

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

BA

A

10/AP

0

12

*Note 2

*Note 1

tSS

3

4

56

∼

∼

∼

∼

*Note 3

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

7

8

10

9

*Note 4

11

12 13

*Note 5

∼

∼

tRCmin

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

14

*Note 6

15

16 17

*Note 7

18

19

DQ

WE

DQM

Hi-Z

Self Refresh Entry

*Note : TO ENTER SELF REFRESH MODE

1. CS, RAS & CAS with CKE should be low at the same clcok cycle.

2. After 1 clock cycle, all the inputs including the system clock can be don't care except for CKE.

3. The device remains in self refresh mode as long as CKE stays "Low".
cf.) Once the device enters self refresh mode, minimum t

TO EXIT SELF REFRESH MODE

4. System colck restart and be stable before returning CKE high.
starts from high.

5. CS

6. Minimum t

7. 2K cycle of burst auto refresh is required before self refresh entry and after self refresh exi t if the system uses burst refresh.

RC is required after CKE going high to complete self refresh exit.

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

Hi-Z

Self Refresh Exit Auto Refresh

RAS is required before exit from self refresh.

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E

CMOS SDRAM

CLOCK

CKE

CS

RAS

CAS

ADDR

DQ

WE

Mode Register Set Cycle

0

12

Key Ra

*Note 2

*Note 1

*Note 3

3

HIGH

Hi-Z

4

56

Auto Refresh Cycle

0 1 2 3 4 5 6 7 8 9 10

7

8

10

9

11

12 13

HIGH

Hi-Z

14

tRC

15

16 17

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

∼

18

19

DQM

MRS Auto Refresh

* Both banks precharge should be completed before Mode Register Set cycle and auto refresh cycle.

MODE REGISTER SET CYCLE

*Note :

1. CS

2. Minimum 2 clock cycles should be met before new RAS

3. Please refer to Mode Register Set table.

New

Command

, RAS, CAS, & WE activation at the same clock cycle with address key will set internal mode register.

activation.

∼

∼

∼

∼

New Command

: Don't care

Rev 1.1 Jun '01

K4S161622D-TI/E CMOS SDRAM

PACKAGE DIMENSIONS

50-TSOP2-400CF

Unit : Millimeters

0~8°

0.25

#50

#26

TYP

(0.50)

0.10MAX

0.075MAX

[ ]

#1

(0.875)

0.30

+0.10

-0.05

20.95

± 0.10

0.35

+0.10

-0.05

#25

0.80TYP

[0.80±0.08]

11.76±0.20

0.05MIN

1.20MAX

1.00

± 0.10

± 0.10

10.16

0.125

+0.075

-0.035

(10.76)

(0.50)

± 0.20

11.76

Rev 1.2 Jan '03