SAMSUNG K4S161622D-TI Technical data

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K4S161622D-TI/E CMOS SDRAM

1M x 16 SDRAM

512K x 16bit x 2 Banks

Synchronous DRAM

LVTTL

Industrial/ExtendedTemperature

Revision 1.2

Jan 2003

Samsung Electronics reserves the right to change products or specification without notice.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

Revision History

Revision 1.0 (June 1999)

• Define Industrial Temperature spec of K4S161622D

Revision 1.1 (June 2001)

• Add Industrial Temperature Specification.

Revision 1.2 (Jan 2003)

• Changed VDD condition of High speed (over 166MHz) from 3.135V~ 3.6V to 3.0V ~ 3.0V.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

512K x 16Bit x 2 Banks Synchronous DRAM

GENERAL DESCRIPTIONFEATURES

• 3.3V power supply

• LVTTL compatible with multiplexed address

• Dual banks operation

• MRS cycle with address key programs

-. CAS Latency ( 2 & 3)

-. Burst Length (1, 2, 4, 8 & full page)

-. Burst Type (Sequential & Interleave)

• All inputs are sampled at the positive going edge of the system
clock

Burst Read Single-bit Write operation

•

•

DQM for masking
Auto & self refresh

•

• 15.6us refresh duty cycle (2K/32ms)

• Extended temperature range : -25°C to +85°C

• Industrial temperature range : -40°C to +85°C

FUNCTIONAL BLOCK DIAGRAM

The K4S161622D is 16,777,216 bits synchronous high data
rate Dynamic RAM organized as 2 x 524,288 words by 16 bits,
fabricated with SAMSUNG′s high performance CMOS technol­ogy. Synchronous design allows precise cycle control with the
use of system clock I/O transactions are possible on every clock
cycle. Range of operating frequencies, programmable burst
length and programmable latencies allow the same device to be
useful for a variety of high bandwidth, high performance mem­ory system applications.

ORDERING INFORMATION

Part NO. MAX Freq. Interface Package

K4S161622D-TI/E50 200MHz
K4S161622D-TI/E55 183MHz

K4S161622D-TI/E60 166MHz

K4S161622D-TI/E70 143MHz
K4S161622D-TI/E80 125MHz
K4S161622D-TI/E10 100MHz

K4S161622D-TI* : Industrial, Normal
K4S161622D-TE* : Extended, Normal

LVTTL

50

TSOP(II)

Data Input Register

Bank Select

Refresh Counter

Row Buffer

Address Register

CLK

ADD

LRAS

LCBR

LCKE

LRAS LCBR LWE LDQM

CLK CKE CS

* Samsung Electronics reserves the right to change products or specification without notice.

Row Decoder Col. Buffer

512K x 16

512K x 16

Column Decoder

Latency & Burst Length

Programming Register

LCAS LWCBR

Timing Register

RAS CAS WE L(U)DQM

Sense AMP

LWE

LDQM

Output BufferI/O Control

DQi

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

PIN CONFIGURATION (TOP VIEW)

VDD

LDQM

A10/AP

PIN FUNCTION DESCRIPTION

DQ0
DQ1

V

DQ2
DQ3

DDQ

V

DQ4
DQ5

V

DQ6
DQ7

DDQ

V

CAS
RAS

V

SSQ

SSQ

WE

CS
BA

A0
A1
A2
A3

DD

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VSS
DQ15
DQ14

SSQ

V
DQ13
DQ12

DDQ

V
DQ11
DQ10

SSQ

V
DQ9
DQ8

DDQ

V
N.C/RFU
UDQM
CLK
CKE
N.C
A9
A8
A7
A6
A5
A4

SS

V

50PIN TSOP (II)

(400mil x 825mil)

(0.8 mm PIN PITCH)

Pin Name Input Function

CLK System Clock Active on the positive going edge to sample all inputs.
CS

Chip Select

Disables or enables device operation by masking or enabling all inputs except
CLK, CKE and L(U)DQM

Masks system clock to freeze operation from the next clock cycle.

CKE Clock Enable

CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.

A

0 ~ A10/AP Address

BA Bank Select Address

RAS

CAS

WE

Row Address Strobe

Column Address Strobe

Write Enable

L(U)DQM Data Input/Output Mask

DQ

0 ~ 15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.

DD/VSS Power Supply/Ground Power and ground for the input buffers and the core logic.

V
V

DDQ/VSSQ Data Output Power/Ground

N.C/RFU

No Connection/
Reserved for Future Use

Row / column addresses are multiplexed on the same pins.
Row address : RA

0 ~ RA10, column address : CA0 ~ CA7

Selects bank to be activated during row address latch time.
Selects bank for read/write during column address latch time.

Latches row addresses on the positive going edge of the CLK with RAS
Enables row access & precharge.

Latches column addresses on the positive going edge of the CLK with CAS
Enables column access.

Enables write operation and row precharge.
Latches data in starting from CAS

Makes data output Hi-Z, t

SHZ after the clock and masks the output.

, WE active.

Blocks data input when L(U)DQM active.

Isolated power supply and ground for the output buffers to provide improved noise
immunity.

This pin is recommended to be left No Connection on the device.

low.

low.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Value Unit

Voltage on any pin relative to Vss V
Voltage on V

DD supply relative to Vss VDD, VDDQ -1.0 ~ 4.6 V

Storage temperature T
Power dissipation P
Short circuit current I

Note :

Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are exceeded.
Functional operation should be restricted to recommended operating condition.
Exposure to higher than recommended voltage for extended periods of time could affect device reliability.

DC OPERATING CONDITIONS

Recommended operating conditions (Voltage referenced to VSS = 0V, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)

Parameter Symbol Min Typ Max Unit Note

Supply voltage V
Input logic high votlage V
Input logic low voltage V
Output logic high voltage V
Output logic low voltage V
Input leakage current I

Note :

:

1. VIH (max) = 5.6V AC. The overshoot voltage duration is ≤ 3ns.

2. V

IL (min) = -2.0V AC. The undershoot voltage duration is ≤ 3ns.

3. Any input 0V ≤ V

IN ≤ VDDQ.

Input leakage currents include HI-Z output leakage for all bi-directional buffers with Tri-State outputs.

DD, VDDQ 3.0 3.3 3.6 V

IH 2.0 3.0 VDDQ+0.3 V 1

IL -0.3 0 0.8 V 2
OH 2.4 - - V IOH = -2mA
OL --0.4VIOL = 2mA
LI -10 - 10 uA 3

IN, VOUT -1.0 ~ 4.6 V

STG -55 ~ +150 °C

D 1W

OS 50 mA

CAPACITANCE (VDD = 3.3V, TA = 23°C, f = 1MHz, VREF =1.4V ± 200 mV)

Pin Symbol Min Max Unit

Clock C

RAS

, CAS, WE, CS, CKE, L(U)DQM CIN 24pF

Address C

0 ~ DQ15 COUT 35pF

DQ

CLK 24pF

ADD 24pF

DECOUPLING CAPACITANCE GUIDE LINE

Recommended decoupling capacitance added to power line at board.

Parameter Symbol Value Unit

Decoupling Capacitance between V
Decoupling Capacitance between V

Note :

1. VDD and VDDQ pins are separated each other.
All V

DD pins are connected in chip. All VDDQ pins are connected in chip.

2. V

SS and VSSQ pins are separated each other

All V

SS pins are connected in chip. All VSSQ pins are connected in chip.

DD and VSS CDC1 0.1 + 0.01 uF
DDQ and VSSQ CDC2 0.1 + 0.01 uF

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DC CHARACTERISTICS

(Recommended operating condition unless otherwise noted, Extended TA = -25 to +85°C , Industri a l TA = -40 to +85°C)

Parameter Symbol Test Condition

Operating Current
(One Bank Active)

Precharge Standby Current
in power-down mode

Precharge Standby Current
in non power-down mode

Active Standby Current
in power-down mode

Active Standby Current
in non power-down mode
(One Bank Active)

Operating Current
(Burst Mode)

CAS

Latency

Burst Length =1

I

CC1

I

CC2PCKE≤VIL(max), tCC = 15ns 2

I

CC2PS CKE & CLK≤VIL(max), tCC = ∞ 2

I

CC2N

t

RC≥tRC(min)

I

o = 0 mA

IH(min), CS≥VIH(min), tCC = 15ns

CKE≥V
Input signals are changed one time during

-50 -55 -60 -70 -80 -10

3 125 120 115 105 95 85
2 ---95 95 80

Version

30ns

IH(min), CLK≤VIL(max), tCC = ∞

CC2NS

I

I

CC3PCKE≤VIL(max), tCC = 15ns 3

I

CC3PS CKE & CLK≤VIL(max), tCC = ∞ 3

I

CC3N

CKE≥V
Input signals are stable

IH(min), CS≥VIH(min), tCC = 15ns

CKE≥V
Input signals are changed one time during
30ns

IH(min), CLK≤VIL(max), tCC = ∞

I

CC3NS

I

CC4

CKE≥V
Input signals are stable

Io = 0 mA
Page Burst 2Banks Activated
t

CCD = 2CLKs

3 160 155 150 140 130 115

2 ---115 115 100

Unit Note

mA 2

mA

15

mA

5

mA

25 mA

15 mA

mA 2

Refresh Current I

Self Refresh Current I

Note :

1. Unless otherwise notes, Input level is CMOS(VIH/VIL=VDDQ/VSSQ) in LVTTL.

CC5 tRC≥tRC(min)

CC6 CKE≤0.2V 1 mA

2. Measured with outputs open. Addresses are changed only one time during tcc(min).

3. Refresh period is 32ms. Addresses are changed only one time during tcc(min).

3 110 105 100 90 90 80

mA 3

2 ---90 90 80

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

AC OPERATING TEST CONDITIONS (VDD = 3.3V±0.3V

*2

, Extended TA = -25 to +85°C , Industrial TA = -40 to +85°C)

Parameter Value Unit

Input levels (Vih/Vil) 2.4 / 0.4 V
Input timing measurement reference level 1.4 V
Input rise and fall time tr / tf = 1 / 1 ns
Output timing measurement reference level 1.4 V
Output load condition See Fig. 2

3.3V

1200Ω

Output

870Ω

50pF

V
V

OL (DC) = 0.4V, IOL = 2mA

*2

Output

Z0=50Ω

OH (DC) = 2.4V, IOH = -2mA

(Fig. 2) AC Output Load Circuit (Fig. 1) DC Output Load Circuit

Note :

1. The DC/AC Test Output Load of K4S161622D-50/55/60/70 is 30pF.

Vtt=1.4V

50Ω

50pF

*1

OPERATING AC PARAMETER

(AC operating conditions unless otherwise noted)

Parameter Symbol

-50 -55 -60 -70 -80 -10

CAS Latency CL 323232323232CLK
CLK cycle time t

Row active to row active delay t
RAS

to CAS delay tRCD(min) 333332323222CLK 1

Row precharge time t
Row active time
Row cycle time

Last data in to row precharge t
Last data in to new col.address delay t
Last data in to burst stop t
Col. address to col. address delay t
Mode Register Set cycle time t

Number of valid output
data

Notes :

1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then

CAS Latency=3 2
CAS Latency=2 1

CC(min) 5105.5106107108101012ns

RRD(min)

RP(min) 333332323222CLK 1

t

RAS(min) 877775756554CLK 1
RAS(max) 100 us

t

RC(min)1110101010 7 10 7 9 7 7 6 CLK 1

t

RDL(min) 1 CLK 2, 5
CDL(min) 1CLK2

BDL(min) 1CLK2
CCD(min) 1CLK
MRS(min) 2CLK

rounding off to the next higher integer. Refer to the following clock unit based AC conversion table

Version

2

Unit Note

CLK 1

ea 4

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

Parameter

CLK cycle time t
Row active to row active delay t
RAS

to CAS delay tRCD(min) 15 16.5 18 20 20 20 ns
Row precharge time t
Row active time t

Row cycle time t

Symbol Version

-50 -55 -60 -70 -80 -10

CC(min) 55.56 7 8 10ns
RRD(min) 10 11 12 14 16 20 ns

RP(min) 15 16.5 18 20 20 20 ns
RAS(min) 40 38.5 42 49 48 48 ns
RAS(max) 100 us

t

RC(min)55556069 70 70ns

2. Minimum delay is required to complete write.

3. All parts allow every cycle column address change.

4. In case of row precharge interrupt, auto precharge and read burst stop.

5. Also, supported tRDL=2CLK for - 60 part which is distinguished by bucket code "J".
From the next generation, tRDL will be only 2CLK for every clock frequency.

AC CHARACTERISTICS (AC operating conditions unless otherwise noted)

Parameter Symbol

CLK cycle time

CAS Latency=3
CAS Latency=2 10 - - 10 10 12

CLK to valid
output delay

CAS Latency=3
CAS Latency=2 -6-6-6-6-6 -8

Output data t
CLK high pulse

width

CLK low pulse
width

Input setup time

CAS Latency=3
CAS Latency=2 3 3 3
CAS Latency=3
CAS Latency=2 3 3 3
CAS Latency=3

CAS Latency=2 2 2 2 2
Input hold time t
CLK to output in Low-Z t

CLK to output
in Hi-Z

CAS Latency=3

CAS Latency=2 -6-6-6-6- 6-8

t

CC

t

SAC

OH 2 - 2 - 2.5 - 2.5 - 2.5 - 2.5 - ns 2

t

CH

t

CL

t

SS

SH 1-1-1-1-1-1- ns3

SLZ 1-1-1-1-1-1-ns2

t

SHZ

-50 -55 -60 -70 -80 -10

Min Max Min Max Min Max Min Max Min Max Min Max

5

1000

5.5
1000

6

1000

7

1000

8

1000

10

-4.5-5-5.5-5.5-6-6

2

2

1.5

2

-

2

-

1.5

-

2.5

-

-

-

-3-3-3.5-ns3

2.5

-3-3-3.5-ns3

1.5

1.75

-

-2-2.5-ns3

-4.5- 5 -5.5-5.5 -6 - 6

Unit

Unit Note

1000 ns 1

ns 1, 2

ns

Note :

1. Parameters depend on programmed CAS latency.

2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter.

3. Assumed input rise and fall time (tr & tf)=1ns.
If tr & tf is longer than 1ns, transient time compensation should be considered,
i.e., [(tr + tf)/2-1]ns should be added to the parameter.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

SIMPLIFIED TRUTH TABLE

COMMAND

CKEn-1 CKEn CS RAS CAS WE DQM BA A10/AP A9~ A0 Note

Register Mode Register Set H X L L L L X OP CODE 1, 2

Refresh

Auto Refresh

Self
Refresh

Entry L 3

H

Exit L H

H

LL LHX X

LHHH

XX

3

3

HX XX 3
Bank Active & Row Addr. H X L L H H X V Row Address
Read &

Column Address

Write &
Column Address

Auto Precharge Disable

HXLHLHXV

Auto Precharge Enable H 4, 5
Auto Precharge Disable

HXLHLLXV

Auto Precharge Enable H 4, 5

Column

L

Address

0~A7)

(A

Column

L

Address

0~A7)

(A

4

4

Burst Stop H X L H H L X X 6

Precharge

Bank Selection

HXLLHLX

VL

X

Both Banks X H

Clock Suspend or
Active Power Down

Entry H L

HX XX

LVVV

X

X

Exit L H X X X X X

Entry H L

Precharge Power Down Mode

Exit L H

HX XX

LHHH

HX XX

X

X

X

LVVV
DQM H V X 7

No Operation Command H X

X

HX XX

XX

LHHH

(V=V alid, X=Don′t Care, H=Logic High, L=Logic Low)

Note :

1. OP Code : Operand Code
A

0 ~ A10/AP, BA : Program keys. (@MRS)

2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.

3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at both banks precharge state.

4. BA : Bank select address.
If "Low" at read, write, row active and precharge, bank A is selected.
If "High" at read, write, row active and precharge, bank B is selected.
If A

10/AP is "High" at row precharge, BA is ignored and both banks are selected.

5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the assoiated bank can be issued at t

RP after the end of burst.

6. Burst stop command is valid at every burst length.

7. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

MODE REGISTER FIELD TABLE TO PROGRAM MODES

Register Programmed with MRS

Address
Function

BA

RFU

A

10/AP

RFU

A9

W.B.L

A

8 A7

TM

A

6 A5 A4 A3 A2 A1 A0

CAS Latency BT Burst Length

Test Mode

A8 A7 A6 A5 A4 A3 A2 A1 A0 BT = 0

0

0

1

0

0

1

1

1

Write Burst Length

A9

0
1

Type

Mode Register Set

Reserved
Reserved
Reserved

Length

Burst

Single Bit

0
0
0
0
1
1
1
1

CAS Latency

0

0

1

0

0

1

1

1

0

0

1

0

0

1

1

1

Latency

Reserved

­2
3

Reserved
Reserved
Reserved
Reserved

Burst Type

Type

0

Sequential

1

Interleave

Full Page Length : x4 (1024), x8 (512), x16 (256)

0
0
0
0
1
1
1
1

Burst Length

0

0

0

1

1

0

1

1

0

0

0

1

1

0

1

1

Reserved
Reserved
Reserved
Full Page

POWER UP SEQUENCE

SDRAMs must be powered up and initialized in a predefined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM= "H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition for a minimum of 200us.

3. Issue precharge commands for all banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode register.
cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

1
2
4
8

BT = 1

1
2
4

8
Reserved
Reserved
Reserved
Reserved

Note : 1. If A9 is high during MRS cycle, "Burst Read Single Bit Write" function will be enabled.

2. RFU (Reserved for future use) should stay "0" during MRS cycle.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

BURST SEQUENCE (BURST LENGTH = 4)

Initial Address

A1 A0

0
0
1
1

0
1
0
1

0
1
2
3

BURST SEQUENCE (BURST LENGTH = 8)

Initial Address

A1 A0A2

0
0
0
0
1
1
1
1

0
0
1
1
0
0
1
1

0

0
1
0
1
0
1
0
1

1

1

2

2

3

3

4

4

5

5

6

6

7

7

0

Sequential Interleave

1
2
3
0

Sequential Interleave

2

3

3

4

4

5

5

6

6

7

7

0

0

1

1

2

2
3
0
1

4

5

5

6

6

7

7

0

0

1

1

2

2

3

3

4

3
0
1
2

6

7

7

0

0

1

1

2

2

3

3

4

4

5

5

6

0
1
2
3

1

0
1
2
3
4
5
6
7

2

0

3

3

0

2

1

5

6

4

7

7

4

6

5

1
0
3
2

3
2
1
0
7
6
5
4

2
3
0
1

5

4

4

5

7

6

6

7

1

0

0

1

3

2

2

3

3
2
1
0

7

6

6

7

5

4

4

5

3

2

2

3

1

0

0

1

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DEVICE OPERATIONS

CLOCK (CLK)

The clock input is used as the reference for all SDRAM opera­tions. All operations are synchronized to the positive going edge
of the clock. The clock transitions must be monotonic between
V

IL and VIH. During operation with CKE high all inputs are

assumed to be in a valid state (low or high) for the duration of
set-up and hold time around positive edge of the clock in order
to function well Q perform and I

CC specifications.

CLOCK ENABLE (CKE)

The clock enable(CKE) gates the clock onto SDRAM. If CKE
goes low synchronously with clock (set-up and hold time are the
same as other inputs), the internal clock is suspended from the
next clock cycle and the state of output and burst address is fro­zen as long as the CKE remains low. All other input s are ignore d
from the next clock cycle after CKE goes low. When all banks
are in the idle state and CKE goes low synchronously with clock,
the SDRAM enters the power down mode from the next clock
cycle. The SDRAM remains in the power down mode ignoring
the other inputs as long as CKE remains low. The power down
exit is synchronous as the internal clock is suspended. When
CKE goes high at least "1CLK + t
of the clock, then the SDRAM becomes active from the same
clock edge accepting all the input commands.

SS" before the high going edge

ADDRESS INPUTS (A0 ~ A10/AP)

: In case x 4

The 21 address bits are required to decode the 2,097,152 word
locations are multiplexed into 11 address input pins (A
AP).

The 11 bit row addresses are latched along with RAS and

BA during bank activate command. The 10 bit column
addresses are latched along with CAS
or write command.

, WE and BA during read

: In case x 8

The 20 address bits are required to decode the 1,048,576 word
locations are multiplexed into 11 address input pins (A
AP). The 11 bit row addresses are latched along with RAS
BA during bank activate command. The 9 bit column addresses
are latched along with CAS
command.

, WE and BA during read or write

: In case x 16

The 19 address bits are required to decode the 524,288 word
locations are multiplexed into 11 address input pins (A
AP). The 11 bit row addresses are latched along with RAS
BA during bank activate command. The 8 bit column addresses
are latched along with CAS
command.

, WE and BA during read or write

0 ~ A10/

0 ~ A10/

and

0 ~ A10/

and

BANK ADDRESS (BA)

: In case x 4

This SDRAM is organized as two independent banks of
2,097,152 words x 4 bits memory arrays. The BA input is latched
at the time of assertion of RAS
used for the operation. The bank select BA is latched at bank
active, read, write, mode register set and precharge operations.

: In case x 8

This SDRAM is organized as two independent banks of
1,048,576 words x 8 bits memory arrays. The BA input is latched
at the time of assertion of RAS
used for the operation. The bank select BA
active, read, write, mode register set and precharge operations.

: In case x 16

This SDRAM is organized as two independent banks of 524,288
words x 16 bits memory arrays. The BA input is latched at the
time of assertion of RAS
for the operation. The bank select BA is latched at bank active,
read, write, mode register set and precharge operations.

and CAS to select the bank to be

and CAS to select the bank to be

is latched at bank

and CAS to select the bank to be used

NOP and DEVICE DESELECT

When RAS, CAS and WE are high, the SDRAM performs no
operation (NOP). NOP does not initiate any new operation, but
is needed to complete operations which require more than sin­gle clock cycle like bank activate, burst read, auto refresh, etc.
The device deselect is also a NOP and is entered by asserting
CS

high. CS high disables the command decoder so that RAS,

CAS

, WE and all the address inputs are ignored.

POWER-UP

SDRAMs must be powered up and initialized in a pre­defined manner to prevent undefined operations.

1. Apply power and start clock. Must maintain CKE= "H", DQM=
"H" and the other pins are NOP condition at the inputs.

2. Maintain stable power, stable clock and NOP input condition
for a minimum of 200us.

3. Issue precharge commands for both banks of the devices.

4. Issue 2 or more auto-refresh commands.

5. Issue a mode register set command to initialize the mode reg­ ister.

cf.) Sequence of 4 & 5 is regardless of the order.

The device is now ready for normal operation.

Rev 1.2 Jan '03

K4S161622D-TI/E CMOS SDRAM

DEVICE OPERATIONS (Continued)

MODE REGISTER SET (MRS)

The mode register stores the data for controlling the various
operating modes of SDRAM. It programs the CAS latency, burst
type, burst length, test mode and various vendor specific options
to make SDRAM useful for variety of different applications. The
default value of the mode register is not defined, therefore the
mode register must be written after power up to operate the
SDRAM. The mode register is written by asserting low on CS
RAS

, CAS and WE (The SDRAM should be in active mode with
CKE already high prior to writing the mode register). The state of
address pins A

, CAS and WE going low is the data written in the mode

RAS

0 ~ A10/AP and BA in the same cycle as CS,

register. Two clock cycles is required to complete the write in the
mode register. The mode register contents can be changed
using the same command and clock cycle requirements during
operation as long as all banks are in the idle state. The mode
register is divided into various fields depending on the fields of
functions. The burst length field uses A

3, CAS latency (read latency from column address) uses A4 ~

A

6, vendor specific options or test mode use A7 ~ A8, A10/AP

A
and BA. The write burst length is programmed using A

10/AP, BA must be set to low for normal SDRAM operation.

A

0 ~ A2, burst type uses

9. A7 ~ A8,

Refer to the table for specific codes for various burst length,
burst type and CAS latencies.

BANK ACTIVATE

The bank activate command is used to select a random row in
an idle bank. By asserting low on RAS
and bank address, a row access is initiated. The read or write
operation can occur after a time delay of t

RCD

of bank activation. t

is an internal timing parameter of
SDRAM, therefore it is dependent on operating clock frequency.
The minimum number of clock cycles required between bank
activate and read or write command should be calculated by
dividing t

RCD(min) with cycle time of the clock and then rounding

off the result to the next higher integer. The SDRAM has two
internal banks in the same chip and shares part of the internal
circuitry to reduce chip area, therefore it restricts the activation
of two banks simultaneously. Also the noise generated during
sensing of each bank of SDRAM is high, requiring some time for
power supplies to recover before the other bank can be sensed
reliably. t

RRD(min) specifies the minimum time required between

activating different bank. The number of clock cycles required
between different bank activation must be calculated similar to

RCD specification. The minimum time required for the bank to be

t

and CS with desired row

RCD(min) from the time

active to initiate sensing and restoring the complete row of
dynamic cells is determined by t
activate command must satisfy t

RAS(min). Every SDRAM bank

RAS(min) specification before a

precharge command to that active bank can be asserted. The
maximum time any bank can be in the active state is determined
by t

RAS(max). The number of cycles for both tRAS(min) and

RAS(max) can be calculated similar to tRCD specification.

t

,

BURST READ

The burst read command is used to access burst of data on con­secutive clock cycles from an active row in an active bank. The
burst read command is issued by asserting low on CS
with WE being high on the positive edge of the clock. The bank
must be active for at least t

RCD(min) before the burst read com-

mand is issued. The first output appears in CAS latency number
of clock cycles after the issue of burst read command. The burst
length, burst sequence and latency from the burst read com­mand is determined by the mode register which is already pro­grammed. The burst read can be initiated on any column
address of the active row. The address wrap s around if the initial
address does not start from a boundary such that number of out­puts from each I/O are equal to the burst length programmed in
the mode register. The output goes into high-impedance at the
end of the burst, unless a new burst read was initiated to keep
the data output gapless. The burst read can be terminated by
issuing another burst read or burst write in the same bank or the
other active bank or a precharge command to the same bank.
The burst stop command is valid at every page burst length.

BURST WRITE

The burst write command is similar to burst read command and
is used to write data into the SDRAM on consecutive clock
cycles in adjacent addresses depending on burst length and
burst sequence. By asserting low on CS
column address, a write burst is initiated. The data inputs are
provided for the initial address in the same clock cycle as the
burst write command. The input buffer is deselected at the end
of the burst length, even though the internal writing can be com­pleted yet. The writing can be completed by issuing a burst read
and DQM for blocking data inputs or burst write in the same or
another active bank. The burst stop command is valid at every
burst length. The write burst can also be terminated by using
DQM for blocking data and procreating the bank t
last data input to be written into the active row. See DQM
OPERA T ION also.

, CAS and WE with valid

and CAS

RDL after the

Rev 1.2 Jan '03