Samsung K4F640412D-TC-L, K4F640412D-JC-L, K4F660412D-TC-L, K4F660412D-JC-L Datasheet
CMOS DRAMK4F660412D,K4F640412D
This is a family of 16,777,216 x 4 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory
cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Normal or Low power)
are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden refresh capabilities.
Furthermore, Self-refresh operation is available in L-version. This 16Mx4 Fast Page Mode DRAM family is fabricated using Samsung′s
advanced CMOS process to realize high band-width, low power consumption and high reliability.
• Fast Page Mode operation
• CAS -before-RAS refresh capability
• RAS -only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• +3.3V±0.3V power supply
Control
Clocks
RAS
CAS
W
Vcc
Vss
A0~A12
(A0~A11)*1
A0~A10
(A0~A11)*1
Memory Array
16,777,216 x 4
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
16M x 4bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FUNCTIONAL BLOCK DIAGRAM
Note) *1 : 4K Refresh
• Refresh Cycles
Part
NO.
Refresh
cycle
Refresh time
Normal L-ver
K4F660412D* 8K
64ms 128ms
K4F640412D 4K
• Performance Range
Speed
tRAC tCAC tRC tPC
-45 45ns 12ns 80ns 31ns
-50 50ns 13ns 90ns 35ns
-60 60ns 15ns 110ns 40ns
• Active Power Dissipation
Speed 8K 4K
-45 324 432
-50 288 396
-60 252 360
Unit : mW
Sense Amps & I/O
Data out
Buffer
DQ0
to
DQ3
Data in
Buffer
* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)
CAS-before-RAS & Hidden refresh mode
: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)
Row Decoder
Column Decoder
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
OE
• Part Identification
- K4F660412D-JC/L(3.3V, 8K Ref., SOJ)
- K4F640412D-JC/L(3.3V, 4K Ref., SOJ)
- K4F660412D-TC/L(3.3V, 8K Ref., TSOP)
- K4F640412D-TC/L(3.3V, 4K Ref., TSOP)
FEATURES
CMOS DRAMK4F660412D,K4F640412D
VCC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
VCC
VSS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
PIN CONFIGURATION (Top Views)
* (N.C) : N.C for 4K Refresh product
Pin Name Pin Function
A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 3 Data In/Out
VSS Ground
RAS Row Address Strobe
CAS Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC Power(+3.3V)
N.C No Connection
VCC
DQ0
DQ1
N.C
N.C
N.C
N.C
W
RAS
A0
A1
A2
A3
A4
A5
VCC
VSS
DQ3
DQ2
N.C
N.C
N.C
CAS
OE
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
(T : 400mil TSOP(II))(J : 400mil SOJ)
• K4F660412D-J
• K4F640412D-J
• K4F660412D-T
• K4F640412D-T
CMOS DRAMK4F660412D,K4F640412D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to
the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Parameter Symbol Rating Units
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS Address 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
*1 : Vcc+1.3V at pulse width≤15ns which is measured at VCC
*2 : -1.3 at pulse width≤15ns which is measured at VSS
Parameter Symbol Min Typ Max Units
Supply Voltage VCC 3.0 3.3 3.6 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.0 -
Vcc+0.3
*1
V
Input Low Voltage VIL
-0.3
*2
- 0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Parameter Symbol Min Max Units
Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,
all other pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V
CMOS DRAMK4F660412D,K4F640412D
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and CAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=CAS-before-RAS cycling or 0.2V,
W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=CAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ3=VCC-0.2V, 0.2V or Open
Symbol Power Speed
Max
Units
K4F660412D K4F640412D
ICC1 Don′t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
ICC2
Normal
L
Don′t care
1
1
1
1
mA
mA
ICC3 Don′t care
-45
-50
-60
90
80
70
120
110
100
mA
mA
mA
ICC4 Don′t care
-45
-50
-60
70
60
50
70
60
50
mA
mA
mA
ICC5
Normal
L
Don′t care
0.5
200
0.5
200
mA
uA
ICC6 Don′t care
-45
-50
-60
120
110
100
120
110
100
mA
mA
mA
ICC7 L Don′t care 350 350 uA
ICCS L Don′t care 350 350 uA
CMOS DRAMK4F660412D,K4F640412D
CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A12] CIN1 - 5 pF
Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ3] CDQ - 7 pF
Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
Parameter Symbol
-45 -50 -60
Units Note
Min Max Min Max Min Max
Random read or write cycle time
tRC
80 90 110
ns
Read-modify-write cycle time
tRWC
115 133 153 ns
Access time from RAS
tRAC
45 50 60 ns 3,4,10
Access time from CAS
tCAC
12 13 15 ns 3,4,5
Access time from column address
tAA
23 25 30 ns 3,10
CAS to output in Low-Z
tCLZ
0 0 0 ns 3
Output buffer turn-off delay
tOFF
0 13 0 13 0 13 ns 6
Transition time (rise and fall)
tT
1 50 1 50 1 50 ns 2
RAS precharge time
tRP
25 30 40 ns
RAS pulse width
tRAS
45 10K 50 10K 60 10K ns
RAS hold time
tRSH
12 13 15 ns
CAS hold time
tCSH
45 50 60 ns
CAS pulse width
tCAS
12 10K 13 10K 15 10K ns
RAS to CAS delay time
tRCD
18 33 20 37 20 45 ns 4
RAS to column address delay time
tRAD
13 22 15 25 15 30 ns 10
CAS to RAS precharge time
tCRP
5 5 5 ns
Row address set-up time
tASR
0 0 0 ns
Row address hold time
tRAH
8 10 10 ns
Column address set-up time
tASC
0 0 0 ns
Column address hold time
tCAH
8 10 10 ns
Column address to RAS lead time
tRAL
23 25 30 ns
Read command set-up time
tRCS
0 0 0 ns
Read command hold time referenced to CAS
tRCH
0 0 0 ns 8
Read command hold time referenced to RAS
tRRH
0 0 0 ns 8
Write command hold time
tWCH
8 10 10 ns
Write command pulse width
tWP
8 10 10 ns
Write command to RAS lead time
tRWL
13 15 15 ns
Write command to CAS lead time
tCWL
12 13 15 ns
Data set-up time
tDS
0 0 0 ns 9
Data hold time
tDH
10 10 10 ns 9
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)
CMOS DRAMK4F660412D,K4F640412D
AC CHARACTERISTICS (Continued)
Parameter Symbol
-45 -50 -60
Units Note
Min Max Min Max Min Max
Refresh period (Normal)
tREF
64 64 64 ms
Refresh period (L-ver)
tREF
128 128 128 ms
Write command set-up time
tWCS
0 0 0 ns 7
CAS to W delay time
tCWD
32 36 38 ns 7
RAS to W delay time
tRWD
67 73 83 ns 7
Column address to W delay time
tAWD
43 48 53 ns 7
CAS precharge W delay time
tCPWD
48 53 60 ns
CAS set-up time (CAS -before-RAS refresh)
tCSR
5 5 5 ns
CAS hold time (CAS -before-RAS refresh)
tCHR
10 10 10 ns
RAS to CAS precharge time
tRPC
5 5 5 ns
Access time from CAS precharge
tCPA
26 30 35 ns 3
Fast Page mode cycle time
tPC
31 35 40 ns
Fast Page mode read-modify-write cycle time
tPRWC
70 76 85 ns
CAS precharge time (Fast page cycle)
tCP
9 10 10 ns
RAS pulse width (Fast page cycle)
tRASP
45 200K 50 200K 60 200K ns
RAS hold time from CAS precharge
tRHCP
28 30 35 ns
OE access time
tOEA
12 13 15 ns 3
OE to data delay
tOED
12 13 13 ns
Output buffer turn off delay time from OE
tOEZ
0 13 0 13 0 13 ns 6
OE command hold time
tOEH
12 13 15 ns
Write command set-up time (Test mode in)
tWTS
10 10 10 ns 11
Write command hold time (Test mode in)
tWTH
15 15 15 ns 11
W to RAS precharge time (C-B-R refresh)
tWRP
10 10 10 ns
W to RAS hold time (C-B-R refresh)
tWRH
10 10 10 ns
RAS pulse width (C-B-R self refresh)
tRASS
100 100 100 us 13,14,15
RAS precharge time (C-B-R self refresh)
tRPS
80 90 110 ns 13,14,15
CAS hold time (C-B-R self refresh)
tCHS
-50 -50 -50 ns 13,14,15
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