Samsung K4F171612D-T, K4F171612D-J, K4F171611D-T, K4F171611D-J, K4F151612D-J Datasheet

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K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
This is a family of 1,048,576 x 16 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (1K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CAS­before-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 1Mx16 Fast Page Mode DRAM family is fabricated using Samsungs advanced CMOS process to realize high band-width, low power consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
- K4F171611D-J(T) (5V, 4K Ref.)
- K4F151611D-J(T) (5V, 1K Ref.)
- K4F171612D-J(T) (3.3V, 4K Ref.)
- K4F151612D-J(T) (3.3V, 1K Ref.)
• Fast Page Mode operation
• 2 CAS Byte/Word Read/Write operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in 42-pin SOJ 400mil and 50(44)-pin TSOP(II) 400mil packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
Control Clocks
VBB Generator
Refresh Timer
Refresh Control
Refresh Counter
Row Address Buffer
Col. Address Buffer
Row Decoder
Column Decoder
Lower
Data out
Buffer
RAS
UCAS
LCAS
W
Vcc Vss
DQ0
to
DQ7
A0-A11
(A0 - A9)*1
A0 - A7
(A0 - A9)*1
Memory Array
1,048,576 x16
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to change products and specifications without notice.
1M x 16Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
Refresh Cycles Part
NO.
VCC
Refresh
cycle
Refresh period
Normal L-ver
K4F171611D 5V
4K 64ms
128ms
K4F171612D 3.3V K4F151611D 5V
1K 16ms
K4F151612D 3.3V
Perfomance Range
Speed
tRAC tCAC tRC tPC
Remark
-50 50ns 15ns 90ns 35ns 5V/3.3V
-60 60ns 15ns 110ns 40ns 5V/3.3V
Active Power Dissipation
Speed
3.3V 5V
4K 1K 4K 1K
-50 324 504 495 770
-60 288 468 440 715
Unit : mW
Sense Amps & I/O
Upper
Data in
Buffer
Upper
Data out
Buffer
Lower
Data in
Buffer
DQ8
to
DQ15
OE
Note) *1 : 1K Refresh
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
VCC DQ0 DQ1 DQ2 DQ3
VCC DQ4 DQ5 DQ6 DQ7
N.C
N.C N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0 A1 A2 A3
VCC
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C
N.C LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
1 2 3 4 5 6 7 8 9 10 11
12 13 14 15 16 17 18 19 20 21 22
44 43 42 41 40 39 38 37 36 35 34
33 32 31 30 29 28 27 26 25 24 23
PIN CONFIGURATION (Top Views)
Pin Name Pin Function
A0 - A11 Address Inputs (4K Product)
A0 - A9 Address Inputs (1K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC
Power(+5V) Power(+3.3V)
N.C No Connection
VCC DQ0 DQ1 DQ2 DQ3
VCC DQ4 DQ5 DQ6 DQ7
N.C N.C
W
RAS
*A11(N.C)
*A10(N.C)
A0 A1 A2 A3
VCC
VSS DQ15 DQ14 DQ13 DQ12 VSS DQ11 DQ10 DQ9 DQ8 N.C LCAS UCAS OE A9 A8 A7 A6 A5 A4 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21
42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22
*A10 and A11 are N.C for K4F151611(2)D(5V/3.3V, 1K Ref. product) J : 400mil 42 SOJ
T : 400mil 50(44) TSOP II
• K4F17(5)1611(2)D-J
• K4F17(5)1611(2)D-T
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Parameter Symbol
Rating
Units
3.3V 5V
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V Storage Temperature Tstg -55 to +150 -55 to +150 °C Power Dissipation PD 1 1 W Short Circuit Output Current IOS Address 50 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC *2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
Parameter Symbol
3.3V 5V Units
Min Typ Max Min Typ Max
Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V Ground VSS 0 0 0 0 0 0 V Input High Voltage VIH 2.0 -
VCC+0.3
*1
2.4 -
VCC+1.0
*1
V
Input Low Voltage VIL
-0.3
*2
- 0.8
-1.0
*2
- 0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Symbol Min Max Units
3.3V
Input Leakage Current (Any input 0≤VIN≤VIN+0.3V, all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 - V Output Low Voltage Level(IOL=2mA) VOL - 0.4 V
5V
Input Leakage Current (Any input 0≤VIN≤VIN+0.5V, all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current (Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-5mA) VOH 2.4 - V Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open. ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4, address can be changed maximum once within one fast page mode cycle time, tPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and UCAS, LCAS cycling @tRC=min.) ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH) ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS cycling @tRC=min.) ICC4* : Fast Page Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tPC=min.) ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V) ICC6* : CAS-Before-RAS Refresh Current (RAS, UCAS or LCAS cycling @tRC=min.) ICC7 : Battery back-up current, Average power supply current, Battery back-up mode Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=0.2V, DQ=Dont care, TRC=31.25us(4K/L-ver), 125us(1K/L-ver), TRAS=TRASmin~300ns ICCS : Self Refresh Current RAS=UCAS=LCAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open
Symbol Power Speed
Max
Units
K4F171612D K4F151612D K4F171611D K4F151611D
ICC1 Dont care
-50
-60
90 80
140 130
90 80
140 130
mA mA
ICC2
Normal
L
Dont care
1 1
1 1
2 1
2 1
mA mA
ICC3 Dont care
-50
-60
90 80
140 130
90 80
140 130
mA mA
ICC4 Dont care
-50
-60
90 80
90 80
90 80
90 80
mA mA
ICC5
Normal
L
Dont care
0.5
200
0.5
200
1
200
1
200
mA
uA
ICC6 Dont care
-50
-60
90 80
140 130
90 80
140 130
mA
mA ICC7 L Dont care 300 200 350 250 uA ICCS L Dont care 150 150 200 200 uA
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A11] CIN1 - 5 pF Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF Output capacitance [DQ0 - DQ15] CDQ - 7 pF
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter Symbol
-50 -60 Units Notes
Min Max Min Max
Random read or write cycle time
tRC
90 110 ns
Read-modify-write cycle time
tRWC
133 155 ns
Access time from RAS
tRAC
50 60 ns 3,4,10
Access time from CAS
tCAC
15 15 ns 3,4,5
Access time from column address
tAA
25 30 ns 3,10
CAS to output in Low-Z
tCLZ
0 0 ns 3
Output buffer turn-off delay
tOFF
0 13 0 15 ns 6
Transition time (rise and fall)
tT
3 50 3 50 ns 2
RAS precharge time
tRP
30 40 ns
RAS pulse width
tRAS
50 10K 60 10K ns
RAS hold time
tRSH
13 15 ns
CAS hold time
tCSH
50 60 ns
CAS pulse width
tCAS
13 10K 15 10K ns
RAS to CAS delay time
tRCD
20 37 20 45 ns 4
RAS to column address delay time
tRAD
15 25 15 30 ns 10
CAS to RAS precharge time
tCRP
5 5 ns
Row address set-up time
tASR
0 0 ns
Row address hold time
tRAH
10 10 ns
Column address set-up time
tASC
0 0 ns 11
Column address hold time
tCAH
10 10 ns 11
Column address to RAS lead time
tRAL
25 30 ns
Read command set-up time
tRCS
0 0 ns
Read command hold time referenced to CAS
tRCH
0 0 ns 8
Read command hold time referenced to RAS
tRRH
0 0 ns 8
Write command hold time
tWCH
10 10 ns
Write command pulse width
tWP
10 10 ns
Write command to RAS lead time
tRWL
13 15 ns
Write command to CAS lead time
tCWL
13 15 ns
AC CHARACTERISTICS (0°CTA70°C, See note 1,2)
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
AC CHARACTERISTICS (Continued)
Parameter Symbol
-50 -60 Units Notes
Min Max Min Max
Data set-up time
tDS
0 0 ns 9,17
Data hold time
tDH
10 10 ns 9,17
Refresh period (1K, Normal)
tREF
16 16 ms
Refresh period (4K, Normal)
tREF
64 64 ms
Refresh period (L-ver)
tREF
128 128 ms
Write command set-up time
tWCS
0 0 ns 7
CAS to W delay time
tCWD
36 40 ns 7,13
RAS to W delay time
tRWD
73 85 ns 7
Column address to W delay time
tAWD
48 55 ns 7
CAS precharge to W delay time
tCPWD
53 60 ns 7
CAS set-up time (CAS-before-RAS refresh)
tCSR
5 5 ns 15
CAS hold time (CAS-before-RAS refresh)
tCHR
10 10 ns 16
RAS to CAS precharge time
tRPC
5 5 ns
Access time from CAS precharge
tCPA
30 35 ns 3
Fast Page mode cycle time
tPC
35 40 ns
Fast Page read-modify-write cycle time
tPRWC
76 80 ns
CAS precharge time (Fast Page cycle)
tCP
10 10 ns 12
RAS pulse width (Fast Page cycle)
tRASP
50 200K 60 200K ns
RAS hold time from CAS precharge
tRHCP
30 35 ns
OE access time
tOEA
13 15 ns 3
OE to data delay
tOED
13 15 ns
Output buffer turn off delay time from OE
tOEZ
0 13 0 15 ns
OE command hold time
tOEH
13 15 ns
RAS pulse width (C-B-R self refresh)
tRASS
100 100 us 18,19,20
RAS precharge time (C-B-R self refresh)
tRPS
90 110 ns 18,19,20
CAS hold time (C-B-R self refresh)
tCHS
-50 -50 ns 18,19,20
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
NOTES
An initial pause of 200us is required after power-up followed by any 8 RAS-only refresh or CAS-before-RAS refresh cycles before proper device operation is achieved. Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition times are measured between VIH(min) and VIL(max) and are assumed to be 5ns for all inputs. Measured with a load equivalent to 2 TTL(5V)/1TTL(3.3V) loads and 100pF. Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.
If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC. Assumes that tRCDtRCD(max). This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.
tWCS, tRWD, tCWD, tAWD and tCPWD are non restrictive operating parameters. They are included in the data sheet as electrical
characteristics only. If tWCStWCS(min), the cycle is an early write cycle and the data output will remain high impedance for the duration of the cycle. If tCWDtCWD(min), tRWDtRWD(min), tAWDtAWD(min) and tCPWDtCPWD(min), then the cycle is a read­modify-write cycle and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the condition of the data out is indeterminate. Either tRCH or tRRH must be satisfied for a read cycle. These parameters are referenced to CAS falling edge in early write cycles and to W falling edge in OE controlled write cycle
and read-modify-write cycles. Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA. tASC, tCAH are referenced to the earlier CAS falling edge. tCP is specified from the later CAS rising edge in the previous cycle to the earlier CAS falling edge in the next cycle.
K4F17(5)1611(2)D Truth Table
RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE
H X X X X Hi-Z Hi-Z Standby
L H H X X Hi-Z Hi-Z Refresh L L H H L DQ-OUT Hi-Z Byte Read L H L H L Hi-Z DQ-OUT Byte Read L L L H L DQ-OUT DQ-OUT Word Read L L H L H DQ-IN - Byte Write L H L L H - DQ-IN Byte Write L L L L H DQ-IN DQ-IN Word Write L L L H H Hi-Z Hi-Z -
6.
5.
10.
8.
3.
2.
1.
4.
11.
12.
7.
9.
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.
tCWL is specified from W falling edge to the earlier CAS rising edge. tCSR is referenced to the earlier CAS falling edge before RAS transition low.
tCHR is referenced to the later CAS rising edge after RAS transition low.
tCSR tCHR
RAS
LCAS
UCAS
16.
15.
14.
13.
tDS, tDH is independently specified for lower byte DQ(0-7), upper byte DQ(8-15)
If tRASS100us, then RAS precharge time must use tRPS instead of tRP. For RAS-only refresh and burst CAS-before-RAS refresh mode, 4096(4K)/1024(1K) cycles of burst refresh must be executed within 64ms/16ms before and after self refresh, in order to meet refresh specification. For distributed CAS-before-RAS with 15.6us interval CAS-before-RAS refresh should be executed with in 15.6us immediately before and after self refresh in order to meet refresh specification.
17.
18.
19.
20.
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
RAS
VIH - VIL -
UCAS
VIH - VIL -
A
VIH - VIL -
W
VIH - VIL -
OE
VIH - VIL -
VOH - VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tASR tRAH
tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
tOFF
tRCH
Dont care
Undefined
LCAS
VIH - VIL -
tCRP
tCSH
tRSHtRCD
tCAS
tRAD
tCRP
tRRH
VOH - VOL -
DQ8 ~ DQ15
tCAC
tCLZ
tRAC
OPEN
DATA-OUT
DATA-OUT
tOFF
tOEZ
tOEZ
tRCS
WORD READ CYCLE
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
tCRP
NOTE : DIN = OPEN
LOWER BYTE READ CYCLE
RAS
VIH - VIL -
LCAS
VIH - VIL -
A
VIH - VIL -
W
VIH - VIL -
OE
VIH - VIL -
VOH - VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tRP
tCSH
tRSHtRCD
tCAS
tRAL
tRAD
tASR tRAH
tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN DATA-OUT
tOEZ
tOFF
tRCH
Dont care
Undefined
tRPC
UCAS
VIH - VIL -
OPEN
VOH - VOL -
DQ8 ~ DQ15
tRCS
tRRH
K4F171611D, K4F151611D
CMOS DRAMK4F171612D, K4F151612D
NOTE : DIN = OPEN
UPPER BYTE READ CYCLE
RAS
VIH - VIL -
LCAS
VIH - VIL -
A
VIH - VIL -
W
VIH - VIL -
OE
VIH - VIL -
VOH - VOL -
DQ0 ~ DQ7
COLUMN
ADDRESS
ROW
ADDRESS
tRAS
tRC
tCRP
tRP
tCSH
tRSHtRCD tCAS
tRAL
tRAD
tASR tRAH tASC
tCAH
tCRP
tAA
tOEA
tCAC
tCLZ
tRAC
OPEN
DATA-OUT
tOEZ
tOFF
tRRH
tRCH
Dont care
Undefined
UCAS
VIH - VIL -
OPEN
VOH - VOL -
DQ8 ~ DQ15
tCRP
tRPC
tRCS
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