Samsung K4F170812D-F, K4F170811D-B, K4F160811D-F, K4F160811D-B, K4F170812D-B Datasheet
...
K4F170811D, K4F160811D
CMOS DRAMK4F170812D, K4F160812D
This is a family of 2,097,152 x 8 bit Fast Page Mode CMOS DRAMs. Fast Page Mode offers high speed random access of memory cells
within the same row. Power supply voltage (+5.0V or +3.3V), refresh cycle (2K Ref. or 4K Ref.), access time (-50 or -60), power consumption(Normal or Low power) and package type(SOJ or TSOP-II) are optional features of this family. All of this family have CASbefore-RAS refresh, RAS-only refresh and Hidden refresh capabilities. Furthermore, Self-refresh operation is available in L-version.
This 2Mx8 Fast Page Mode DRAM family is fabricated using Samsung′s advanced CMOS process to realize high band-width, low power
consumption and high reliability. It may be used as graphic memory unit for microcomputer, personal computer and portable machines.
• Part Identification
- K4F170811D-B(F) (5V, 4K Ref.)
- K4F160811D-B(F) (5V, 2K Ref.)
- K4F170812D-B(F) (3.3V, 4K Ref.)
- K4F160812D-B(F) (3.3V, 2K Ref.)
• Fast Page Mode operation
• CAS-before-RAS refresh capability
• RAS-only and Hidden refresh capability
• Self-refresh capability (L-ver only)
• Fast parallel test mode capability
• TTL(5V)/LVTTL(3.3V) compatible inputs and outputs
• Early Write or output enable controlled write
• JEDEC Standard pinout
• Available in Plastic SOJ and TSOP(II) packages
• Single +5V±10% power supply (5V product)
• Single +3.3V±0.3V power supply (3.3V product)
Control
Clocks
RAS
CAS
W
Vcc
Vss
DQ0
to
DQ7
A0-A11
(A0 - A10)*1
A0 - A8
(A0 - A9)*1
Memory Array
2,097,152 x 8
Cells
SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.
2M x 8Bit CMOS Dynamic RAM with Fast Page Mode
DESCRIPTION
FEATURES
FUNCTIONAL BLOCK DIAGRAM
• Refresh Cycles
Part
NO.
VCC
Refresh
cycle
Refresh period
Normal L-ver
K4F170811D 5V
4K 64ms
128ms
K4F170812D 3.3V
K4F160811D 5V
2K 32ms
K4F160812D 3.3V
• Performance Range
Speed
tRAC tCAC tRC tPC
Remark
-50 50ns 13ns 90ns 35ns 5V/3.3V
-60 60ns 15ns 110ns 40ns 5V/3.3V
• Active Power Dissipation
Speed
3.3V 5V
4K 2K 4K 2K
-50 324 396 495 605
-60 288 360 440 550
Unit : mW
Sense Amps & I/O
Data out
Buffer
Data in
Buffer
OE
Note) *1 : 2K Refresh
Col. Address Buffer
Row Address Buffer
Refresh Counter
Refresh Control
Refresh Timer
Column Decoder
Row Decoder
VBB Generator
K4F170811D, K4F160811D
CMOS DRAMK4F170812D, K4F160812D
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
VCC
VSS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
PIN CONFIGURATION (Top Views)
Pin Name Pin Function
A0 - A11 Address Inputs (4K Product)
A0 - A10 Address Inputs (2K Product)
DQ0 - 7 Data In/Out
VSS Ground
RAS Row Address Strobe
CAS Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC
Power(+5V)
Power(+3.3V)
N.C No Connection (2K Ref. product)
VCC
DQ0
DQ1
DQ2
DQ3
W
RAS
*A11(N.C)
A10
A0
A1
A2
A3
VCC
VSS
DQ7
DQ6
DQ5
DQ4
CAS
OE
A9
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
*A11 is N.C for K160811(2)D(5V/3.3V, 2K Ref. product)
B : 300mil 28 SOJ
F : 300mil 28 TSOP II
• K4F17(6)0811(2)D-B
• K4F17(6)0811(2)D-F
K4F170811D, K4F160811D
CMOS DRAMK4F170812D, K4F160812D
ABSOLUTE MAXIMUM RATINGS
* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted
to the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for
extended periods may affect device reliability.
Parameter Symbol
Rating
Units
3.3V 5V
Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 -1.0 to +7.0 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 -1.0 to +7.0 V
Storage Temperature Tstg -55 to +150 -55 to +150 °C
Power Dissipation PD 1 1 W
Short Circuit Output Current IOS Address 50 50 mA
RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)
*1 : VCC+1.3V/15ns(3.3V), VCC+2.0V/20ns(5V), Pulse width is measured at VCC
*2 : -1.3V/15ns(3.3V), -2.0V/20ns(5V), Pulse width is measured at VSS
Parameter Symbol
3.3V 5V
Units
Min Typ Max Min Typ Max
Supply Voltage VCC 3.0 3.3 3.6 4.5 5.0 5.5 V
Ground VSS 0 0 0 0 0 0 V
Input High Voltage VIH 2.0 -
VCC+0.3
*1
2.4 -
VCC+1.0
*1
V
Input Low Voltage VIL
-0.3
*2
- 0.8
-1.0
*2
- 0.8 V
DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)
Max Parameter Symbol Min Max Units
3.3V
Input Leakage Current (Any input 0≤VIN≤VIN+0.3V,
all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V
5V
Input Leakage Current (Any input 0≤VIN≤VIN+0.5V,
all other input pins not under test=0 Volt)
II(L) -5 5 uA
Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)
IO(L) -5 5 uA
Output High Voltage Level(IOH=-5mA) VOH 2.4 - V
Output Low Voltage Level(IOL=4.2mA) VOL - 0.4 V
K4F170811D, K4F160811D
CMOS DRAMK4F170812D, K4F160812D
*Note :
ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6 address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one fast page mode cycle time, tPC.
DC AND OPERATING CHARACTERISTICS (Continued)
ICC1* : Operating Current (RAS and CAS cycling @tRC=min.)
ICC2 : Standby Current (RAS=CAS=W=VIH)
ICC3* : RAS-only Refresh Current (CAS=VIH, RAS cycling @tRC=min.)
ICC4* : Fast Page Mode Current (RAS=VIL, CAS, Address cycling @tPC=min.)
ICC5 : Standby Current (RAS=CAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and CAS cycling @tRC=min.)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, CAS=0.2V,
DQ=Don′t care, TRC=31.25us(4K/L-ver), 62.5us(2K/L-ver),
TRAS=TRASmin~300ns
ICCS : Self Refresh Current
RAS=CAS=VIL, W=OE=A0 ~ A11=VCC-0.2V or 0.2V,
DQ0 ~ DQ7=VCC-0.2V, 0.2V or Open
Symbol Power Speed
Max
Units
K4F170812D K4F160812D K4F170811D K4F160811D
ICC1 Don′t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
ICC2
Normal
L
Don′t care
1
1
1
1
2
1
2
1
mA
mA
ICC3 Don′t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
ICC4 Don′t care
-50
-60
80
70
90
80
80
70
90
80
mA
mA
ICC5
Normal
L
Don′t care
0.5
200
0.5
200
1
250
1
250
mA
uA
ICC6 Don′t care
-50
-60
90
80
110
100
90
80
110
100
mA
mA
ICC7 L Don′t care 250 250 300 300 uA
ICCS L Don′t care 200 200 250 250 uA
K4F170811D, K4F160811D
CMOS DRAMK4F170812D, K4F160812D
CAPACITANCE (TA=25°C, VCC=5V or 3.3V, f=1MHz)
Parameter Symbol Min Max Units
Input capacitance [A0 ~ A11] CIN1 - 5 pF
Input capacitance [RAS, CAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ7] CDQ - 7 pF
Test condition (5V device) : VCC=5.0V±10%, Vih/Vil=2.4/0.8V, Voh/Vol=2.4/0.4V
Parameter Symbol
-50 -60
Units Notes
Min Max Min Max
Random read or write cycle time
tRC
90 110 ns
Read-modify-write cycle time
tRWC
133 155 ns
Access time from RAS
tRAC
50 60 ns 3,4,10
Access time from CAS
tCAC
13 15 ns 3,4,5
Access time from column address
tAA
25 30 ns 3,10
CAS to output in Low-Z
tCLZ
0 0 ns 3
Output buffer turn-off delay
tOFF
0 13 0 15 ns 6
Transition time (rise and fall)
tT
3 50 3 50 ns 2
RAS precharge time
tRP
30 40 ns
RAS pulse width
tRAS
50 10K 60 10K ns
RAS hold time
tRSH
13 15 ns
CAS hold time
tCSH
50 60 ns
CAS pulse width
tCAS
13 10K 15 10K ns
RAS to CAS delay time
tRCD
20 37 20 45 ns 4
RAS to column address delay time
tRAD
15 25 15 30 ns 10
CAS to RAS precharge time
tCRP
5 5 ns
Row address set-up time
tASR
0 0 ns
Row address hold time
tRAH
10 10 ns
Column address set-up time
tASC
0 0 ns
Column address hold time
tCAH
10 10 ns
Column address to RAS lead time
tRAL
25 30 ns
Read command set-up time
tRCS
0 0 ns
Read command hold time referenced to CAS
tRCH
0 0 ns 8
Read command hold time referenced to RAS
tRRH
0 0 ns 8
Write command hold time
tWCH
10 10 ns
Write command pulse width
tWP
10 10 ns
Write command to RAS lead time
tRWL
13 15 ns
Write command to CAS lead time
tCWL
13 15 ns
AC CHARACTERISTICS (0°C≤TA≤70°C, See note 1,2)
Test condition (3.3V device) : VCC=3.3V±0.3V, Vih/Vil=2.0/0.8V, Voh/Vol=2.0/0.8V
K4F170811D, K4F160811D
CMOS DRAMK4F170812D, K4F160812D
AC CHARACTERISTICS (Continued)
Parameter Symbol
-50 -60
Units Note
Min Max Min Max
Data set-up time
tDS
0 0 ns 9
Data hold time
tDH
10 10 ns 9
Refresh period (2K, Normal)
tREF
32 32 ms
Refresh period (4K, Normal)
tREF
64 64 ms
Refresh period (L-ver)
tREF
128 128 ms
Write command set-up time
tWCS
0 0 ns 7
CAS to W delay time
tCWD
36 40 ns 7
RAS to W delay time
tRWD
73 85 ns 7
Column address to W delay time
tAWD
48 55 ns 7
CAS precharge to W delay time
tCPWD
53 60 ns
CAS set-up time (CAS -before-RAS refresh)
tCSR
5 5 ns
CAS hold time (CAS -before-RAS refresh)
tCHR
10 10 ns
RAS to CAS precharge time
tRPC
5 5 ns
Access time from CAS precharge
tCPA
30 35 ns 3
Fast Page cycle time
tPC
35 40 ns
Fast Page read-modify-write cycle time
tPRWC
76 85 ns
CAS precharge time (Fast Page cycle)
tCP
10 10 ns
RAS pulse width (Fast Page cycle)
tRASP
50 200K 60 200K ns
RAS hold time from CAS precharge
tRHCP
30 35 ns
OE access time
tOEA
13 15 ns
OE to data delay
tOED
13 15 ns
Output buffer turn off delay time from OE
tOEZ
0 13 0 15 ns 6
OE command hold time
tOEH
13 15 ns
Write command set-up time (Test mode in)
tWTS
10 10 ns 11
Write command hold time (Test mode in)
tWTH
10 10 ns 11
W to RAS precharge time(C-B-R refresh)
tWRP
10 10 ns
W to RAS hold time(C-B-R refresh)
tWRH
10 10 ns
RAS pulse width (C-B-R self refresh)
tRASS
100 100 us 13,14,15
RAS precharge time (C-B-R self refresh)
tRPS
90 110 ns 13,14,15
CAS hold time (C-B-R self refresh)
tCHS
-50 -50 ns 13,14,15
Loading...