Samsung K4E661612C-TL60, K4E641612C-TC60, K4E641612C-TC50, K4E641612C-TC45, K4E661612C-TL50 Datasheet

CMOS DRAMK4E661612C,K4E641612C

4M x 16bit CMOS Dynamic RAM with Extended Data Out

DESCRIPTION

This is a family of 4,194,304 x 16 bit Extended Data Out Mode CMOS DRAMs. Extended Data Out Mode offers high speed random
access of memory cells within the same row. Refresh cycle(4K Ref. or 8K Ref.), access time (-45, -50 or -60), power consumption(Nor­mal or Low power) are optional features of this family. All of this family have CAS-before-RAS refresh, RAS-only refresh and Hidden
refresh capabilities. Furthermore, Self-refresh operation is available in L-version. This 4Mx16 EDO Mode DRAM family is fabricated
using Samsung′s advanced CMOS process to realize high band-width, low power consumption and high reliability.

FEATURES

• Part Identification

- K4E661612C-TC/L(3.3V, 8K Ref.)

- K4E641612C-TC/L(3.3V, 4K Ref.)

• Active Power Dissipation

Unit : mW

Speed 8K 4K

-45 324 468

-50 288 432

-60 252 396

• Extended Data Out Mode operation

• 2 CAS Byte/Word Read/Write operation

• CAS-before-RAS refresh capability

• RAS-only and Hidden refresh capability

• Fast parallel test mode capability

• Self-refresh capability (L-ver only)

• LVTTL(3.3V) compatible inputs and outputs

• Early Write or output enable controlled write

• JEDEC Standard pinout

• Available in Plastic TSOP(II) packages

• +3.3V±0.3V power supply

• Refresh Cycles
Part

NO.

K4E661612C* 8K

Refresh

cycle

Refresh time

Normal L-ver

64ms 128ms

K4E641612C 4K

* Access mode & RAS only refresh mode
: 8K cycle/64ms(Normal), 8K cycle/128ms(L-ver.)

CAS-before-RAS & Hidden refresh mode

: 4K cycle/64ms(Normal), 4K cycle/128ms(L-ver.)

• Performance Range

Speed

tRAC tCAC tRC tHPC

-45 45ns 12ns 74ns 17ns

-50 50ns 13ns 84ns 20ns

-60 60ns 15ns 104ns 25ns

SAMSUNG ELECTRONICS CO., LTD. reserves the right to
change products and specifications without notice.

RAS
UCAS
LCAS

W

A0~A12

(A0~A11)*1

A0~A8

(A0~A9)*1

FUNCTIONAL BLOCK DIAGRAM

Control
Clocks

Refresh Timer

Refresh Control

Refresh Counter

Row Address Buffer

Col. Address Buffer

Note) *1 : 4K Refresh

VBB Generator

Row Decoder

Memory Array

4,194,304 x 16

Cells

Column Decoder

Vcc
Vss

Sense Amps & I/O

Lower

Data in

Buffer
Lower

Data out

Buffer
Upper

Data in

Buffer
Upper

Data out

Buffer

DQ0

to

DQ7

OE

DQ8

to

DQ15

PIN CONFIGURATION (Top Views)

• K4E661612C-T

• K4E641612C-T

CMOS DRAMK4E661612C,K4E641612C

1

VCC
DQ0
DQ1
DQ2
DQ3

DQ4
DQ5
DQ6
DQ7

RAS

2
3
4
5
6

VCC

7
8
9
10
11

N.C

12

VCC

13

W

14
15

N.C

16

N.C

17

N.C

18

N.C

19

A0

20

A1

21

A2

22

A3

23

A4

24

A5

25

VCC

(400mil TSOP(II))

50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26

VSS
DQ15
DQ14
DQ13
DQ12
VSS
DQ11
DQ10
DQ9
DQ8
N.C
VSS
LCAS
UCAS
OE
N.C
N.C
A12(N.C)*
A11
A10
A9
A8
A7
A6
VSS

*(N.C) : N.C for 4K Refresh Product

Pin Name Pin function

A0 - A12 Address Inputs(8K Product)
A0 - A11 Address Inputs(4K Product)
DQ0 - 15 Data In/Out
VSS Ground
RAS Row Address Strobe
UCAS Upper Column Address Strobe
LCAS Lower Column Address Strobe
W Read/Write Input
OE Data Output Enable
VCC Power(+3.3V)
N.C No Connection

CMOS DRAMK4E661612C,K4E641612C

ABSOLUTE MAXIMUM RATINGS

Parameter Symbol Rating Units

Voltage on any pin relative to VSS VIN,VOUT -0.5 to +4.6 V
Voltage on VCC supply relative to VSS VCC -0.5 to +4.6 V
Storage Temperature Tstg -55 to +150 °C
Power Dissipation PD 1 W
Short Circuit Output Current IOS Address 50 mA

* Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to

the conditions as detailed in the operational sections of this data sheet. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.

RECOMMENDED OPERATING CONDITIONS (Voltage referenced to Vss, TA= 0 to 70°C)

Parameter Symbol Min Typ Max Units

Supply Voltage VCC 3.0 3.3 3.6 V
Ground VSS 0 0 0 V
Input High Voltage VIH 2.0 ­Input Low Voltage VIL

*1 : Vcc+1.3V at pulse width≤15ns which is measured at VCC
*2 : -1.3 at pulse width≤15ns which is measured at VSS

-0.3

*2

- 0.8 V

Vcc+0.3

*1

V

DC AND OPERATING CHARACTERISTICS (Recommended operating conditions unless otherwise noted.)

Parameter Symbol Min Max Units

Input Leakage Current (Any input 0≤VIN≤VCC+0.3V,
all other pins not under test=0 Volt)

Output Leakage Current
(Data out is disabled, 0V≤VOUT≤VCC)

Output High Voltage Level(IOH=-2mA) VOH 2.4 - V
Output Low Voltage Level(IOL=2mA) VOL - 0.4 V

II(L) -5 5 uA

IO(L) -5 5 uA

DC AND OPERATING CHARACTERISTICS (Continued)

Symbol Power Speed

ICC1 Don′t care

-45

-50

-60

K4E661612C K4E641612C

90
80
70

Max

130
120
110

CMOS DRAMK4E661612C,K4E641612C

Units

mA
mA
mA

ICC2

ICC3 Don′t care

ICC4 Don′t care

ICC5

ICC6 Don′t care

ICC7 L Don′t care 350 350 uA
ICCS L Don′t care 350 350 uA

ICC1* : Operating Current (RAS and UCAS, LCAS, Address cycling @tRC=min.)
ICC2 : Standby Current (RAS=UCAS=LCAS=W=VIH)
ICC3* : RAS-only Refresh Current (UCAS=LCAS=VIH, RAS, Address cycling @tRC=min.)
ICC4* : Extended Data Out Mode Current (RAS=VIL, UCAS or LCAS, Address cycling @tHPC=min.)
ICC5 : Standby Current (RAS=UCAS=LCAS=W=VCC-0.2V)
ICC6* : CAS-Before-RAS Refresh Current (RAS and UCAS or LCAS cycling @tRC=min)
ICC7 : Battery back-up current, Average power supply current, Battery back-up mode
Input high voltage(VIH)=VCC-0.2V, Input low voltage(VIL)=0.2V, UCAS, LCAS=CAS-before-RAS cycling or 0.2V
W, OE=VIH, Address=Don′t care, DQ=Open, TRC=31.25us
ICCS : Self Refresh Current
RAS=UCAS=LCAS=0.2V, W=OE=A0 ~ A12(A11)=VCC-0.2V or 0.2V, DQ0 ~ DQ15=VCC-0.2V, 0.2V or Open

Normal

L

Normal

L

Don′t care

-45

-50

-60

-45

-50

-60

Don′t care

-45

-50

-60

1
1

90
80
70

100

90
80

0.5

200
130

120
110

1
1

130
120
110

100

90
80

0.5

200
130

120
110

mA
mA

mA
mA
mA

mA
mA
mA

mA

uA

mA
mA
mA

*Note :

ICC1, ICC3, ICC4 and ICC6 are dependent on output loading and cycle rates. Specified values are obtained with the output open.
ICC is specified as an average current. In ICC1, ICC3 and ICC6, address can be changed maximum once while RAS=VIL. In ICC4,
address can be changed maximum once within one EDO mode cycle time, tHPC.

CMOS DRAMK4E661612C,K4E641612C

CAPACITANCE (TA=25°C, VCC=3.3V, f=1MHz)

Parameter Symbol Min Max Units

Input capacitance [A0 ~ A12] CIN1 - 5 pF
Input capacitance [RAS, UCAS, LCAS, W, OE] CIN2 - 7 pF
Output capacitance [DQ0 - DQ15] CDQ - 7 pF

AC CHARACTERISTICS (0°C≤TA≤70°C, See note 2)

Test condition : VCC=3.3V±0.3V, Vih/Vil=2.2/0.7V, Voh/Vol=2.0/0.8V

Parameter Symbol

Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
CAS to output in Low-Z
Output buffer turn-off delay from CAS
OE to output in Low-Z
Transition time (rise and fall)
RAS precharge time
RAS pulse width
RAS hold time
CAS hold time
CAS pulse width
RAS to CAS delay time
RAS to column address delay time
CAS to RAS precharge time
Row address set-up time
Row address hold time
Column address set-up time
Column address hold time
Column address to RAS lead time
Read command set-up time
Read command hold time referenced to CAS
Read command hold time referenced to RAS
Write command hold time
Write command pulse width
Write command to RAS lead time
Write command to CAS lead time
Data set-up time

tRC
tRWC
tRAC
tCAC
tAA
tCLZ
tCEZ
tOLZ
tT
tRP
tRAS
tRSH
tCSH
tCAS
tRCD
tRAD
tCRP
tASR
tRAH
tASC
tCAH
tRAL
tRCS
tRCH
tRRH
tWCH
tWP
tRWL
tCWL
tDS

-45 -50 -60

Min Max Min Max Min Max

74 84 104 ns

101 113 138 ns

45 50 60 ns 3,4,10
12 13 15 ns 3,4,5

23 25 30 ns 3,10
3 3 3 ns 3
3 13 3 13 3 13 ns 6,20
3 3 3 ns 3
1 50 1 50 1 50 ns 2

25 30 40 ns
45 10K 50 10K 60 10K ns

8 8 10 ns

35 38 40 ns

7 5K 8 10K 10 10K ns

11 33 11 37 14 45 ns 4

9 22 9 25 12 30 ns 10
5 5 5 ns
0 0 0 ns
7 7 10 ns
0 0 0 ns 13
7 7 10 ns 13

23 25 30 ns

0 0 0 ns
0 0 0 ns 8
0 0 0 ns 8
7 7 10 ns
6 7 10 ns
8 8 10 ns
7 7 10 ns 16
0 0 0 ns 9,19

Unit

s

Note

AC CHARACTERISTICS (Continued)

Parameter Symbol

Data hold time
Refresh period (Normal)
Refresh period (L-ver)
Write command set-up time
CAS to W delay time
RAS to W delay time
Column address to W delay time
CAS set-up time (CAS -before-RAS refresh)
CAS hold time (CAS -before-RAS refresh)
RAS to CAS precharge time
Access time from CAS precharge
Hyper Page cycle time
Hyper Page read-modify-write cycle time
CAS precharge time (Hyper page cycle)
RAS pulse width (Hyper page cycle)
RAS hold time from CAS precharge
OE access time
OE to data delay
CAS precharge to W delay time
Output buffer turn off delay time from OE
OE command hold time
Write command set-up time (Test mode in)
Write command hold time (Test mode in)
W to RAS precharge time (C-B-R refresh)
W to RAS hold time (C-B-R refresh)
Output data hold time
Output buffer turn off delay from RAS
Output buffer turn off delay from W
W to data delay
OE to CAS hold time
CAS hold time to OE
OE precharge time
W pulse width (Hyper Page Cycle)
RAS pulse width (C-B-R self refresh)
RAS precharge time (C-B-R self refresh)
CAS hold time (C-B-R self refresh)

tDH
tREF
tREF
tWCS
tCWD
tRWD
tAWD
tCSR
tCHR
tRPC
tCPA
tHPC
tHPRWC
tCP
tRASP
tRHCP
tOEA
tOED
tCPWD
tOEZ
tOEH
tWTS
tWTH
tWRP
tWRH
tDOH
tREZ
tWEZ
tWED
tOCH
tCHO
tOEP
tWPE
tRASS
tRPS
tCHS

CMOS DRAMK4E661612C,K4E641612C

-45 -50 -60

Min Max Min Max Min Max

7 7 10 ns 9,19

64 64 64 ms

128 128 128 ms

0 0 0 ns 7
24 27 32 ns 7,15
57 64 77 ns 7
35 39 47 ns 7

5 5 5 ns 17
10 10 10 ns 18

5 5 5 ns

24 28 35 ns 3
17 20 25 ns 21
47 47 56 ns 21

6.5 7 10 ns 14
45 200K 50 200K 60 200K ns
24 30 35 ns

12 13 15 ns 3

8 10 13 ns

36 41 52 ns

3 11 3 13 3 13 ns 6

5 5 5 ns
10 10 10 ns 11
10 10 10 ns 11
10 10 10 ns
10 10 10 ns

4 5 5 ns

3 13 3 13 3 13 ns 6,20

3 13 3 13 3 13 ns 6

8 15 15 ns

5 5 5 ns

5 5 5 ns

5 5 5 ns

5 5 5 ns

100 100 100 us 22,23,24

74 90 110 ns 22,23,24

-50 -50 -50 ns 22,23,24

Units Note

CMOS DRAMK4E661612C,K4E641612C

TEST MODE CYCLE

Parameter Symbol

Random read or write cycle time
Read-modify-write cycle time
Access time from RAS
Access time from CAS
Access time from column address
RAS pulse width
CAS pulse width
RAS hold time
CAS hold time
Column Address to RAS lead time
CAS to W delay time
RAS to W delay time
Column Address to W delay time
Hyper Page cycle time
Hyper Page read-modify-write cycle time
RAS pulse width (Hyper page cycle)
Access time from CAS precharge
OE access time
OE to data delay
OE command hold time

tRC
tRWC
tRAC
tCAC
tAA
tRAS
tCAS
tRSH
tCSH
tRAL
tCWD
tRWD
tAWD
tHPC
tHPRWC
tRASP
tCPA
tOEA
tOED
tOEH

( Note 11 )

-45 -50 -60

Min Max Min Max Min Max

79 89 109 ns

110 121 145 ns

50 55 65 ns 3,4,10,12
17 18 20 ns 3,4,5,12

28 30 35 ns 3,10,12
50 10K 55 10K 65 10K ns
12 10K 13 10K 15 10K ns
18 18 20 ns
39 43 50 ns
28 30 35 ns
29 35 39 ns 7
62 72 84 ns 7
40 47 54 ns 7
22 25 30 ns 21
52 53 61 ns 21
50 200K 55 200K 65 200K ns

29 33 40 ns 3

17 18 20 ns 3
13 18 20 ns
13 18 20 ns

Units Note

NOTES

1.

2.

3.

4.

5.

6.

7.

8.

9.

10.

11.

12.

13.

14.

15.

CMOS DRAMK4E661612C,K4E641612C

An initial pause of 200us is required after power-up followed by any 8 RAS-only or CAS-before-RAS refresh cycles before
proper device operation is achieved.
Input voltage levels are Vih/Vil. VIH(min) and VIL(max) are reference levels for measuring timing of input signals. Transition
times are measured between VIH(min) and VIL(max) and are assumed to be 2ns for all inputs.
Measured with a load equivalent to 1 TTL load and 100pF.
Operation within the tRCD(max) limit insures that tRAC(max) can be met. tRCD(max) is specified as a reference point only.

If tRCD is greater than the specified tRCD(max) limit, then access time is controlled exclusively by tCAC.
Assumes that tRCD≥tRCD(max).
This parameter defines the time at which the output achieves the open circuit condition and is not referenced to Voh or Vol.

tWCS, tRWD, tCWD and tAWD are non restrictive operating parameters. They are included in the data sheet as electric charac-

teristics only. If tWCS≥tWCS(min), the cycles is an early write cycle and the data output will remain high impedance for the
duration of the cycle. If tCWD≥tCWD(min), tRWD≥tRWD(min) and tAWD≥tAWD(min), then the cycle is a read-modify-write cycle
and the data output will contain the data read from the selected address. If neither of the above conditions is satisfied, the
condition of the data out is indeterminate.
Either tRCH or tRRH must be satisfied for a read cycle.
This parameters are referenced to the CAS leading edge in early write cycles and to the W falling edge in OE controlled write
cycle and read-modify-write cycles.
Operation within the tRAD(max) limit insures that tRAC(max) can be met. tRAD(max) is specified as a reference point only. If

tRAD is greater than the specified tRAD(max) limit, then access time is controlled by tAA.

These specifiecations are applied in the test mode.
In test mode read cycle, the value of tRAC, tAA, tCAC is delayed by 2ns to 5ns for the specified values. These parameters
should be specified in test mode cycles by adding the above value to the specified value in this data sheet.

tASC, tCAH are referenced to the earlier CAS falling edge.
tCP is specified from the last CAS rising edge in the previous cycle to the first CAS falling edge in the next cycle.
tCWD is referenced to the later CAS falling edge at word read-modify-write cycle.

K4E64(6)1612C Truth Table

RAS LCAS UCAS W OE DQ0 - DQ7 DQ8-DQ15 STATE

H X X X X Hi-Z Hi-Z Standby

L H H X X Hi-Z Hi-Z Refresh
L L H H L DQ-OUT Hi-Z Byte Read
L H L H L Hi-Z DQ-OUT Byte Read
L L L H L DQ-OUT DQ-OUT Word Read
L L H L H DQ-IN - Byte Write
L H L L H - DQ-IN Byte Write
L L L L H DQ-IN DQ-IN Word Write
L L L H H Hi-Z Hi-Z -

CMOS DRAMK4E661612C,K4E641612C

tCWL is specified from W falling edge to the earlier CAS rising edge.

16.

tCSR is referenced to earlier CAS falling before RAS transition low.

17.

18.

tCHR is referenced to the later CAS rising high after RAS transition low.

RAS

LCAS

UCAS

tCSR tCHR

tDS is specified for the earlier CAS falling edge and tDH is specified by the later CAS falling edge in early write cycle.

19.

LCAS

UCAS

tDS tDH

DQ0 ~ DQ15

If RAS goes high before CAS high going, the open circuit condition of the output is achieved by CAS high going.

20.

21.

tASC≥6ns, Assume tT=2.0ns, if tASC≤6ns, then tHPC(min) and tCAS(min) must be increased by the value of "6ns-tASC".

22.

If tRASS≥100us, then RAS precharge time must use tRPS instead of tRP.

23.

For RAS-only-Refresh and Burst CAS-before-RAS refresh mode, 4096 cycles(4K/8K) of burst refresh must be executed within
64ms before and after self refresh, in order to meet refresh specification.

24.

For distributed CAS-before-RAS with 15.6us interval, CBR refresh should be executed with in 15.6us immediately before and
after self refresh in order to meet refresh specification.

Din

WORD READ CYCLE

CMOS DRAMK4E661612C,K4E641612C

VIH -

RAS

VIL -

VIH -

UCAS

VIL -

VIH -

LCAS

VIL -

VIH -

A

VIL -

VIH -

W

VIL -

VIH -

OE

VIL -

DQ0 ~ DQ7

VOH -
VOL -

DQ8 ~ DQ15

VOH -
VOL -

tCRP

tCRP

tRAD

tASR tRAH tASC

ROW

ADDRESS

tRCS

OPEN

OPEN DATA-OUT

tRAC

tRAC

tRAS

tCSH

tCSH

tCAH

COLUMN

ADDRESS

tAA

tCLZ

tCLZ

tCAC

tCAC

tRC

tCAS

tRSHtRCD
tCAS

tRAL

tOLZ

tOEA

tRP

tRSHtRCD

tCRP

tCRP

tRCH

tRRH

tCEZ

tOEZ

DATA-OUT

tCEZ

tOEZ

Don′t care

Undefined

LOWER BYTE READ CYCLE

NOTE : DIN = OPEN

CMOS DRAMK4E661612C,K4E641612C

VIH -

RAS

VIL -

VIH -

UCAS

VIL -

VIH -

LCAS

VIL -

VIH -

A

VIL -

VIH -

W

VIL -

VIH -

OE

VIL -

DQ0 ~ DQ7

VOH -
VOL -

DQ8 ~ DQ15

VOH -
VOL -

tCRP

tCRP

tRAD

tASR tRAH tASC

ROW

ADDRESS

tRCS

OPEN DATA-OUT

tRAC

tRAS

tCSH

tCAH

COLUMN

ADDRESS

tAA

tCLZ

tOLZ

tRC

tRP

tRPC

tRSHtRCD
tCAS

tRAL

tRCH

tRRH

tCEZ

tOEZ

tOEA

tCAC

OPEN

Don′t care

Undefined