Samsung C3332 Service Manual
L105
L113
H
H
H
H
H
H
COMPANY NAME
Drawing Number
LB_RX_N
LB_RX_P
HB_RX_N
HB_RX_P
C127
81
86
FM_LNA_OUT
Address
City
Sheet
8
8
1 6
Size
A3
of
1
SAMSUNG CONFIDENTIAL
THIS DOCUMENT CONTAINS CONFIDENTIAL
PROPRIETARY INFORMATION THAT IS
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
ANT100
A
A
1
1
2
2
ANT101
1
1
2
2
R101
B
B
VLOGIC
RAMP
TX_EN
LB_TX
HB_TX
C
C
R112
L101
C129
L115
L220
C101
R102
R104
R106
R113
L116
L117
C109
2
2
RFS100
KMS-560-002-BEF
A
G
G
2
1C3
4
C102
22nH
2
VLOGIC
3
VRAMP
4
TX_EN
27
GSM_IN
29
DCS|PCS_IN
G
G
1
8
7
C110
3
3
GT-C3332_REV0.8
RF
L109
L108
C108
17
ANT
PAM100
G
G
G
G10G15G16G
G
G
G
20
21
22
18
19
9
C104
C107
30
VBATT
G
23
G24G25G26G
BS1
BS2
RX1
RX2
G
G34G35G
G
G
33
36
28
31
32
VDD_1.8V
VDD_1.8V
D
D D
C113
VDD_PADS
A5
TP_BT_RST
TP_100
VREG_EN_RST#
E6
SPI_PCM#_SEL
D4
PCM_IN
E2
PCM_OUT
D2
PCM_SYNC
D3
PCM_CLK
E1
PIO0
E4
PIO1
D5
PIO2
E3
PIO3
E5
PIO4
C6
PIO9
R111
E
E
BT_CLK_32KHZ
F
F
BT_RST
PCM_TXD
PCM_RXD
PCM_SYNC
PCM_CLK
BT_REQ_CLK
C112
C111
B4
A4
C3
VREG_IN_HV
VREG_OUT_HV
U101
NC1NC
VSS_DIG
2
C114
C115
D6
B2
C2
VDD_DIG
VDD_AUX
VDD_RADIO
VSS_RADIO
VSS_AUX
A1
C1
C4
XTAL_OUT
UART_RTS
UART_CTS
C117
B1
BT_RF
A2
A3
XTAL_IN
A6
UART_TX
B6
C5
B5
UART_RX
TP_UART_TXD
TP_UART_RXD
C118
C124
CLK26M_BT
UART2_RXD
4IN2
UART2_TXD
C132
BT
2
1
1
2
3
3
4
4
VBAT
C105
5
R103
6
12
13
11
G
14
G
ANTENNA
BT Antenna
GSM 900 / PCS 1900 RX
GSM 850 / DCS 1800 RX
TX(GSM/DCS/PCS)
V_BAT
F101
OUT
G1G
3
C119
4
4
C103
BS1
GSM850_DCS1800_RX
GSM900_PCS1900_RX
C120
5
5
6
77
RF PART / BT MODULE
F100
GSM900_PCS1900_RX
GSM850_DCS1800_RX
C106
L107
L114
Mode
OUT2
1
IN1
OUT2
OUT1
4
IN2
OUT1
G
G3G
G
2
5
10
L110
TX_EN
GSM850 Rx (RX1)
GSM900 Rx (RX2)
DCS1800 Rx (RX1)
PCS1900 Rx (RX2)
GSM900_850 Tx
DCS_PCS Tx
C123
Changed by
L121
R114
C116
C125
L119
R108
C128
Date Changed
6
6
3
Q100
1
2
R109
FM_LNA_SW
FM_ANT
C121
C122
5
5
L103
6
7
8
9
L111
L L
L
L
L
H L
H
R115
C130
C131
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK
7
7
L100
L104
L106
L112
BS1 BS2
H
L
H
H
FMR TR
L118
C126
TITLE:
GT-C3332_REV0.8
VERdegnahC emiT
A
A
B
B
C
C
D
E
E
F
F
1
SAMSUNG CONFIDENTIAL
THIS DOCUMENT CONTAINS CONFI DENTI AL
PROPRI ETARY I NFORMATION THAT I S
SAMSUNG ELECTRONICS CO’S PROPERTY.
DO NOT DISCLOSE TO OR DUPLICATE FOR OTHERS
EXCEPT AS AUTHORIZED BY SAMSUNG.
A
VDD_2.85V
VBAT
B
C
VDD_1.8V
C213
C211
C212
VDD_IO1_1.8V
VDD_IO2_1.8V
VDD_EBU_1.8V
D
E
KEY_COL(0:3)
F
VDD_1.8V
KEY_ROW(0:5)
R203
VCAM_IO_1.8V
G
CAM_SCL
CAM_SDA
H
1
2
4 113
5
6
7
BB / MEMORY / JTAG
VDD_IO2_1.8V
VDD_IO1_1.8V
VDD_NEG_1.3VVDD_1.8V V_EARMIC
C209
DDR_DQ(0:15)
CAM_PCLK_IN
CAM_PWR_EN
USB_I2C_SDA
KEY_COL(0)
KEY_COL(1)
KEY_COL(2)
KEY_COL(3)
KEY_ROW(0)
KEY_ROW(5)
CAM_D(0:7)
FM_LNA_SW
CAM_RST
CAM_HSYNC
CAM_VSYNC
LCD(0)
LCD(1)
LCD(2)
LCD(3)
LCD(4)
LCD(5)
LCD(6)
LCD(7)
LCD_WR
LCD_RST
TSP_SCL
TSP_SDA
DSDS_SCL
EAR_AMP_EN
C233
SD_DATA(0)
SD_DATA(1)
SD_DATA(2)
SD_DATA(3)
PCM_RXD
PCM_TXD
PCM_CLK
PCM_SYNC
DDR_LDMD
DDR_UDMD
DDR_LDQSD
DDR_UDQSD
C210
DDR_DQ(0)
DDR_DQ(1)
DDR_DQ(2)
DDR_DQ(3)
DDR_DQ(4)
DDR_DQ(5)
DDR_DQ(6)
DDR_DQ(7)
DDR_DQ(8)
DDR_DQ(9)
DDR_DQ(10)
DDR_DQ(11)
DDR_DQ(12)
DDR_DQ(13)
DDR_DQ(14)
DDR_DQ(15)
MEM_AD(0)
MEM_AD(1)
MEM_AD(2)
MEM_AD(3)
MEM_AD(4)
MEM_AD(5)
MEM_AD(6)
MEM_AD(7)
MEM_AD(8)
MEM_AD(9)
MEM_AD(10)
MEM_AD(11)
MEM_AD(12)
MEM_AD(13)
MEM_AD(14)
MEM_AD(15)
CAM_D(0)
CAM_D(1)
CAM_D(2)
CAM_D(3)
CAM_D(4)
CAM_D(5)
CAM_D(6)
CAM_D(7)
LCD_CS
LCD_RS
FLM
R210
LCD_TP
TSP_INT
CHAR_ADC
AUDIO_ADC
DSDS_SDA
C234
SD_CLK
SD_CMD
T6
T7
K9
J12
F11
P16
P18
P10
VAUX
L1
A0
M2
A1
J2
A2
L3
A3
K3
A4
J1
A5
K2
A6
K4
A7
H6
A8
H1
A9
H3
A10
G3
A11
G2
A12
H2
A13
H4
A14
G6
A15
R5
A_D0
N5
A_D1
N3
A_D2
M4
A_D3
M1
A_D4
P3
A_D5
R3
A_D6
R4
A_D7
T3
A_D8
M5
A_D9
L5
A_D10
N4
A_D11
N6
A_D12
P7
A_D13
R1
A_D14
M3
A_D15
A8
CIF_D0
B8
CIF_D1
C7
CIF_D2
A9
CIF_D3
B9
CIF_D4
C8
CIF_D5
C9
CIF_D6
E10
CIF_D7
G9
CIF_PD
G8
CIF_PCLK
CIF_PCLK
E8
CIF_RESET
F9
CIF_HSYNC
E9
CIF_VSYNC
E3
DIF_D0
D3
DIF_D1
F4
DIF_D2
D5
DIF_D3
C4
DIF_D4
C3
DIF_D5
B3
DIF_D6
D4
DIF_D7
C1
DIF_D8
F5
DIF_CS1
E5
DIF_CD
E4
DIF_HD
D6
DIF_RD
C2
DIF_VD
C5
DIF_WR
B2
DIF_RESET
A11
KP_IN0
A12
KP_IN1
B12
KP_IN2
C12
KP_IN3
D12
KP_IN4
E12
KP_IN5
D11
KP_OUT0
B11
KP_OUT1
C11
KP_OUT2
E11
KP_OUT3
A2
KP_OUT4
F12
KP_OUT5
N14
M0
T13
M1
R13
M2
J15
MON1
J14
MON2
C6
MON3
R14
MICN1
R15
MICN2
T14
MICP1
T15
MICP2
F3
MMCI_DAT0
G5
MMCI_DAT1
G4
MMCI_DAT2
E1
MMIC_DAT3
F2
MMCI_CLK
F1
MMCI_CMD
A10
I2S1_RX
B10
I2S1_TX
B7
I2C_SCL
A7
I2C_SDA
D10
I2S1_CLK0
C10
I2S1_WA0
L2
BC0_N
J3
BC1_N
L4
BC2_N
G1
BC3_N
R18
N10
K10
B14
H15
G16
VBAT
G15
G11
G10
VCHG
VDDFS
VDDMS
VDDIO1
VDDIO2
VDDRF2
VBATSP
VDDNEG
VDDCHG
VDD1V81
VDDCORE
VDDCORE
VDD1V8CP
VBAT_PMU
GSM RX
GSM TX
PCS/DCS RX
PCS/DCS TX
SPK P/N
EAR L/R
RCV P/N
V_BAT
UCP201
VSSRF
VSSMS
VSSRF
VSSCORE
AGND
VSSCORE
VSSCORE
VSSRF
VSSMS
VSSCORE
VSSRF_D
VSSRF
VSSLSR
VSSCORE
VSSRF_D
A3
R7
J11
F17
L13
F14
F15
F16
L16
F10
P13
P17
E14
H11
C17
G14
C214
C215
C216 C217
MEM_AD(0:15)
LCD(0:7)
VDD_IO2_1.8V
R201
LCD_RD
R202
TH200
R204
MIC_BB_N
AUX_MIC_N
MIC_BB_P
AUX_MIC_P
R207R206
32
VDD_TDC_1.3V
VDD_RF2_2.5V
VDD_TRX_1.4V
L9
F6
P6
P9
H8
P14
P15
E13
N13
B16
M10
M11
VSIM
VMIC
VUSB
VMMC
VUMIC
VDDXO
VDDTRX
VDDTDC
VSSRF_D
VSS_PMU
VSS_SD1
T9
T11
4 6
E2
VDD_DLL
VDD_SD1
VDD_EBU
VDD_EBU
VDD_FMR
CC_IO
SIM_IO
D1
CC_CLK
SIM_CLK
D2
CC_RST
SIM_RST
A6
CLKOUT0
F8
CLKOUT2
T2
BFCLKO_0
NAND_CLK
J4
BFCLKO_1
DDR_CLKn
L18
F32K
L17
OSC32K
T17
CP1
R17
CP2
C227
M9
CS
R8
CSB
N2
CS0_N
R2
CS1_N
R6
CS2_N
H13
DIGUP1
G12
DIGUP2
J13
DIGUP_CLK
K14
DMINUS
K13
DPLUS
M17
EPN
M18
EPP
N18
LSN
N17
LSP
D18
RX12
F18
RX34
C18
RX12X
E18
RX34X
A17
TX1
B17
TX2
H14
SWIF_TXRX
B4
USIF1_CTS_N
A5
USIF1_RST_N
J10
USIF2_CTS_N
H9
USIF2_RTS_N
B5
USIF1_RXD_MRST
A4
USIF1_TXD_MTSR
J9
USIF2_RXD_MRST
H10
USIF2_TXD_MTSR
L11
LEDDRV
L10
LEDFBN
K12
LEDFBP
L8
SENSEN
M8
SENSEP
B18
FE1
A16
FE2
M12
FMRIN
M13
FMRINX
G13
FSYS1
F13
FSYS2
K17
FSYS_EN
R16
HSL
T16
HSR
A13
XO
B13
XOX
R11
ONOFF
R9
SD1SW
T8
SD1_FB
P4
CKE
DDR_CKE
P5
CAS_N
DDR_CASn
P2
RAS_N
DDR_RASn
T4
ADV_N
NAND_ADVn
P1
RD_N
NAND_RDn
L15
RESET_N
H17
TRST_N
TRSTn
J8
WAIT_N
NAND_WAITn
T5
WR_N
WEn
K18
TRIG_IN
B6
T2IN
C15
PABIAS
B15
PABS
C14
PAEN
R12
ACD
P11
ANAMON
C16
VDET
T10
VIB
P12
VPMU
A15
VRAMP
RAMP
T12
VREF
H12
VRF1
L12
VRTC
B1
FCDP_RBN
J5
SDCLKO
H18
TCK
J18
TDI
J17
TDO
G18
TMS
K8
VSHNT
VSS_VIB
NC3
NC
NC4
NC
NC1
NC2
1
2
T1
A1
T18
R10
A18
5
VDD_EBU_1.8V
C219
C218
BT_CLK_32KHZ
CAM_MCLK_OUT
CS0n_OneNAND
CS1n_RAM
BT_RST
EAR_SW
USB_DM_BB
USB_DP_BB
RCV_N
RCV_P
SPK_N
SPK_P
LB_RX_P
HB_RX_P
LB_RX_N
HB_RX_N
LB_TX
HB_TX
LCD_BL_EN
USB_I2C_SCL
USB_SW_DET
MEM_INT
UART1_RXD
UART1_TXD
UART2_RXD
UART2_TXD
VBAT
VLOGIC
BS1
ISOLATE
CLK26M_BT
BT_REQ_CLK
EAR_SPK_L
EAR_SPK_R
ONKEY
RST_MAX8985
RST_BB_J
RST_BB
R205
TX_EN
EAR_ADC
VF
DDR_CLK
TCK
TDI
TDO
TMS
C236
C220
L201
VDD_IO1_1.8V
VBAT
VMMC_2.85V
VSIM_2.85V
V_MIC_2.2V
C221 C222
C224
C223
C225
OSC200
C229
C228
C230
FM_LNA_OUT
C231
OSC201
VDD_1.8V
L202
C232
22000nF
10V
CLOSE TO THE PIN
4213
3.5_DETECT
VRTC_2.3V
VDD_1.8V
C235
C238
C237
7 11
VUSB_3.1V
VBUS_5V_J
JIG_ON_J
VDD_NEG_1.3V
8
C200
C201
NAND_WAITn
CS0n_OneNAND
VDD_TDC_1.3VVDD_RF2_2.5V
VDD_TRX_1.4V
C203
C202
VDD_EBU_1.8V
R200
TP_CS0n_OneNAND
9
VUSB_3.1V
NAND_CLK
MEM_INT
NAND_ADVn
NAND_RDn
WEn
RST_BB
10
C204
C205
C206
P7
P8
A7
H13
N13
C14
B13
G13
M14
VDDD
VDDQDA8VDDQD
VDDQD
VDDQD
VDDQD
VDDQD
VDDQD
VDDQD
VDDQD
VDDQD
D4
A1_INDEX
TP_NAND_CLK
F5
CLKO
TP_MEM_INT
E8
INTO
C6
RDYO
C4
TP_NAND_ADVN
_AVDO
C5
_CEO
TP_NAND_RDn
B3
_OEO
B6
TP_WEn
_WEO
B5
TP_RST_BB
_RPO
A1
DNU
A2
DNU
A13
DNU
A14
DNU
B1
DNU
B14
DNU
N1
DNU
N14
DNU
P1
DNU
P2
DNU
P13
DNU
P14
DNU
A3
NC
B4
NC
B7
NC
B8
NC
B9
UME201
NC
B11
NC
B12
NC
C2
NC
C10
NC
C11
NC
D12
NC
D13
NC
E1
NC
E6
NC
E7
NC
E9
NC
E10
NC
E12
NC
F10
NC
G10
NC
J13
NC
L1
NC
M3
NC
M9
NC
M10
NC
M11
NC
M12
NC
N3
NC
N7
NC
N9
NC
N10
NC
N11
NC
N12
NC
1
NC
2
NC
VSSQD
VSSQD
VSSQD
VSSQD
VSSQD
VSSQD
VSSQD
VSSO
VSSQD
VSSQD
VSSQD
P9
A9
A6
N6
J14
L14
F14
P12
D14
A12
VDD_EBU_1.8V
C207
C208
E5
A5
H1
K7
N2
D1
M2
P11
A11
G12
VDDD
VDDD
VDDD
VDDD
VDDD
VCCO
VCCO
VCCQO
VCCQO
TP_MEM_AD(0)
F3
MEM_AD(0)
A0D
L3
MEM_AD(1)
A1D
E3
MEM_AD(2)
A2D
K3
MEM_AD(3)
A3D
J1
MEM_AD(4)
A4D
J3
MEM_AD(5)
A5D
K1
MEM_AD(6)
A6D
H3
MEM_AD(7)
A7D
L2
MEM_AD(8)
A8D
G2
MEM_AD(9)
A9D
K2
MEM_AD(10)
A10D
H2
MEM_AD(11)
A11D
F2
MEM_AD(12)
A12D
D3
MEM_AD(14)
BA0D
G3
MEM_AD(15)
BA1D
TP_DDR_DQ(0)
M13
DDR_DQ(0)
DQ0D
N8
DDR_DQ(1)
DQ1D
K12
DDR_DQ(2)
DQ2D
M8
DDR_DQ(3)
DQ3D
K14
DDR_DQ(4)
DQ4D
L12
DDR_DQ(5)
DQ5D
M7
DDR_DQ(6)
DQ6D
L13
DDR_DQ(7)
DQ7D
C8
DDR_DQ(8)
DQ8D
C12
DDR_DQ(9)
DQ9D
F13
DDR_DQ(10)
DQ10D
F12
DDR_DQ(11)
DQ11D
B10
DDR_DQ(12)
DQ12D
C9
DDR_DQ(13)
DQ13D
C7
DDR_DQ(14)
DQ14D
E13
DDR_DQ(15)
DQ15D
E14
UDQSD
DDR_UDQSD
M6
MEM_AD(0)
ADQ0O
P6
MEM_AD(1)
ADQ1O
M5
MEM_AD(2)
ADQ2O
N5
MEM_AD(3)
ADQ3O
P5
MEM_AD(4)
ADQ4O
M4
MEM_AD(5)
ADQ5O
N4
MEM_AD(6)
ADQ6O
P4
MEM_AD(7)
ADQ7O
H5
MEM_AD(8)
ADQ8O
J5
MEM_AD(9)
ADQ9O
K5
MEM_AD(10)
ADQ10O
K6
MEM_AD(11)
ADQ11O
K9
MEM_AD(12)
ADQ12O
K10
MEM_AD(13)
ADQ13O
J10
MEM_AD(14)
ADQ14O
H10
MEM_AD(15)
ADQ15O
G1
CKED
G14
CLKD
C13
UDMD
K13
LDMD
J12
LDQSD
D2
_CSD
H14
_CLKD
F1
TP_DDR_CASn
_CASD
E2
TP_DDR_RAS_n
_RASD
C3
_WED
VSSD
VSSD
VSSD
VSSD
VSSO
VSSD
VSSO
VSSD
VSSO
VSSO
J2
P3
C1
B2
A4
K8
G5
M1
P10
H12
A10
DDR_CKE
DDR_CLK
DDR_UDMD
DDR_LDMD
DDR_LDQSD
DDR_CLKn
DDR_CASn
DDR_RASn
WEn
TP_CS1n_RAM
12
A
MEM_AD(0:15)
B
DDR_DQ(0:15)
C
MEM_AD(0:15)
D
CS1n_RAM
E
MEMORY
1G OneNand + 512M DDR SDRAM
C3330L
Sheet
F
G
R211
H
Size
A3
of
62
12
BOTH HOLE (2.7PI)
VBAT
JTAG200
1
VBATT
2
V_BUS
3
GND
4
D+
JIG_RXD
5
HP|PWR
6
D-
JIG_TXD
7
RXD
JIG_RXD
8
TXD
JIG_TXD
9
JIG_ID
ID
10
ANT
RST_BB_J
VDD_IO1_1.8V
CN200
1
1
2
TMS
TDI
TCK
TRSTn
TDO
TXD1_J
RXD1_J
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
G200
SPK HOLE (1.5PI)
G204
JTAG
Changed by
Date Changed
8
9
Time Changed
10
G208
G206
G207
G203
G201
C3332
C3330
G210
G205
R208 R209
Engineer
Drawn by
R&D CHK
DOC CTRL CHK
MFG ENGR CHK
QA CHK
SAMSUNG ELECTRONICS
TITLE
GT-C3332_REV0.8
REV
Drawing Number
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