SM-R400 User’s Manual
Company Date Version
V2.4.16
5
Identification with Radio and Optical
*RFID Functional Description
The transmitter supports both in-phase quadrature (IQ) vector modulation and polar modulation. The direct IQ up-
conversion is intended for phase reversal amplitude shift keying (PR-ASK). The polar modulation is intended for
double sideband amplitude shift keying (DSB-ASK). In both cases, the signals are generated in the digital domain
and converted to analog signals by sigma-delta digital-to-analog converters (DACs) followed by reconstruction
filters. The integrated power amplifier can be operated in three different modes:
• Class F with high output power and without internal amplitude modulation (AM)
The integrated power amplifier acts as a driver for an external power amplifier. The external power amplifier
performs the amplitude modulation, but it does require an external modulator. This is likely to be done with DSB
and not PR-ASK.
• Class F with drain modulation using an external modulator
• Class A required for PR-ASK An optional linear external power amplifier can be used to increase the output power
to the maximum allowed level.
The receiver is in principle a homodyne to ensure that as much as possible of the transmitter leakage falls on DC.
The receiver down-conversion mixer uses an internal local oscillator (LO). The receiver uses a single on-chip, low
noise amplifier (LNA) to maintain a desirable signal to noise ratio.
After down conversion, the DC signal is removed internal which reduces off chip component requirements and
lowers implementation costs. The analog intermediate frequency (IF) filter provides coarse channel selectivity. It
has programmable bandwidth to accommodate the large range of required data rates. The coarsely filtered I and Q
signals are analog-to-digital converted. Automatic intermediate frequency gain stepping in the filter reduces the
required dynamic range of the analog-to-digital converter (ADC). Sharp and well-controlled digital filtering
supplements the coarse analog filtering. Digital logic also performs the demodulation.
The reader chip logic derives the clocks for the digital blocks from a 24 MHz reference frequency signal originating
from an external temperature-compensated crystal oscillator (TCXO). The sigma-delta DACs run directly off the 24
MHz signal. The sigma-delta ADCs run off a 48 MHz clock generated by an integrated frequency doubler.
The Indy R500 includes a fully integrated voltage-controlled oscillator (VCO). The loop filter is external so that the
synthesizer meets the stringent phase noise requirements and allows flexibility. The reader chip logic derives the
time reference required by the phase locked loop and the digital blocks from the 24-MHz reference frequency.
The Indy R500 reader chip supports two interfaces—one low speed parallel interface with a data rate of up to 20
Mbps and one serial interface with data rates of 150 Mbps to (downstream), and up to 450 Mpbs from (upstream)
the Indy R500 reader chip. The serial interface is used on the Impinj reference design and firmware. The interfaces
are multiplexed on the same pins, and the interface is determined during power-up. Both interfaces operate at 3.3
V. The Indy R500 executes one low level instruction at a time from those written into a first in, first out buffer. All
information is transferred via the register bank, and state machines control the reader chip.