㆔合微科股份㈲限公司
S
AMHOP
GENERAL DESCRIPTION FEATURES
Microelectronics Corp.
SM6B595
8-BIT LED DRIVER
The SM6B595 is specifically designed for
USE in LED DISPLAY.
This device contains an 8-bit shift register,
8 bit D-type storage register an d open-drain
NMOS output drivers.
The serial output allows for cascading of the
data from the shift register to additional
devices.
PIN ASSIGNMENTS
* Maximum output terminal voltage: 30V.
* Maximum continuous drain current:100mA.
* Typical R
DS(ON) :
5 Ω
* Devices are cascadable
* Low power consumption
* Serial data transfer rate: 25 MHz.
NC
VCC
SERIN
OUT0
OUT1
OUT2
OUT3
SRCLR
G
GND
1
2
3
4
5
6
7
8
9
10
SM6B595P
20 PIN DIP
20
19
18
17
16
15
14
13
12
11
NC
GND
SEROUT
OUT7
OUT6
OUT5
OUT4
SRCK
RCK
GND
NC
VCC
SERIN
OUT0
OUT1
OUT2
OUT3
SRCLR
G
GND
1
2
3
4
5
6
7
8
9
10
SM6B595F
20 PIN SOP
20
19
18
17
16
15
14
13
12
11
NC
GND
SEROUT
OUT7
OUT6
OUT5
OUT4
SRCK
RCK
GND
Page 1
SEP, 2002
㆔合微科股份㈲限公司
S
AMHOP
PIN DESCRIPTION
Microelectronics Corp.
SM6B595
8-BIT LED DRIVER
Pin NO.
1
2
3
4-7
8
9 G
10-11 GND Ground terminal.
Pin Name
NC
Vcc
SER IN
OUT0~3
SRCLR
No connection
5V supply voltage terminal.
Input terminal of a serial-data for shift-register.
Output terminals.
Input terminal of clear signal for shift-register. When SRCLR is
low, the input shift-register is cleared.
Input terminal of output enable. All outputs (OUT0~7) do off
with "H" level of G-terminal, and do on with "L" level input.
Function Description
12 RCK
13
14-17
18
19
20
SRCK
OUT4~7
SER OUT
GND
NC
Input terminal of a clock for storage-register. Data transfer
through storage-register on the rising edge of the storageregister clock.
Input terminal of a clock for shift-register. Data transfer through
shift-register on the rising edge of the shift-register clock.
Output terminals.
Output terminal of serial-data for next SER IN terminal.
Ground terminal.
No connection.
Page 2
SEP, 2002