ROHS 3D7324 Technical data
3D7324
MONOLITHIC QUADRUPLE
FIXED DELAY LINE
(SERIES 3D7324)
FEATURES
• All-silicon, low-power CMOS technology
• TTL/CMOS compatible inputs and outputs
• Vapor phase, IR and wave solderable
• Auto-insertable (DIP pkg.)
• Low ground bounce noise
• Leading- and trailing-edge accuracy
• Delay range: 6 through 6000ns
• Delay tolerance: 2% or 1.0ns
• Temperature stability: ±3% typ (-40C to 85C)
• Vdd stability: ±1% typical (4.75V to 5.25V)
• Minimum input pulse width: 20% of total delay
• 14-pin Gull-Wing available as drop-in
replacement for hybrid delay lines
I1
N/C
I2
I3
I4
N/C
GND
3D7324-xx DIP
3D7324G-xx Gull-Wing
For mechanical dimensions, click here.
For package marking details, click here.
PACKAGES
1
14
2
13
3
12
4
11
5
10
6
9
7
8
VDD
N/C
O1
N/C
O2
O3
O4
N/C
N/C
GND
I1
I2
I3
I4
3D7324D-xx
(150 Mil)
FUNCTIONAL DESCRIPTION
The 3D7324 Quadruple Delay Line product family consists of fixeddelay CMOS integrated circuits. Each package contains four matched,
independent delay lines. Delay values can range from 6ns through
6000ns. The input is reproduced at the output without inversion,
shifted in time as per the user-specified dash number. The 3D7324 is
TTL- and CMOS-compatible, capable of driving ten 74LS-type loads,
and features both rising- and falling-edge accuracy.
The all-CMOS 3D7324 integrated circuit has been designed as a
reliable, economic alternative to hybrid TTL fixed delay lines. It is
offered in a standard 14-pin auto-insertable DIP and a space saving
surface mount 14-pin SOIC.
TABLE 1: PART NUMBER SPECIFICATIONS
PART NUMBER DELAY INPUT RESTRICTIONS
DIP-14
3D7324
-6 -6 -6
-8 -8 -8
-10 -10 -10
-15 -15 -15
-20 -20 -20
-25 -25 -25
-30 -30 -30
-40 -40 -40
-50 -50 -50
-100 -100 -100
-200 -200 -200
-500 -500 -500 -500
-1000 -1000 -1000 -1000
-6000 -6000 -6000 -6000
NOTES: Any delay between 10 and 6000 ns not shown is also available. 2006 Data Delay Devices
DIP-14
3D7324G
SOIC-14
3D7324D
PER LINE
(ns)
6 ± 1.0
8 ± 1.0
10 ± 1.0
15 ± 1.0
20 ± 1.0
25 ± 1.0
30 ± 1.0
40 ± 1.0
50 ± 1.0
100 ± 2.0
200 ± 4.0
Max Operating
Frequency
55.5 MHz 125.0 MHz 9.0 ns 4.0 ns
41.6 MHz 111.0 MHz 12.0 ns 4.5 ns
33.3 MHz 100.0 MHz 15.0 ns 5.0 ns
22.2 MHz 100.0 MHz 22.5 ns 5.0 ns
16.7 MHz 100.0 MHz 30.0 ns 5.0 ns
13.3 MHz 83.3 MHz 37.5 ns 6.0 ns
11.1 MHz 71.4 MHz 45.0 ns 7.0 ns
8.33 MHz 62.5 MHz 60.0 ns 8.0 ns
6.67 MHz 50.0 MHz 75.0 ns 10.0 ns
3.33 MHz 25.0 MHz 150.0 ns 20.0 ns
1.67 MHz 12.5 MHz 300.0 ns 40.0 ns
500 ± 10.0
1000 ± 20
6000 ±120
Absolute Max
Oper. Freq.
0.67 MHz 5.00 MHz 750.0 ns
0.33 MHz 2.50 MHz 1500.0 ns
0.05 MHz 0.42 MHz 9000.0 ns
PIN DESCRIPTIONS
I1 Delay Line 1 Input
I2 Delay Line 2 Input
I3 Delay Line 3 Input
I4 Delay Line 4 Input
O1 Delay Line 1 Output
O2 Delay Line 2 Output
O3 Delay Line 3 Output
O4 Delay Line 4 Output
VDD +5 Volts
GND Ground
N/C No Connection
Min Operating
Pulse Width
Absolute Min
Oper. P.W.
1
14
2
13
3
12
4
11
5
10
6
7
SOIC
VDD
N/C
O1
N/C
O2
O3
9
O4
8
Doc #06016 DATA DELAY DEVICES, INC. 1
5/10/2006 3 Mt. Prospect Ave. Clifton, NJ 07013
3D7324
APPLICATION NOTES
OPERATIONAL DESCRIPTION
The 3D7324 quadruple delay line architecture is
shown in Figure 1. The individual delay lines are
composed of a number of delay cells connected
in series. Each delay line produces at its output
a replica of the signal present at its input, shifted
in time. The delay lines are matched and share
the same compensation signals, which minimizes
line-to-line delay deviations over temperature and
supply voltage variations.
INPUT SIGNAL CHARACTERISTICS
The Frequency and/or Pulse Width (high or low)
of operation may adversely impact the specified
delay accuracy of the particular device. The
reasons for the dependency of the output delay
accuracy on the input signal characteristics are
varied and complex. Therefore a Maximum and
an Absolute Maximum operating input
frequency and a Minimum and an Absolute
Minimum operating pulse width have been
specified.
OPERATING FREQUENCY
The Absolute Maximum Operating Frequency
specification, tabulated in Table 1, determines
the highest frequency of the delay line input
signal that can be reproduced, shifted in time at
the device output, with acceptable duty cycle
distortion.
The Maximum Operating Frequency
specification determines the highest frequency of
the delay line input signal for which the output
delay accuracy is guaranteed.
To guarantee the Table 1 delay accuracy for
input frequencies higher than the Maximum
Operating Frequency, the 3D7324 must be
tested at the user operating frequency.
Therefore, to facilitate production and device
identification, the part number will include a
custom reference designator identifying the
intended frequency of operation. The
programmed delay accuracy of the device is
guaranteed, therefore, only at the user specified
input frequency. Small input frequency variation
about the selected frequency will only marginally
impact the programmed delay accuracy, if at all.
Nevertheless, it is strongly recommended that
the engineering staff at DATA DELAY
DEVICES be consulted.
OPERATING PULSE WIDTH
The Absolute Minimum Operating Pulse
Width (high or low) specification, tabulated in
Table 1, determines the smallest Pulse Width of
the delay line input signal that can be
reproduced, shifted in time at the device output,
with acceptable pulse width distortion.
The Minimum Operating Pulse Width (high or
low) specification determines the smallest Pulse
Width of the delay line input signal for which the
output delay accuracy tabulated in Table 1 is
guaranteed.
To guarantee the Table 1 delay accuracy for
input pulse width smaller than the Minimum
Operating Pulse Width, the 3D7324 must be
tested at the user operating pulse width.
Therefore, to facilitate production and device
identification, the part number will include a
Temp & VDD
Compensatio
Doc #06016 DATA DELAY DEVICES, INC. 2
VDD
GND
Figure 1: 3D7324 Functional Diagram
O1
Dela
y
I1
O2
Dela
y
I2
O3
Dela
y
I3
O4
Dela
y
I4
5/10/2006 Tel: 973-773-2299 Fax: 973-773-9672 http://www.datadelay.com
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