Datasheet RMW130N03 Datasheet (ROHM)

Data Sheet

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4.5V Drive Nch MOSFET

RMW130N03

 Structure  Dimensions (Unit : mm)

Silicon N-channel MOSFET

PSOP8

Features

1) High Power package(PSOP8).

2) High-speed switching,Low On-resistance.

1pin mark

3) Low voltage drive(4.5V drive).

 Application

Switching

 Packaging specifications  Inner circuit

Package Taping

Type

Code TB
Basic ordering unit (pieces) 2500

RMW130N03 

 Absolute maximum ratings (Ta = 25C)

Parameter

Symbol Limits Unit
Drain-source voltage V
Gate-source voltage V

Drain current
Source current

(Body Diode)

Continuous I
Pulsed I
Continuous I
Pulsed I

Power dissipation P

DSS
GSS

D

DP

S

SP

D

30 V

20 V
13 A

*1

52 A

2.5 A

*1
*2

52 A

3.0 W

(1) Source
(2) Source
(3) Source
(4) Gate
(5) Drain
(6) Drain
(7) Drain
(8) Drain

Channel temperature Tch 150 C
Range of storage temperature Tstg 55 to 150 C

*1 Pw10s, Duty cycle1%
*2 MOUNTED ON 40mm×40mm Cu BOARD

(8)

(1)

(6)

(7)

(2) (3) (4)

1.27

5.0

0.50.5

(5)

5.0

6.0

0.4

(8) (7) (6) (5)

∗2

(1) (2) (3) (4)

∗1 ESD PROTECTION DIODE
∗2 BODY DIODE

0~0.1

0.22

0.9

∗1

 Thermal resistance

Parameter

Channel to Ambient Rth (ch-a) 41.7 C / W

* MOUNTED ON 40mm×40mm Cu BOARD

Symbol Limits Unit

*

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2011.03 - Rev.A

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Data Sheet

RMW130N03

 Electrical characteristics (Ta = 25C)

Parameter
Gate-source leakage I
Drain-source breakdown voltage V
Zero gate voltage drain current I
Gate threshold voltage V
Static drain-source on-state

resistance
Forward transfer admittance l Y

Input capacitance C
Output capacitance C
Reverse transfer capacitance C
Turn-on delay time t
Rise time t
Turn-off delay time t
Fall time t
Total gate charge Q
Gate-source charge Q
Gate-drain charge Q

*Pulsed

Symbol Min. Typ. Max. Unit

GSS

(BR)DSS

DSS

GS (th)

R

DS (on)

fs

iss

oss

rss

d(on)

r

d(off)

f

g
gs
gd

Conditions

--10 AVGS=20V, VDS=0V

30 - - V ID=1mA, VGS=0V

--1AVDS=30V, VGS=0V

1.0 - 2.5 V VDS=10V, ID=1mA

- 9.0 12.6 I

*

- 12.6 17.7 I

*

*

l7 - -SI

=13A, VGS=10V

D

m

=13A, VGS=4.5V

D

=13A, VDS=10V

D

- 650 - pF VDS=15V

- 310 - pF VGS=0V

- 85 - pF f=1MHz

- 11 - ns ID=6A, VDD 15V

*

*

- 35 - ns VGS=10V

*

*

- 30 - ns RL=2.5

*

*

-8-nsR

*

*

- 12 - nC ID=13A, VDD 15V

*

*

- 2.7 - nC VGS=10V

*

*

- 2.6 - nC

*

*

=10

G

Body diode characteristics (Source-Drain) (Ta = 25C)

Parameter

Forward Voltage V

*Pulsed

Symbol Min. Typ. Max. Unit

*

SD

- - 1.2 V Is=2.5A, VGS=0V

Conditions

2/6

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Data Sheet

RMW130N03

Electrical characteristic curves (Ta=25C)

0

1

2

3

4

5

6

7

8

9

10

11

12

13

0 0.2 0.4 0.6 0.8 1

VGS= 2.5V

Ta=25°C

Pulsed

VGS= 10V
VGS= 4.5V
VGS= 4.0V
VGS= 3.5V

VGS= 3.0V

Fig.1 Typical Output Characteristics(Ⅰ)

DRAIN CURRENT : I

D

[A]

DRAIN-SOURCE VOLTAGE : VDS[V]

0

1

2

3

4

5

6

7

8

9

10

11

12

13

0 2 4 6 8 10

VGS= 2.5V

VGS= 3.0V

VGS= 10V
VGS= 4.5V
VGS= 4.0V

VGS= 3.5V

Ta=25°C
Pulsed

Fig.2 Typical Output Characteristics(Ⅱ)

DRAIN-SOURCE VOLTAGE : VDS[V]

DRAIN CURRENT : I

D

[A]

Fig.3 Typical Transfer Characteristics

DRAIN CURRENT : I

D

[A]

GATE-SOURCE VOLTAGE : VGS[V]

Fig.4 Static Drain-Source On-State
Resistance vs. Drain Current(Ⅰ)

DRAIN-CURRENT : ID[A]

STATIC DRAIN-SOURCE ON-STATE

RESISTANCE : R

DS

(on)[mΩ]

Fig.5 Static Drain-Source On-State
Resistance vs. Drain Current(Ⅱ)

DRAIN-CURRENT : ID[A]

STATIC DRAIN-SOURCE ON-STATE

RESISTANCE : R

DS

(on)[mΩ]

Fig.6 Static Drain-Source On-State
Resistance vs. Drain Current(Ⅲ)

DRAIN-CURRENT : ID[A]

STATIC DRAIN-SOURCE ON-STATE

RESISTANCE : R

DS

(on)[mΩ]

0.001

0.01

0.1

1

10

100

0 1 2 3 4

VDS= 10V
Pulsed

Ta=125°C

Ta=75°C
Ta=25°C

Ta=-25°C

1

10

100

0.1 1 10 100

.

Ta=25°C
Pulsed

VGS= 4.5V
VGS= 10V

1

10

100

0.1 1 10 100

VGS= 10V
Pulsed

Ta=125°C
Ta=75°C
Ta=25°C
Ta=-25°C

1

10

100

0.1 1 10 100

VGS= 4.5V
Pulsed

Ta=125°C
Ta=75°C
Ta=25°C
Ta=-25°C

3/6

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Data Sheet

RMW130N03

Fig.7 Forward Transfer Admittance
vs. Drain Current

FORWARD TRANSFER ADMITTANCE : |Yfs| [S]

DRAIN-CURRENT : ID[A]

Fig.8 Reverse Drain Current
vs. Sourse-Drain Voltage

SOURCE CURRENT : Is [A]

SOURCE-DRAIN VOLTAGE : VSD [V]

0

5

10

15

20

25

30

35

40

45

50

0 5 10 15

ID= 13A

ID= 6.5A

Ta=25°C
Pulsed

Fig.9 Static Drain-Source On-State
Resistance vs. Gate Source Voltage

STATIC DRAIN-SOURCE ON-STATE

RESISTANCE : R

DS

(ON)[mΩ]

GATE-SOURCE VOLTAGE : VGS[V]

1

10

100

1000

10000

0.01 0.1 1 10 100

t

f

t

d(on)

t

d(off)

Ta=25°C

VDD= 15V
VGS=10V
RG=10Ω

Pulsed

t

r

Fig.10 Switching Characteristics

SWITCHING TIME : t [ns]

DRAIN-CURRENT : ID[A]

0

1

2

3

4

5

6

7

8

9

10

0 1 2 3 4 5 6 7 8 9 10 11 12 13

Ta=25°C
VDD= 15V
ID= 13A
RG=10Ω

Pulsed

Fig.11 Dynamic Input Characteristics

GATE-SOURCE VOLTAGE : V

GS

[V]

TOTAL GATE CHARGE : Qg [nC]

10

100

1000

10000

0.01 0.1 1 10 100

C

iss

C

rss

Ta=25°C
f=1MHz

VGS=0V

C

oss

Fig.12 Typical Capacitance
vs. Drain-Source Voltage

DRAIN-SOURCE VOLTAGE : VDS[V]

CAPACITANCE : C [pF]

0.1

1

10

100

0.01 0.1 1 10 100

VDS= 10V
Pulsed

Ta=125°C
Ta=75°C
Ta=25°C
Ta=-25°C

0.01

0.1

1

10

100

0 0.5 1 1.5

VGS=0V
Pulsed

Ta=125°C
Ta=75°C
Ta=25°C
Ta=-25°C

4/6

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Data Sheet

RMW130N03

0.01

0.1

1

10

100

1000

0.1 1 10 100

PW = 1ms

DC operation

Operation in this area is limited by R

DS(ON)

(VGS=10V)

PW=100us

PW=10ms

Ta = 25°C
Single Pulse
Mounted on a COPPER BOARD

Fig.13 Maximum Safe Operating Aera

DRAIN-SOURCE VOLTAGE : VDS[V]

DRAIN CURRENT : I

D

(A)

0.001

0.01

0.1

1

10

0.0001 0.001 0.01 0.1 1 10 100 1000

Ta = 25°C
Single Pulse : 1Unit
Rth(ch-a)(t) = r(t)×Rth(ch-a)
Rth(ch-a) = 41.7°C/W
<Mounted on a COPPER board>

Fig.14 Normalized Transient Thermal Resistance vs. Pulse Width

PULSE WIDTH : Pw(s)

NORMARIZED TRANSIENT THERMAL

RESISTANCE : r (t)

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Data Sheet

RMW130N03

S

%

V
V

V

S

 Measurement circuits

V

GS

R

G

Fig.1-1 Switching Time Measurement Circuit

V

GS

I

G(Const.)

Fig.2-1 Gate Charge Measurement Circuit

D.U.T.

D.U.T.

D

I

D

I

Pulse width

V

D

R

L

V

DD

50%

10%

GS
DS

10% 10%

t

d(on)

t

on

Fig.1-2　Switching Waveforms

V

G

V

D

R

L

V

DD

GS

QgsQ

Fig.2-2 Gate Charge Waveform

90%

50%

90% 90

t

d(off)

t

r

t

off

Q

g

gd

Charge

t

f

 Notice

This product might cause chip aging and breakdown under the large electrified environment. Please consider to design
ESD protection circuit.

6/6

2011.03 - Rev.A

Notes

Notice

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