ROHM BU94604BKV Technical data

A

USB Audio Decoder ICs

AAC/WMA/MP3
+SD Memory Card+iPod

BU94604BKV

●Description

BU94604BKV is AAC+WMA+MP3 decoder IC which contains USB host and SD card I/F,
audio DAC, system controller, regulator for internal CORE power supply.

For using of this LSI, it is necessary to become a licensee of Apple Inc. regarding "Made for iPod/iPhone/iPad License".

●Features

1) USB2.0 Full Speed host I/F function contained.

2) Protocol conversion from I2C to USB HID or from USB HID to I2C.

3) SD card I/F function contained.

2

4) I

C I/F function contained.

5) FAT analysis function contained.

6) MP3 decode function contained. (available for MPEG1, 2 and 2.5, Layer 1, 2 and 3)

7) WMA decode function contained. (available for WMA9 standard and not available for DRM)

8) AAC decode function contained. (available for MPEG4 AAC-LC and not available for DRM)

9) Sample Rate Converter contained.

10) System Controller contained.

11) LED Controller contained.

12) KEY matrix Controller contained.

13) Stand Alone mode contained.

14) External processor can control. (Slave mode)

15) Audio DAC contained.

16) Sound Effect function contained.

17) Digital Audio Out(I

18) File Name, Folder Name Sorting.

19) ID3TAG and WMATAG and AACTAG Analysis.

20) Reading a specified file data is possible from USB memory.

21) LUN is selectable.

22) Regulator for internal CORE power supply contained.

23) VQFP64pin(0.5mm pitch)

●Applications

Audio products, etc.

2

S, S/PDIF) function contained.

No.12080EAT03

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●Absolute maximum ratings (Ta = 25℃)

Parameter Symbol Limits Unit Comment

Supply voltage(Analog, I/O) VDD1MAX

Input voltage VIN
Storage temperature range TSTG
Operating temperature range TOPR
Power dissipation *1 PD 750 mW

*1：In the case of use at Ta=25℃ or more, 7.5mW should be reduced per 1℃.

Radiation resistance design is not arranged.

●Operating conditions (Ta = 25℃)

Parameter Symbol Limits Unit Comment

Supply voltage(Analog, I/O) VDD1

-0.3～4.5

-0.3 ～ VDD1 + 0.3

-55～125 ℃

-40～85 ℃

3.0～3.6 V DVDDIO,VDD_PLL,

V DVDDIO, VDD_PLL,

V

Technical Note

DAVDD, AVDDC

DAVDD, AVDDC

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Technical Note

Ⅰ .Electrical characteristics

（Unless specified, Ta=25℃、VDD1=3.3V, DVSS=AVSSC=VSS_PLL=DAVSS=0V, XIN_PLL=16.9344MHz）

Parameter Symbol

MIN. TYP. MAX.

Limits

Unit Condition

<Total >
Circuit current (VDD1 USB1) IDD1USB1

- 65 80

mA *1 When USB memory is

played.
Circuit current (VDD1 SD1) IDD1SD1 - 35 50 mA *1 When SD card is played.
<Digital block>
H-Level input voltage VIH VDD1*0.7 － VDD1 V *3
L-Level input voltage
H-Level output voltage1
L-Level output voltage1
H-Level output voltage2
L-Level output voltage2
H-Level output voltage3
L-Level output voltage3
H-Level output voltage4
L-Level output voltage4

VIL DVSS － VDD1*0.3 V *3

VOH1 VDD1-0.4 － VDD1 V IOH=-1.6mA, *4

VOL1 0 － 0.4 V IOL=1.6mA. *4

VOH2 VDD1-0.4 － VDD1 V IOH=-3.6mA, *5

VOL2 0 － 0.4 V IOL=3.6mA, *5

VOH3 VDD1-0.4 － VDD1 V IOH=-0.6mA, *6

VOL3 0 － 0.4 V IOL=0.6mA, *6

VOH4 VDD1-1.0 － VDD1 V IOH=-0.6mA, *7

VOL4 0 － 1.0 V IOL=0.6mA, *7

<USB-HOST >

H-Level input

VIHUSB VDD1*0.6 － VDD1 V *8

voltage

L-Level input voltage

VILUSB AVSSC － VDD1*0.3 V *8
Output impedance(H) ZOH 22.0 45.0 60.0 Ω *8
Output impedance(L) ZOL 22.0 45.0 60.0 Ω *8

H-Level output

VOHUSB VDD1-0.5 － VDD1 V *8

voltage

L-Level output voltage

VOLUSB 0 － 0.3 V *8
Rise/Fall time Tr/Tf － 11 － ns *8, Output capacity 50pF
Voltage of crossing point VCRS － VDD1/2 － V *8, Output capacity 50pF
Range of differential input VDIFF 0.8 － 2.5 V *8
Differential input sensitivity VSENS 0.2 － － V *8
Pull-down resistance RPD 14.25 15.0 24.8 kΩ *8
<Audio DAC>
Distortion rate THD － 0.02 － % 1kHz, 0dB, sine, *9
Dynamic range DR － 88 － dB 1kHz, -60dB, sine, *9
S/N ratio S/N － 96 － dB *9
Max output level VSMAX － 0.92 － Vrms 1kHz, 0dB, sine, *9

*1 3.3V system I/O, Analog Power supply(VDD1), 1kHz, 0dB, sine-wave playing
*3 1-7, 9-17, 19-20, 25-26, 28-30, 40, 49-52, 56, 58-61, 63 pin
*4 8, 10-11, 14-16, 48-55 pin
*5 13 pin
*6 21-23, 26 pin
*7 41 pin
*8 33, 34 pin
*9 44, 46 pin

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Ⅱ . Block diagram

LED_ERROR/TEST9

LED_PLAY/TEST10

LED_PSD/TEST11

LED_PUSB/TEST12

LED_ACCESS/LRCK

/SPDIF

LED_RANDOM/BCK

LED_REPEAT/DATA

TEST13

DVDD_M1

TEST14

TEST15

TEST16

TEST17

DVSS

TMODE

DVDDIO

49

50

51

52

53

54

55

56

57

58

59

60

61

62

63

64

USB_DP

AVSSC

43 42 41 4047 46 45 4448

DAVSS

VSS_PLL

XOUT_PLL

XIN_PLL

TEST_PLL

39 38 37 36 35 34 33

VDD_PLL

VOREFI

PLL

REXTI

USB
PHY

DAVDD

LDACO

VCDACO

RDACO

AMUTE

Audio DAC

USB

Sound Effecter

Controller

FAT

File system

AAC / WMA /

LDO

MP3

Decoder

SD I/F

Controller

System

Controller

12345678910111213141516

IRPTO

TEST2

RESETX

SEL_SLAVE

SEL_MP3

SEL_DOUT

SEL_VOL

SEL_APLAY

SEL_UTPKT

Block diagram

MCHNG

KEY_ROW1/

BUSY

KEY_ROW2/

I2C I/F

Controller

KEY_ROW3/SCL

KEY_ROW4/SDA

KEY_COL1/A0

KEY_COL2/A1

Technical Note

USB_DM

32

AVDDC

31

ATEST1

30

TEST8

29

TEST7

28

TEST6

27

DVDD_M2

26

TEST5/CLKOUT12

25

TEST4

DVSS

24

SD_CS

23

22

SD_DI

21

SD_CLK

SD_DO

20

SD_CON

19

DVDDIO

18

17

TEST3

SEL_SMAN

KEY_COL3/

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Ⅲ . Description of Terminals

STAND ALONE MODE(MODE1) SLAVE MODE(MODE2,MODE3)

Pin

Signal Name

No.

1 RESETX A I PU

2 SEL_SLAVE B I PU(*1) H: STAND ALONE, L:SLAVE ←

3 SEL_MP3 B I PU(*1)

4 SEL_DOUT B I PU(*1)

5 SEL_VOL B I PU(*1)

6 SEL_APLAY B I PU(*1)

7 SEL_UTPKT B I PU(*1)

8 IRPTO B O -

9 TEST2 - I PU

10 KEY_ROW1 B I PU KEY Input ROW1 MCHNG O - Music change Output

11 KEY_ROW2 B I PU KEY Input ROW2 BUSY O -

12 KEY_ROW3 B I PU KEY Input ROW3 SCL I - I2C I/F Clock Input

13 KEY_ROW4 B I PU KEY Input ROW4 SDA I/O -

14 KEY_COL1 B O - KEY Input COLUMN1 A0 I -

15 KEY_COL2 B O - KEY Input COLUMN2 A1 I -

16 KEY_COL3 B O - KEY Input COLUMN3 SEL_SMAN I PU(*1) H: MODE2, L: MODE3

17 TEST3 B I PU

18 DVDDIO - - -

19 SD_CON B I - SD I/F (*2) ←
20 SD_DO B I - SD I/F (*2) ←
21 SD_CLK B O - SD I/F ←
22 SD_DI B O - SD I/F ←
23 SD_CS B O - SD I/F ←
24 DVSS - - - Connect to GND ←

25 TEST4 - I PU

26 TEST5 - I PU

27 DVDD_M2 - - - Connect to 57PIN ←

28 TEST6 - I -

29 TEST7 - I -

30 TEST8 - I -

31 ATEST1 - O - OPEN (for TEST) ←

32 AVDDC - - -

33 USB_DM C I/O - USB DATA- ←
34 USB_DP C I/O - USB DATA+ ←
35 AVSSC - - - Connect to GND ←

36 REXTI D O -

37 VOREFI - O - OPEN (for TEST) ←

38 VDD_PLL - - -

39 TEST_PLL - I - OPEN (for TEST) ←
40 XIN_PLL E I - X'tal Input 16.9344MHz ←

I/O
Cir

I/O

Pull-Up/

Down

Function Signal Name I/O

H: Release RESET,
L: RESET

H: PLAY MP3 ONLY,
L: PLAY MP1,MP2 and MP3

H: ANALOG DAC Output,
L: Digital Output

H: Volume control valid,
L: Volume control invalid

H: Auto Play OFF ,
L: Auto Pla

H: Normal Operation
L: USB Test Packet Output

Device (Have 2 configuration
or more) connection’s
interruption output terminal

Pull-up to 3.3V system power
supply (for TEST

Pull-up to 3.3V system power
supply (for TEST

Connect to 3.3V
System Power Suppl

Pull-up to 3.3V system power
supply (for TEST
Pull-up to 3.3V system power
supply (for TEST

Pull-up to 3.3V system power
supply (for TEST

Pull-up to 3.3V system power
supply (for TEST

Pull-up to 3.3V system power
supply (for TEST

Connect to 3.3V
System Power Suppl

Connect Bias Resistor
to GND

Connect to 3.3V
System Power Suppl

CLKOUT12(*3)

Pull-Up/

Down

←

←

←

←

←

←

←

←

←

←

←

I/O

PU(*3) 12MHz CLK Output.

(*3)

←

←

←

←

←

←

Technical Note

Function

Command
Operation Busy Fla

I2C I/F Data
Input/Output
I2C I/F Slave
Address Set0
I2C I/F Slave
Address Set1

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41 XOUT_PLL E O - Connect to X'tal 16.9344MHz ←
42 VSS_PLL - - - Connect to GND ←
43 DAVSS - - - Connect to GND ←
44 RDACO F O - Audio DAC Line Output Rch ←

45 VCDACO F O -

Audio DAC
Reference Voltage Output

46 LDACO F O - Audio DAC Line Output Lch ←

47 DAVDD - - -

48 AMUTE G O -

Connect to 3.3V
System Power Suppl

Audio Mute Output

H:Mute Cancel, L:Mute

49 LED_ERROR B O - Error LED Output TEST9 I PU

50 LED_PLAY B O - Play LED Output TEST10 I PU

51 LED_PSD B O - Play SD Card LED Output TEST11 I PU

52 LED_PUSB B O - Play USB LED Output TEST12 I PU

53(*3) LED_ACCESS B O - Memory Access LED Output

LRCK

/SPDIF(*4)

54(*3) LED_RANDOM B O - Random Play LED Output BCK(*4)

55(*3) LED_REPEAT B O - Repeat Play LED Output DATA(*4)

56 TEST13 - I PU

57 DVDD_M1 - - -

Pull-up to 3.3V system power
supply (for TEST

Connect to
Bypass Condense

I/O

(*4)

I/O

(*4)

I/O

(*4)

58 TEST14 F I - Connect to GND ←

59 TEST15 - I -

60 TEST16 - I -

61 TEST17 - I -

Pull-up to 3.3V system power
supply (for TEST

Pull-up to 3.3V system power
supply (for TEST

Pull-up to 3.3V system power
supply (for TEST

62 DVSS - - - Connect to GND ←
63 TMODE H I - Connect to GND ←

64 DVDDIO - - -

Connect to 3.3V
System Power Suppl

*1 When L is input, Pull-UP turns OFF.
*2 When SD I/F is disused, pull-up to 3.3V system power supply.
*3 Enabled/Disabled can be selected using commands.
This pin becomes output and pull-up is OFF, only when 12MHz clock output is enable.
*4 In STAND ALONE MODE (MODE1),
When ANALOG DAC output is selected (SEL_DOUT=H), LED output is enabled.
When the Digital output is selected (SEL_DOUT=L), the I2S format audio output is enabled.

In SLAVE MODE (MODE2, MODE3),

When the ANALOG DAC output is selected (SEL_DOUT=H), these pins are TEST terminals.

When the Digital output is selected (SEL_DOUT=L), you can select I2S format audio output or digital audio

interface output (SPDIF).

See Chapter Ⅴ.4 for further information.

Technical Note

←

←

←

Pull-up to 3.3V system
power suppl
Pull-up to 3.3V system
power suppl
Pull-up to 3.3V system
power suppl
Pull-up to 3.3V system
power suppl

PU(*4)

PU(*4) I2S Output Bit Clock

PU(*4) I2S Output LR DATA

I2S Output
LR Clock /
SPDIF Output

←

←

←

←

←

←

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Ⅳ. Terminal equivalent circuit diagram

A B C D

DVDDIO

DVDDIO

DVDDIO

DVDDIO

Technical Note

D
P

D
M

AVDDC

AVDDC

15KΩ

DVSSIO

DVSSIO

15KΩ

AVSSCAVSSC

AVSSC

E F G H

VDD_PLL

XIN

VSS_PLL

VDD_PLL

XOUT

VSS_PLL

DAVDD

DAVSS

DVDDIO

DVSSIO

DVDDIO

DVSSIO

I/O terminal equivalent circuit diagram

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X

X

V. I/O Signal Specifications

V.1 Clock and reset

Clock

Signal name I/O Function Remarks

XIN_PLL I

XOUT_PLL O

Reset

Signal name I/O Function Remarks

RESETX I System reset input terminal

To disable a reset signal, continue L input for more than 5 us after all of the supply voltage reach the specified value and
clock input from the oscillation I/O terminal becomes stable. (See Figure V.1.)

Power
supply

XIN_PLL

RESETX

’tal (16.9344 MHz) connection

input terminal

’tal (16.9344 MHz) connection

terminal

Oscillation stabilization

standby time

Technical Note

clk

f

Clock frequency

Reset L interval

V.2 SEL_SLAVE

MODE1/MODE2, 3 selection input signal

Signal name I/O Function Remarks

SEL_SLAVE I Selects MODE1 or MODE2, 3. H: MODE1, L: MODE2, 3

V.3 SEL_MP3

Signal name I/O Function Remarks

SEL_MP3 I MPEG Audio Layer selection

tRSTX

Figure V.1 Reset Timing

Specification

Item Symbol

f

CLK

t

RSTX

min typ max

16.9302 16.9344 16.9386 MHz

5 - - us

Unit Remarks

SEL_SLAVE selects MODE1 (STAND ALONE MODE) or MODE 2/3 (SLAVE MODE).
By selecting SEL_SLAVE, SLAVE mode terminal setting shown in Table II.2 is enabled.
SEL_SLAVE is set only at power ON. Note that change of selection after power ON is ignored.

MPEG Audio Layer 1, 2, 3 play selection signal

H: Can play MP3 only. L: Can play MP1, MP2 and
MP3.

SEL_MP3 allows you to select the layer of the MPEG audio to be played. When enabling all the files having mp1,
mp2 or mp3 as the file extension to be played, enter L. When enabling mp3 only, enter H.
SEL_MP3 is set only at power ON. Note that change of election after power ON is ignored.

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V.4 SEL_DOUT

Audio output selection signal

Signal name I/O Function Remarks

SEL_DOUT I Audio output selection H: Line output, L: I2S 3 lines serial output/SPDIF

This SEL_DOUT selects audio output signal.
Table V4.1 “Audio output” shows the audio outputs for each MODE.
Also table V4.2 ”I2S_fs” shows the I2S output formats for each MODE.
For command, see Chapter VI.
"TEST terminal" needs to be pull-up to 3.3V power supply.

Technical Note

TableV.4.1 Audio output

Pin No.

44 Line Out Rch O OF
46 Line Out Lch O OF
53 LED_ACCESS O OF
54 LED_RANDOM O OF
55 LED_REPEAT O OF

V.5 SEL_VOL

MODE1 MODE2,3

SEL_DOUT=H SEL_DOUT=L SEL_DOUT=H

function I/O PU function I/O PU function I/O PU function I/O PU function I/O PU

HiZ O OFFLine Out Rch O OFF HiZ O OFF HiZ O OFF
HiZ O OFFLine Out Lch O OFF HiZ O OFF HiZ O OFF

I2S LR CLOCK O OFFTEST terminal I ON I2S LR CLOCK O OFF SPDIF O OFF

I2S BIT CLOCK O OFFTEST terminal I ON I2S BIT CLOCK O OFF TEST terminal I OFF

I2S LRDATA O OFFTEST terminal I ON I2S LRDATA O OFF TEST terminal I OFF

SEL_DOUT=L

I2S SPDIF　ON

Table V.4.2 I2S_fs

MODE1 32fs

MODE2/3 Can select 32fs, 48fs, 64fs by command.

SEL_DOUT is set only at power ON. Note that change of selection after power ON is ignored.

Sound volume operation selection signal

Signal name I/O Function Remarks

SEL_VOL I Sound volume operation

H: Sound volume operation enabled, L: Sound volume
operation disabled

SEL_VOL selects whether sound volume operation is to be enabled or disabled.
Sound volume operation is enabled when SEL_VOL=H.
Initial value of audio output is -24.1dB at power ON.
Sound volume operation is disabled when SEL_VOL=L. Audio output is fixed to 0dB.
Figure V.5 shows the relationship between audio output and sound volume step.
SEL_VOL is set only at power ON. Note that change of selection after power ON is ignored.

0

*PU・・・Pull-Up

-10

-20

-30

-40

-50

 -

Audio output (dB)

-60

Initial value: -24.1 dB
(when SEL_VOL=H)

02468101214161820222426283032

Volume ste

Figure V.5 Volume Step Function

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V.6 SEL_APLAY

Auto play selection signal at power ON/device recognition

Signal name I/O Function Remarks

SEL_APLAY I

SEL_APLAY selects whether the audio data in the memory is to be automatically played when a memory device
(USB memory or SD card) is inserted at power ON or when the system recognizes the memory device inserted.
SEL_APLAY can be selected only in MODE1. Since selection of SEL_APLAY is ignored in MODE2/3, select it
from Pull-up. When MODE2/3 is selected, audio data is halted after the system recognizes a device.

V.7 SEL_UTPKT

USB test packet

Signal name I/O Function Remarks

SEL_UTPKT I USB test packet send H: Disabled, L: USB test packet send

A test packet signal is output from USB_DP terminal or USB_DM terminal when L is set to SEL_UTPKT at power
ON.
Once enabled, SEL_UTPK keeps that state regardless of operation modes and sends out a test packet.
A test packet signal is continuously output until power turns OFF. Use SEL_UTPKT when evaluating the USB
terminal. In other cases, use it from Pull-up.

V.8 Audio output

Audio output

Signal name I/O Function Remarks

LDACO O Lch audio line output -

RDACO O Rch audio line output -

These signals are decoded MP3 music audio data line outputs.
They turn ON when the line output is selected by SEL_DOUT terminal.

V.9 MUTE control output

Audio MUTE

Signal name I/O Function Remarks

AMUTE O Audio mute control terminal H: At audio output, L: At mute

This is a control terminal to mute audio output at power ON or FF/FB (silence).
This terminal outputs H at audio output and L at mute.
Figure Ⅴ.9 shows the operation waveform.

Auto play selection signal at
device recognition

Technical Note

H: Stop after recognizing device, H: Play after
recognizing device

Figure V.9 Waveform at Audio Mute

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V.10 KEY input format

3x4 matrix command input

Signal name I/O Function Remarks

KEY_ROW1 I

KEY_ROW2 I -

KEY_ROW3 I -

KEY_ROW4 I -

KEY_COL1 O -

KEY_COL2 O -

KEY_COL3 O -

Configure a circuit for the matrix signals terminals for KEY commands as shown in the applied circuit diagram
V.10.
The operation corresponding to the key pressed over the circuit is performed.
Details of each operation are explained in Chapter VI.2.

Technical Note

-

KEY matrix I/O signal

REPEAT RANDOM CHG_DEV+10

VOL+ FOL- FOL+VOL-

V.11 I2C interface format

I2C serial interface

Signal name I/O Function Remarks

SCL I I2C interface clock input -

SDA I/O I2C interface data I/O -

A0 I Slave address selection terminal Slave address [0] bit setting terminal

A1 I Slave address selection terminal Slave address [1] bit setting terminal

This is an I2C serial interface terminal. By inputting L to SEL_SLAVE terminal, the interface terminal becomes
enabled.
The terminal supports slave I2C operation.

V.11.1 I2C protocol

When I2C bus is in IDLE, SDA and SCL are set to H by the external Pull-up resistance. When starting
communications, the master sets SDA to L while SCL is set to H (Start condition). When ending communications,
the master sets SDA to H while SCL is set to H (Stop condition). During transfer, SDA is changed only when SCL
is set to L. Figure V.11.1 shows Start condition, Stop condition of I2C.

KEY_

ROW1

KEY_

ROW2

PLAY/

PAUSE

STOP

KEY_

ROW3

KEY_

ROW4

FFFB

KEY_

COL1

Figure V.10 KEY Matrix Applied Circuit Diagram

KEY_

COL2

KEY_

COL3

SCL

SDA

Start or
Repeated start
condition

12

MSB

8

LSB ACK

9 1

ACK

9

Stop or
Repeated start
condition

Figure V.11.1 I2C start, stop condition

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V.11.2 Slave address

An I2C bus slave address corresponds to the 7-bit addressing mode. As shown in Table V.11.2, you can select
the slave address using input of A0 terminal and A1 terminal. Figure V.11.2 shows the slave address transfer
format.

S A6 A5 A4 A3 A2 A1 A0 R/W ACK

Start

condition

R / W = Read / Write Pulse

ACK = Acknowledge

Slave Address

Figure V.11.2 Slave Address Transfer Format

Table V.11.2 Settable Slave Addresses

sent by

slave

Technical Note

MSB

A6

A5 A4 A3 A2

A1

terminal

LSB

A0

terminal

1 0 0 0 0 0 0
1 0 0 0 0 0 1
1 0 0 0 0 1 0
1 0 0 0 0 1 1

V.11.3 Write protocol from master

To send a master command using an I2C bus, follow the transfer protocol shown in Figure V.11.3. For details on
each command, see Chapter VI.

S Slave Address A Data(8bit)R/W A Data(8bit) A Data(8bit) PA/A

"0"(write)

From Master to Slave

From Slave to Master

A = Acknowledge(SDA low)
A = No Acknowledge(SDA high)
S = Start Condition
P = Stop condition

Figure V.11.3 Command send protocol

V.11.4 Read protocol to master

To send reception data using an I2C bus from the slave to the master, follow the transfer protocol shown in Figure
V.11.4.1. First, transfer the status read command (step1). Then, input SCL clock of required bytes in step 2 to
read the status.
When the device is BUSY at reception of device status or memory data, the I2C bus may possibly be occupied by
the device during BUSY. This LSI transfers the bus to the master so as not to generate such bus occupation.
However, as a BUSY state still exists inside of the system, appropriate data may not be transferred during BUSY.
Therefore, the first byte of transfer data (Step2) is used to judge the transfer data is enabled/disabled. When
specifying addresses from the master to the slave and the first byte of the transfer data immediately after data
transfer is required is 0x00, transfer data from the slave is enabled. If the first byte is 0xFF, it shows the BUSY
state. Therefore, the transfer data should be disabled. If this happens, retry command transfer at Step 1 to read
out the status.
Figure V.11.4.2 shows the relationship between the transfer data and BUSY.
* For further information on BUSY, see Chapter V.17.

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I2C

Step1

S Slave Address A Data(8bit)R/W A Data(8bit) PA/A

Step2

S Slave Address A Data(8bit)R/W A Data(8bit) PA/A

From Master to Slave

From Slave to Master

"0"(write)

"1"(read)

A = Acknowledge(SDA low)
A = No Acknowledge(SDA high)
S = Start Condition
P = Stop condition

Figure V.11.4.1 Status Reception Protocol

Step1 command S Slave Address A 0xFF A Data(8bit) PA/AData(8bit) AR

Technical Note

Data(8bit) A

BUSY

Step1 command S Slave Address A 0x00 A Data(8bit) PA/AData(8bit) AR

Dummy byte for Busy

Dummy byte for Busy

Figure V.11.4.2 Relationship between Transfer Data and BUSY

V.11.5 I2C Bus line electrical specification and timing

SDA and SCL bus-line characteristic (Unless specified, Ta=25℃, Vcc=3.3V)

Parameter Code Min. Max. Unit

1 SDA, SCL H input voltage VIH VDD*0.7 VDD V

2 SDA, SCL L input voltage VIL DVSS VDD*0.3 V

3 SDA H output voltage VOH VDD-0.4 VDD V

4 SDA L output voltage VOL 0 0.4 V

5 SCL clock frequency fSCL 0 400 kHz

Bus-free-time between "Stop" condition and

6

"Start" condition

Hold time for "Start" condition

7

After this, the first clock pulse is generated.

tBUF 1.3 － us

tHD;STA 0.6 － us

8 LOW status hold-time of SCL clock tLOW 1.3 － us

9 HIGH status hold-time of SCL clock tHIGH 0.6 － us

10 Data-hold-time tHD;DAT 0＊ － us

11 Date-setup-time tSU;DAT 100 － ns

12 Rising time of SDA and SCL signal tR 20+0.1*Cb 300 ns

13 Fall time of SDA and SCL signal tF 20+0.1*Cb 300 ns

14 Setup time of "Stop" condition tSU;STO 0.6 － us

15 Capacitive load of each bus-line Cb － 400 pF

The above-mentioned numerical values are all the values corresponding to V
*To exceed an undefined area on falling edged of SCL, transmission device should internally offer the hold-time of 300ns or more for SDA signal (V
signal).
Because the "Repeated Start" condition to send "Start" condition without sending "Stop" condition doesn't correspond, after sending "Start" condition, always
send "Stop" condition.
Neither terminal SCL nor terminal SDA correspond to 5V tolerant.

IH min

and V

IL max

level.

IH min

of SCL

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SDA

t

BUF

SCL

t

LOW

t

R

t

HD;STA

SP

t

HD;DAT

t

HIGH

Figure V.11.5 Timing chart

V.12 I2S format

I2S serial audio interface

Signal name I/O Function Remarks

LRCK O I2S Bit clock output (fs=44.1kHz) -

BCK O I2S Bit clock output -

DATA O I2S data output -

This is a serial audio interface terminal. By inputting L to SEL_DOUT terminal, the interface terminal becomes
enabled. When selecting the I2S serial audio output, the output format varies depending on MODE. *See
Chapter Ⅴ.4. MODE2 allows you to select 32fs, 48fs or 64fs. *See Chapter V.4.
Figures V.12.1. V12.2 and V.12.3 show the I2S format to be output.

t

F

t

SU;DAT

t

SU;STO

Technical Note

P

LRCK

BCK(32fs)

DATA

Left Channel

0 15 14 13 12 11 10 9 8 7 6 5 4 3 2 11 0

Right Channel

15

Figure V.12.1 I2S Output Timing (32fs)

LRCK Left Channel Right Channel

BCK(48fs)

DATA

15 14 12 11 10 9 8 7 6 5 4 3 2 1 0 15 1413

Figure V.12.2 I2S Output Timing (48fs)

LRCK

BCK(64fs)

DATA

13 1215 14 11 8 710 9 6 3 25 4 1 0 13 1215 14

Left Channel Right Channel

Figure V.12.3 I2S Output Timing (64fs)

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V.13 SPDIF format

Digital audio interface

Signal name I/O Function Remarks

SPDIF O Digital audio output -

SPDIF output becomes enabled by setting SEL_DOUT terminal to L and setting this condition using the I2C
command. *See Chapter V.4.
Figure V.13 shows the digital audio signal output format.

Source code

Synchronous
preamble

Source code(4-31)

SPDIF output

Technical Note

034 1112 2728293031

Synchronous

preamble

Synchronous

preamble

0 0 0 0 0 0 0 0 1 0 1 1 0 1

all 0 Audio data(16bit)

(B pattern)

(M pattern)

(W pattern)

LSB MSB

Figure V.13 SPDIF Output Format

V U C P

A sub-frame of SPDIF is composed of synchronous preamble, 16-bit audio data, V bit (validity flag), U bit (user
data), C bit (channel status) and P bit (parity bit).
Output rate is fixed to 1X speed.
SPDIF outputs synchronous preamble (source code 0-3) as it is and others (source code 4-31) as bi-phase output.
It outputs L while the operation is stopped.
Synchronous preamble and C bit use 32 frames (≈4.4ms) as one cycle. Table V.13.1 and Table V.13.2 show
these formats. V bit is fixed to L. U bit uses 98 frames (≈13.3ms) as one cycle.

Table V.13.1 Synchronous Preamble Pattern

L0 R0 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5

0 B W M W M W M W M W M W

1 M W M W M W M W M W M W

: : : : : : : : : : : : :

31 M W M W M W M W M W M W

Table V.13.2 C Bit Format

L0 R0 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5

0 0 0 0 0 0 0

1 0 0 1 0 0 0

2 0 0 0 0 0 0

3 0 0 1 0 0 1 0 0

4 0 0 0 0 0 0

5 0 0 0 0 0 0

: : : : : : :

31 0 0 0 0 0 0

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P bit is set to 1 if the number of “1s” of source codes 4-30 is odd, and set to 0 if the number is even. Therefore,
the number of source codes which turn to 1 for one data must be an odd value, SPDIF ends with L output and
preamble output always starts in the same direction.

V.14 USB I/F

USB I/O I/F

Signal name I/O Function Remarks

USB_DP I/O USB D+I/O terminal -

USB_DM I/O USB D-I/O terminal -

REXTI O

Differential signals of USB_DP and USB_DM enable communications with USB devices.
REXTI terminals become bias resistance connection terminals of the USB-PHY block.

V.15 SD I/F

SPI interface for SD memory card I/F

Signal name I/O Function Remarks

SD_CS O SPI chip select -

SD_CLK O SPI clock -

SD_DI O SPI data input -

SD_DO I SPI data output -

SD_CON I

These I/F enable communication with SD memory cards through SD memory card slots.
Since SD memory card slot requires detecting insertion of SD memory card, use of slot equipped with SD memory
card detecting terminal and connection to SD_CON terminal are required.

SD_CON terminal is pulled up within the device and detects SD memory card connection by L input.

V.16 MCHNG

Playing sound tune number detection output

Signal name I/O Function Remarks

MCHNG O

This signal outputs change of file to be played during playing MP3 file in the memory device.
MCHNG correctly outputs "H" during MP3 decode sequence, outputs "L" during "STOP" status.

V.17 BUSY

BUSY state detection output

Signal name I/O Function Remarks

BUSY O

This signal outputs to indicate that this LSI is in BUSY.
BUSY signal analyzes commands from the master and outputs H until the operation is executed.
This LSI ignores command input during BUSY. However, only the ABORT and STOP commands can be
accepted even during BUSY, which can be executed. *See Chapter V.11.

Technical Note

Table V.13.3 U Bit Format

L0 R0 L1 R1 L2 R2 L3 R3 L4 R4 L5 R5

0 0 0 0 0 0 0 0 0 0 0 0 0

1 0 0 0 0 0 0 0 0 0 0 0 0

2 1 0 0 0 0 0 0 0 0 0 0 0

3 1 0 0 0 0 0 0 0 0 0 0 0

: : : : : : : : : : : : :

97 1 0 0 0 0 0 0 0 0 0 0 0

USB bias resistance connection
terminal

SD card connect detection
terminal

Music tune number change
detection output signal

BUSY state detection output
signal

Connect resistance of 12kΩ  1% to GND.

H: Not detecting SD card connection.
L: Detecting SD card connection.

H: Playing, L: Tune completed/stopped

H: Busy, L: Not Busy

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V.18 IRPTO

CONFIG outputs it for two more device connection state detection.

Signal name I/O Function Remarks

IRPTO O

When the USB device is chosen, output it to show that the USB device that two USB CONFIGURATION
DESCRIPTOR or more has in this LSI is connected. The timing of an output is dependent on the connected USB
device.

V.19 TEST terminal

By the terminal setting of TEST15, TEST16 and TEST17, It is possible to following function.

TEST15 TEST16 TEST17 Function

H H H Full function effective

L L L Only WMA and MP3 can play-back. The AAC file is disregarded.

H L L The IRPTO function is invalidated.

USB CONFIG outputs it for two
more device connection state
detection.

H: Detection , L: Undetection.

Technical Note

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VI. Function/Operation Explanation

VI.1 File detection

VI.1.1 Function

· This function supports FAT16 and FAT32 file systems. (It does not support NTFS and FAT12.)

· The maximum number of playable files per folder

The number of files described above contains files other than AAC/WMA/MP3 and folders. If those non­AAC/WMA/MP3 files and folders exit within the folder and exceed the maximum number, all the AAC/WMA/MP3
files may not be played.

· Files less than 100 can be sorted by UNICODE in the FAT order within the folder. Files over 100 are sorted
in the FAT order. Also, the folders can be sorted in the same manner and those over 100 are sorted in the
FAT order.

· The searchable folder hierarchy is of 8 layers containing the root folder. Figure VI.1.1 shows an example of
memory layers.

Memory

Technical Note

Table VI.1.1 Maximum Number of Playable Files

Root folder Sub folder

FAT16 512 65534
FAT32 65536 65534

USB

Folder

Folder

Folder

Folder

File File

File

File File

Playable layers

FolderFolder

Folder

Folder

Folder Folder

Folder

Folder Folder

Folder File File File File File

Folder File File File

Folder

File

File File File File

File File

Unplayable layers

File

Figure VI.1.1 Example of Memory Layers

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