ROHM BU9409FV Technical data

A

Digital Sound Processors for FPD TVs

32bit Audio DSP

BU9409FV

●General Description

It is a digital audio sound processor used for thin TV. Digital signal processor is Rohm original DSP only for TV
sound signal processing, and it’s cost performance is excellent. Digital inputs are two lines. Output is digital output
corresponding to 2.1ch or play of sub-voice L/R signal.

●Features

■DSP Part

Data width: 32bit (Data RAM)
Quickest machine cycle:40.7ns (512fs,fs=48kHz)
Multiplier: 32 x 24 → 56bit
Adder: 32 + 32 → 32bit
Data RAM: 256 x 32bit
Coefficient RAM: 128 x 24bit
Sampling frequency: fs=48kHz
Master clock: 512fs

（24.576MHz,fs=48kHz）

■Input output I/F

2 stereo digital signal input port : 16/20/24bit (I2S,left-align,right-align)
2 stereo digital signal output port : 16/20/24bit (I2S,left-align,right-align), S/PDIF output

■Sound signal processing function for TV

Prescaler, DC cut HPF, channel mixer, P
TREBLE, pseudo stereo, surround, P
master volume, L/R balance, postscaler, output clipper, subwoofer output processing

2

（P

Volume，P2Bass，P2Treble are Rohm original sound effect functions.）

●Applications

Flat Panel TVs (LCD, Plasma)

2

Volume(Perfect Pure Volume),BASS,MIDDLE,

2

Bass, P2Treble, 7 band parametric equalizer,

No.12083EAT03

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Technical Note

●Absolute maximum rating（Ta = 25 ° C）

Item Symbol Rating Unit
Power-supply voltage VDD 4.5 V
Allowable dissipation Pd 700 (*1) mW
operating temperature range T
Storage temperature range T

*1 7mW is decreased for 1°C when using it with Ta=25°C or more.

Operation can’t be guaranteed.

-25～+85 °C

opr

-55～+125 °C

stg

●Operating condition（Ta = - 25 ～+85°C）

Item Symbol Rating Unit
Power-supply voltage VDD 3.0～3.6 V

* 1 It isn’t Radiation-proof designed for the product.

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Technical Note

●Electrical Characteristics(Digital serial)

=3.3V unless specified, Ta=25°C

V

DD

Rating value

Unit Terms Adaptive

V

=0～3.3V

IN

Hysteresis

Input voltage

Item Symb

ol
H Level voltage VIH 2.5 - - V *1,2,3
L Level voltage VIL - - 0.8 V *1,2,3

Min. Standard Max.

Input current II -1 - +1 µA

Pull-up resistor input L current IIL -150 -100 -50 µA VIN=0V *2

Pull-down resistor input H current IIH 35 70 105 µA VIN=3.3V *3

Output voltage

H Level voltage V
L Level voltage VOL - - 0.55 V IO=0.6mA *4

2.75 - - V IO=-0.6mA *4

OH

terminal

*1

SDA terminal
Output voltage

L Level voltage V

- - 0.4 V IO=3mA *5

OL

Adaptive terminal
*1 CMOS hysteresis input terminal
SCLI(8pin), SDAI(9pin), MODE(20pin)
*2 Pull-up resistor built-in CMOS hysteresis input terminal
LRCKI(2pin), SDATA1(3pin), SDATA2(4pin), MCLK(39pin), BCKI(40pin)
*3 Pull-down resistor built-in CMOS hysteresis input terminal
RESETX(5pin), MUTEX_SP(6pin), MUTEX_DAC(7pin), ADDR(21pin)

*4 CMOS output terminal
SPDIFO(22pin), SDAO(28pin), SCLO(29pin), MUTEX_DACO(30pin), MUTEX_SPO(31pin),
RESETXO(32pin), DATAO2(33pin), DATAO1(34pin), LRCKO(35pin), BCKO(36pin), SYSCKO(37pin)

*5 Open drain output terminal
SDAI(9pin)

Electric characteristic(Analogue serial)

V

=3.3V Unless specified, Ta=25°C,RL=10kΩ, VC standard

DD

Item Symbol

Min Standard Max
whole
Circuit current IQ - 15 30 mA VDD
Regulator part
Output voltage V

1.3 1.5 1.7 V IO=100mA

REG

PLL part
Lock frequency F

- 24.576 - MHz 256fs(fs=48kHz) input

LK8

Rating Value

Unit Object pin/Condition

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●Block diagram

Technical Note

BCKI

MCLK

VSS3

39

BCKO

LRCKO

SDATAO1

SYSCLKO

3740 38 36 27

35

SDATAO2

RESETXO

33 32 31 30 29 2834

MUTEX_DACO

MUTEX_SPO

SCLO

CLK

DSP

SP

Conv.

TEST

I2S

IF

2 3 4 5 6 7 8 9 10 11 13 14 15

1

N.C.

LRCKI

SDATA1

SDATA2

RESETX

Control

IF

MUTEX_SP

MUTEX_DAC

I2C

IF

LDO15

12

SCLI

１VSS

SDAI

REG15

DVDDCORE

SDAO

N.C.

N.C.

N.C.

N.C.

2526

24 23 22 21

SPDIFO

N.C.

ADDR

PLLA

16

17 18 19 20

N.C.

VDD

ANATEST

LDOPOFF

N.C.

２VSS

PLLFIL

MODE

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●Pin Description(s)

No.

Name Description of terminals

1 N.C (*2)

2 LRCKI I2S Audio LR signal input
3 SDATA1 I2S Audio data input 1
4 SDATA2 I2S Audio data input 2
5 RESETX Reset status with “L”
6 MUTEX_SP DAC mute signal input(*1)
7 MUTEX_DAC SP mute signal input(*1)
8 SCLI I2C Forwarding clock input

9 SDAI I2C Data input output
10 VSS1 Digital I/O GND
11 DVDDCORE Connect to REG15 terminal
12 REG15 Built-in regulator voltage output
13 LDOPOFF Built-in regulator POFF signal

input
14 ANATEST Analog test monitor terminal
15 VDD Digital I/O power supply
16 N.C
17 N.C
18 PLLFIL Filter connection terminal for

PLL
19 VSS2 Digital I/O GND
20 MODE Test mode selection input

N.C.：Non Connection
(*1)：signal terminal is used with D class amplifier IC (BD5446EFV etc.) for input I2S made by Rohm.
(*2) ：It connects with the lead frame of a package. Please use by OPEN or GND connection.

Type

-

D
D
D
B
B
B
F
E

-

­G
G

G

-

-

­G

­A

Technical Note

No.

21 ADDR I2C Slave address selection

22 SPDIFO S/PDIF Signal output
23 N.C
24 N.C
25 N.C
26 N.C
27 N.C
28 SDAO 2 line serial data output（*1）
29 SCLO 2 line serial clock output（*1）
30 MUTEX_DACO DAC mute signal output(*1)
31 MUTEX_SPO SP mute signal output(*1)
32 RESETXO Reset signal output(*1)
33 SDATAO2 I2S Audio data output 2

34 SDATAO1 I2S Audio data output 1
35 LRCKO I2S Audio LR signal output 1
36 BCKO I2S Audio clock output 1
37 SYSCLKO System clock output（*1）
38 VSS3 Digital I/O GND

39 MCLK Master clock input
40 BCKI I2S Audio clock input

Name Description of terminals

terminal

Type

B

C

-

-

-

-

­C
C
C
C
C
C

C
C
C
C

-

H
D

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●Terminal equal circuit figure

A B C

VDD

Technical Note

VDD

VDD

VSS

VSS

VSS

D E F

VDD

VSS

VSS

VSS

G H

VDD

VSS

VDD

VSS

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A

1.Command interface

I2C bus method is used in command interface with host CPU on BU9409FV.

In BU9409FV, not only writing but read-out is possible except for some registers.

Besides the slave address in BU9409FV, one byte select address can be Specified, written and readout.

2

The format of I

MSB LSB MSB LSB MSB LSB

S Slave Address A Select Address A Data A P

S: Start condition

Slave Address: Putting up the bit of read mode (H") or write mode (L") after slave address (7bit) set with ADDR,

A: The acknowledge bit in each byte adds into the data when acknowledge is sent and received.

When data is correctly sent and received, "L" will be sent and received.

There was no acknowledge for "H".

Select Address: 1 byte select address is used in BU9409FV. (MSB first)

Data: Data-byte, data(MSB first)sent and received

P: Stop Condition

SDA

SCL

11--11.. DDaattaa wwrriittiinngg

S Slave Address A Select Address A Data A P

: From master to slave : From slave to master

ADDR=0
MSB LSB

A6 A5 A4 A3 A2 A1 A0 R/W

1 0 0 0 0 0 0 0

ADDR=1
MSB LSB

A6 A5 A4 A3 A2 A1 A0 R/W

1 0 0 0 0 0 1 0

S Slave Address

(example) 80h 20h 00h 00h 00h
: From master to slave : From slave to master

C bus slave mode is shown below.

the data of eight bits in total will be sent. (MSB first)

MSB 6 5 LSB

Start Condition

↓When SDA , SCL=”H”

Select Address A Data A Data A Data A P

Stop Condition

↑When SDA , SCL=”H”

Setting of BU9409FV slave address

Terminal setting Write-mode

ADDR

0 80h
1 82h

Technical Note

Slave-address

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Writing procedure

Step Clock Master Slave(BU9409FV) Note

1 Start Condition

2 7 Slave Address

3 1 R/W (0)

4 1 Acknowledge

5 8 Select Address Writing object register 8 bit

6 1 Acknowledge

7 8 Data Writing data 8 bit

8 1 Acknowledge

9 Stop Condition

- The select address add +1 by auto increment function when the data is transferred continuously.
Repeat of Step 7~8.

11--22.. DDaattaa rreeaaddoouutt

First of all, the readout target address(ex.&h20h) is written in &hD0 address register at the time of readout.

In the following stream, data is read out after the slave address. Please do not return the acknowledge when ending the

reception.

S Slave Address A Req_Addr A Select Address A P

（example） 80h D0h 20h

S Slave Address A Data 1 A Data 2 A A Data N Ā P

（example） 81h **h **h **h
： Master to slave， ： Slave to master， A：With acknowledge， Ā：without acknowledge

Readout Procedure

Step Clock Master Slave(BU9409FV) Note

1 Start Condition

2 7 Slave Address

3 1 R/W (0)

4 1 Acknowledge

5 8 Req_Addr Address for I2C readout &hD0

6 1 Acknowledge

7 8 Select Address Readout object register 8 bit

8 1 Acknowledge

9 1 Stop Condition

10 1 Start Condition

11 7 Slave Address

12 1 R/W (1)

13 1 Acknowledge

14 8 Data Readout data 8 bit

15 1 Acknowledge

16 Stop Condition

○ The select address adds +1 by auto increment function when continuous data is transferred.
Repeat Step14~15.

&h80 (&h82)

&h80 (&h82)

&h81 (&h82)

Technical Note

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Technical Note

11--33.. CCoonnttrrooll ssiiggnnaall ssppeecciiffiiccaattiioonn

○ Bus line, I/O stage electrical specification and timing.

SDAI

t

BUF

t

LOW

t

t

R

F

t

HD;STA

SCLI

t

HD;STA

SP

t

HD;DAT

t

HIGH

t

SU;DATtSU;STA

t

SU;STO

Sr

Fig.1-1: Timing chart

Table 1-1: SDAI and SCLI bus-line characteristic (Unless specified, Ta=25, Vcc=3.3V)

Parameter Code

High-speed mode

Min. Max.

Unit

1 SCLI clock frequency fSCL 0 400 kHz

Bus-free-time between "Stop" condition and "Start"

2

condition

"Start" condition of hold-time (resending). After this period,

3

the first clock-pulse is generated.

4 LOW status hold-time of SCLI clock

5 HIGH status hold-time of SCLI clock

6 Setup time of resending “Start” condition

7 Data-hold-time

8 Data-setup time

9 Rising time of SDAI and SCL signal

10 Fall time of SDAI and SCL signal

11 Setup time of "Stop" condition

t

BUF 1.3 － μs

t

HD;STA 0.6 － μs

t

LOW 1.3 － μs

t

HIGH 0.6 － μs

t

SU;STA 0.6 － μs

t

HD;DAT 01) － μs

t

SU;DAT

t

R 20+Cb 300 ns

t

F 20+Cb 300 ns

t

SU;STO 0.6 － μs

500/250/15

0

－ ns

12 Capacitive load of each bus-line Cb － 400 pF

The above-mentioned numerical values are all the values corresponding to V

IH min

and V

IL max

level.

1) To exceed an undefined area on falling edged of SCLI, transmission device should internally offer the hold-time of

300ns or more for SDAI signal(V

of SCLI signal).

IH min

2) Data-setup time changes with setup of MCLK. In MCLK=512fs, data setup time is 150ns.

In MCLK=256fs, data setup time is 250ns. In MCLK=128fs, data setup time is 500ns.

The above-mentioned characteristic is a theory value in IC design and it doesn't be guaranteed by shipment inspection.

When problem occurs by any chance, we talk in good faith and correspond.

Neither terminal SCLI nor terminal SDAI correspond to 5V tolerant. Please use it within absolute maximum rating 4.5V.

P

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Technical Note

2.Switching of data and clock

I/O system chart of BU9409FV audio data is shown below.

Digital input1

Digital input1

Digital input2

Digital input2

SEL1

SDATA1

SDATA2

Audio DSP
(BU9409FV)

S-P

conversi

on1

S-P

conversi

on2

DSP CLK
(512fs)

DSP operation part
This part is performanced by hardware.

Main Main

Bass

Func.

Main

PLLA

mclk_

P-EQ

div

MCLK

SEL3

Sub

Treble

plla_

div

SYSCLKO

(256fs)

EVR

I2C

Sub

Control I/F

RESET

SEL2

MODE

Convers

Convers

Convers

・・・

ADDR

P-S

SDATAO1(Main)

ion1

P-S

SDATAO2(Sub)

ion2

P-S

ion3

SPDIFO

D Class amp output

D Class amp output

(Sub Woofer)

Optical output

BU9409FV has 2 digital stereo input and 3 digital stereo output with the same sampling rate.

Output from DSP operation part is converted into I

2

S mode digital output or S/PDIF mode digital serial output.

System clock uses master clock input from MCLK terminal, makes 512fs multiplying clock in PLL block. Moreover, 256fs

synchronous clock can be output from terminal SYSCLKO, and the clock is supplied to external DAC or D class SP

amplifier.

SPDIFO and output data selection of SDATAO1 and SDATAO2 should unify the DSP processing after (post) or processing

before (pre) with all outputs.

22--11.. SS--PP ccoonnvveerrssiioonn11 iinnppuutt ddaattaa sseelleeccttiioonn((SSEELL11))

Default = 0

Select Address Value Operating Description

&h03 [ 0 ]

0 Input data from SDATA1

1 Input data from SDATA2

22--22.. SS--PP ccoonnvveerrssiioonn22 iinnppuutt ddaattaa sseelleeccttiioonn((SSEELL11))

Default = 0

Select Address Value Operating Description

&h03 [ 4 ]

0 Input data from SDATA1

1 Input data from SDATA2

22--33.. OOuuttppuutt ddaattaa sseelleeccttiioonn((SSEELL22)) ttoo PP--SS ccoonnvveerrssiioonn11 ((SSDDAATTAAOO11 TTeerrmmiinnaall))

Default = 0

Select Address Value Operating Description

&h04 [ 1：0 ]

0 Main data output after DSP is processed.

1 Sub data output after DSP is processed.

2 Main data output before DSP is processed.

3 Sub data output before DSP is processed.

(Main SP)

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Technical Note

22--44.. OOuuttppuutt ddaattaa sseelleeccttiioonn((SSEELL22)) ttoo PP--SS ccoonnvveerrssiioonn22 ((SSDDAATTAAOO22 TTeerrmmiinnaall))

Default = 0

Select Address Value Operating Description

&h04 [ 5：4 ]

22--55.. SSPPDDIIFFOO TTeerrmmiinnaall oouuttppuutt ddaattaa sseelleeccttiioonn（（SSEELL22））

Default = 0

Select Address Value Operatin

&h05 [ 1：0 ]

22--66.. SSyysstteemm cclloocckk sseelleeccttiioonn（（SSEELL33））

Select the DSP clock supplied to S-P conversion1、S-P conversion2、DSP、P-S conversion1、P-S conversion2、S/PDIF

output part.

Default = 0

Select Address Value Operating Description

&h08 [ 5：4 ]

After power on or reset released, system block selection uses clock(even if not 512fs is ok) input from terminal MCLK to

receive I2C command and initialize BU9409. Then set the dividing frequency ratio of PLL block (mclk_div, pll_div) that is

suitable for the clock frequency from terminal MCLK , when PLL_512fs clock from PLL is steady, set &h08 = 10h.

Dividing frequency ratio setting of PLL block which corresponding to input clock from terminal MCLK

22--77..

Sampling rate of input clock Setting of mclk_div

512fs（24.576MHz、fs=48kHz）
256fs（12.288MHz、fs=48kHz）

128fs（6.144MHz、fs=48kHz）

0 Sub data output after DSP is processed.

1 Main data output after DSP is processed.

2 Sub data output before DSP is processed.

3 Main data output before DSP is processed.

0 Main data output after DSP is processed.

1 Sub data output after DSP is processed.

2 Main data output before DSP is processed.

3 Sub data output before DSP is processed.

0 Chose the input from a MCLK terminal as a clock.

1 Chose the PLL output as a clock.

2

Chose the input from a SDATA2terminal as a clock. (used for IC test).

3

&hF3

10h 01h 23h

08h 01h 23h

04h 01h 23h

Setting of pll_div

&hF5

g Description

PLL initialization

&hF6

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Technical Note

3. S-P Conversion 1, S-P Conversion 2

BU9409FV has two serial-parallel conversion circuits. （S-P conversion 1, S-P conversion 2）

S-P conversion 1 & 2 receives the audio data of three-wire serial input from terminal and converts it into parallel data.

They select the inputs from LRCKI (2pin), BCKI (40pin), SDATA1 (3pin), and SDATA2(4pin).

Input format has IIS method, left-justified method and right-justified method. Moreover, for bit clock frequency, 64fs or 48fs

can be selected, and when 48fs is selected, the input format becomes the fixed right-justification. In addition, 16bit, 20bit and

24bit inputs can be selected respectively.

Timing chart of each transmission method is shown in the diagram below.

IIS method

IIS方式

LRCKI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

BCKI

MSB LSB

S

DATAI

16bit

MSB LSB

S

16bit

20bit

24bit

20bit

24bit

Left-justified method

左詰方式

LRCKI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

BCKI

MSB L SB

S

DATAI

16bit

20bit

24bit

MSB L SB

S

16bit

20bit

24bit

Right-justified method

右詰方式

LRCKI

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

BCKI

DATAI

MSB LSB

S

16bit

20bit

24bit

MSB LSB

S

16bit

20bit

24bit

48fs

LRCKO

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24

BCKO

DATAO

MSB LSB

S

16bit

20bit

24bit

MSB L SB

S

16bit

20bit

24bit

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Technical Note

33--11.. TThhrreeee--wwiirree sseerriiaall iinnppuutt’’ss bbiitt cclloocckk ffrreeqquueennccyy sseettttiinngg

Default = 0

Select Address Value Operational explanation

S-P conversion1, S-Pconversion2

&h0B [ 4 ]

33--22.. TThhrreeee--wwiirree sseerriiaall iinnppuutt’’ss ffoorrmmaatt sseettttiinngg

Default = 0

Select Address Value Operational explanation

S-P conversion1 &h0B

S-P conversion2 &h0C

33--33.. TThhrreeee--wwiirree sseerriiaall iinnppuutt’’ss ddaattaa bbiitt wwiiddtthh sseettttiinngg

Default =

S-P conversion1 &h0B

S-P conversion2 &h0C

0

Select Address Value Operational explanation

[ 3：2 ]

[ 3：2 ]

[ 1：0 ]

[ 1：0 ]

0 64fs method

1 48fs method

0 IIS method

1 left-justified method

2 right-justified method

0 16 bit

1 20 bit

2 24 bit

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Technical Note

4. Digital sound processing（DSP）

BU9409FV’s Digital Sound Processing（DSP） consists of special hardware most suitable to Thin TV.
BU9409FV uses this special DSP to perform the following processing.
Prescaler, DC Cut HPF, Channel Mixer, P

2

Volume（Perfect Pure Volume）, BASS, MIDDLE, TREBLE,

Pseudo Stereo, Surround, P2Bass, P2Treble, 7 Band・Parametric Equalizer, Master Volume, L/R Balance, PostScaler,
Output Clipper、 Sub-woofer output Processing.

DDSSPP OOuuttlliinnee aanndd SSiiggnnaall FFllooww

Data width： 32 bit （DATA RAM）
Machine cycle： 40.7ns （512fs, fs=48kHz）
Multiplier： 32×24 → 56 bit
Adder： 32＋32
Data RAM： 256×32 bit

→ 32 bit

MUX

Data

Input

RAM

MUX

0

M
U
X

Coefficient RAM： 128×24 bit
Sampling frequency： fs=48kHz
Master clock： 512fs （24.576MHz, fs=48kHz）

ADD

Acc

Digital signal from 16bit to 24bit is inputted to DSP,

Output

and it is extended by +8bit（+42dB） as overflow margin on the upper side.

The clip process is performed in DSP when the process exceeding this range is performed.

Input1

Input2

Pre

scaler

HPF

Channel

mixer

Digital Audio Processing Signal Flow

P2Volume

BASS

MIDDLE

TREBLE

Scaler

Pseude

stereo

1

surround

＆

P2Bass P2Treble

Channel

Channel

mixer

mixer

Scaler

LPF

7Band
P-EQ

2

3band
P-EQ

EVR

＆

Blance

EVR

＆

Balance

Post

scaler

＆

Clipper

Post

scaler

＆

Clipper

44--11.. PPrreessccaalleerr

When digital signal is inputted to audio DSP, if the level is full scale input and the process of surround or equalizer is
performed, then it overflows, therefore the input gain is adjusted by prescaler.
Adjustable range is +24dB to -103dB and can be set by the step of 0.5dB.
Prescaler does not incorporate the smooth transition function.

Default = 30h

Select Address Operational explanation

&h20 [ 7：0 ]

command gain

00
01 +23.5dB

30
31

32

……

FE
FF

+24dB

0dB

-0.5dB

-1dB

-103dB

-∞

……

Coefficient

operation

Circuit

Coefficient

RAM

Decoder

circuit

Main output

Sub output

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Technical Note

44--22.. DDCC CCuutt HHPPFF

The DC offset component of digital signal inputted to the audio DSP is cut by this HPF.
The cutoff frequency fc of HPF is 1Hz, and first-order filter is used.

Default = 0

44--33.. CChhaannnneell mmiixxeerr

It performs the setting of mixing the sounds of left channel & right channel of digital signal inputted to the audio DSP.
Here the stereo signal is made to be monaural.

The data inputted to Lch of DSP is mixed.

Default = 0

The data inputted to Rch of DSP is mixed.

Default = 0

Select Address Value Operational explanation

&h21 [ 0 ]

Select Address Value Operational explanation

&h22 [ 7：6 ]

Select Address Value Operational explanation

&h22 [ 5：4 ]

0 Not using the DC Cut HPF

1 Using the DC Cut HPF

0 Inputting the Lch data

1 Inputting the data of （Lch + Rch） / 2

2 Inputting the data of （Lch + Rch） / 2

3 Inputting the Rch data

0 Inputting the Rch data

1 Inputting the data of （Lch + Rch） / 2

2 Inputting the data of（Lch + Rch） / 2

3 Inputting the Lch data

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© 2012 ROHM Co., Ltd. All rights reserved.

15/54

2012.03 - Rev.

BU9409FV

A

2

2

44--44.. P

P

VVoolluummee （（PPeerrffeecctt PPuurree VVoolluummee））

There are some scenes in which sound suddenly becomes large like plosive sound in TV Commercial or Movie.

2

Volume function automatically controls the volume and adjusts the output level.

P

In addition, it also adjusts in such a way that a whispery sound can be heard easily.

2

Volume function operates in the fields of (1), (2) & (3) divided according to input level.

P

(1) at the time of V

inf

Ｉ

(-∞)～V

Noise is prevented from being lifted by P

(2) When input level is over V
V

= VI + α

O

α： Lifting the Whole output level by the offset value α
(3) When output level Ｖ

V

Ｏ

= K・VI + α

O

min

Ｉ

and output is below V

min

Ｉ

exceeds V

Omax

2

Volume function.

Omax

V

O

V

Omax

P2V_MAX

(2)

K： Slope for suppressing of D range （P2V_K）

It is also possible to set an output level constant.

2

Selection of using the P

Default = 0

Volume function.

V

Omin

α

V

Oinf

(1)

V

V

Iinf

Imin

P2V_MIN

Select Address Value Operational explanation

&h33 [ 7 ]

0 Not using the P2Volume function

1 Using the P2Volume function

Setting of V

In order to cancel that noise etc. is lifted by P

2

Volume functions.

P

Default = 00h

min

Ｉ

2

Volume, the P2V_MIN sets the minimum level at which (to the minimum) the

command

Select Address Operational explanation

&h34 [ 4:0 ]

command gain

00 -∞
01
02
03
04
05
06
07

-30dB

-32dB

-34dB

-36dB

-38dB

-40dB

-42dB

command gain

-44dB

08
09

-46dB

0A

-48dB

-50dB

0B
0C

-52dB

0D

-54dB

0E

-56dB

0F

-58dB

command gain

-60dB

10
11

-62dB

12

-64dB

-66dB

13
14

-68dB

15

-70dB

16

-72dB

17

-74dB

コマンド値 ゲイン

-76dB

18
19

-78dB

1A

-80dB

-82dB

1B
1C

-84dB

1D

-86dB

1E

-88dB

1F

-90dB

Technical Note

K

(3)

0dB

P2V off

V

I

Setting of V

max

Ｏ

P2V_MAX sets the output suppression level. It represents the output level V
case of setting of P2V_K = “0h”（slope is 0）.

Default = 00h

Select Address Operational explanation

&h35 [ 4:0 ]

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© 2012 ROHM Co., Ltd. All rights reserved.

command gain

00 0dB
01

-1dB

-2dB

02

-3dB

03
04

-4dB

05

-5dB

06

-6dB

07

-7dB

16/54

command gain

08

-8dB

09

-9dB

-10dB

0A

-11dB

0B
0C

-12dB

0D

-13dB

0E

-14dB

0F

-15dB

at the time of input level VI = 0dB in the

max

Ｏ

command gain

10
11
12
13
14
15
16
17

-16dB

-17dB

-18dB

-19dB

-20dB

-21dB

-22dB

-23dB

command gain

18

-24dB

19

-25dB

-26dB

1A

-27dB

1B
1C

-28dB

1D

-29dB

1E

-30dB

1F

-

2012.03 - Rev.

BU9409FV

A

Setting of K
P2V_K sets the slop of D range. It sets the P2V_MAX = “1Eh”（-30dB） and represents the output level V

input level V

= 0dB.

I

Default = 00h

Select Address Operational explanation

&h36 [ 3:0 ]

command gain

0 -30dB
1

-28dB

-26dB

2

-24dB

3
4

-22dB

5

-20dB

6

-18dB

7

-16dB

comman

8

9
A
B
C
D

E

F

gain

-14dB

-12dB

-10dB

-8dB

-6dB

-4dB

-2dB
0dB

Setting of α

P2V_OFS makes small voice easy to be heard because the whole output level is lifted.

Default = 00h

Select Address Operational explanation

&h37 [ 4:0 ]

command gain

00 0dB
01
02
03
04
05
06
07

+1dB
+2dB
+3dB
+4dB
+5dB
+6dB
+7dB

command gain

08
09
0A
0B
0C
0D
0E
0F

+8dB

+9dB
+10dB
+11dB
+12dB
+13dB
+14dB
+15dB

command gain

10

+16dB

11

+17dB
+18dB

12

+19dB

13
14

+20dB

15

+21dB

16

+22dB

17

+23dB

Setting 1 of transition time at the time of attack

2

A_RATE is the setting of transition time when the state of P

Default = 0

Volume function is transited to (2)→(3).

Select Address Operational explanation

&h38 [ 6:4 ]

command A_RATE time

0 1ms
1 2ms
2
3

3ms
4ms

command

4
5
6
7

A_RATE time

10ms
20ms
40ms

Setting 1 of transition time at the time of recovery

2

R_RATE is the setting of transition time when the state of P

Default = 0h

Volume function is transited to (3)→(2).

Select Address Operational explanation

&h38 [ 3:0 ]

command R_RATE time

0 0.25s
1
2
3
4
5
6
7

0.5s

0.75s
1s

1.25s

1.5s
2s

2.5s

command

8
9
A
B
C
D
E
F

R_RATE time

3s
4s
5s
6s
7s
8s
9s

10s

Technical Note

max

Ｏ

command gain

18
19
1A
1B
1C
1D
1E
1F

5ms

at the time of

+24dB

-

-

-

-

-

-

-

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© 2012 ROHM Co., Ltd. All rights reserved.

17/54

2012.03 - Rev.