GPIO ICs Series
GPIO Expander IC
BU8272GUW
●Description
GPIO expander is useful especially for the application that is in short of IO ports.
It can
1. Control GPIO output states by I
2. Know GPIO input states by I
Furthermore,it has the interrupt function that can release CPU from polling the registers in the GPIO expander.
GPIO expander are also equipped with Built-in power on reset, 3V tolerant input,and NMOS open-drain output.
●Features
1) 400Kbps, 2-Wire serial interface
2) Interrupt output
3) 20-bit General purpose input/output interface
8-bit and 12-bit IO groups are designed for different power supply
voltages from the device core voltage supply
● Absolute Maximum Ratings
(Ta=25℃)
Item Symbol Value Unit comment
Supply Voltage
Input voltage VI
Storage temperature range Tstg -55 ~ +125
Package power PD 310 *2 mW -
*1
The input voltage range doesn't exceed absolute maximum ratings even including +0.5 V.
*2
Package dissipation will be reduced each 3.1mW/
This IC is not designed to be X-ray proof.
● Recommended Operating Conditions
(Ta=-25
o
C ~+85 oC)
2
C write protocol.
2
C read protocol.
VDD -0.3 ~ +2.5 V -
VDDI2C -0.3 ~ +3.5 V -
VDDIO -0.3 ~ +3.5 V -
-0.3 ~ VDD +0.5
*1
V CMOS Core
-0.3 ~ VDDI2C +0.5 *1 V CMOS I/O for 2-Wire
-0.3 ~ VDDIO +0.5 *1 V CMOS I/O
o
C -
o
C when the ambient temperature increases beyond 25 oC.
No.09098EAT01
Item Symbol
Unit Condition
Min Typ Max
Limit
Supply voltage (VDD） V
Supply voltage（VDDI2C） V
Supply voltage（VDDIO1） V
Supply voltage（VDDIO2） V
2-Wire operating Frequency F
1.65 1.80 1.95 V Core
VDD
1.65 - 3.45 V 2-Wire,INT,ADR, XRST
VDDI2C
1.65 - 3.45 V GPIO[7:0]
VDDIO1
1.65 - 3.45 V GPIO[19:8]
VDDIO2
- - 400 KHz Slave
I2C
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU8272GUW
● Package Specification（VBGA035W040）
Technical Note
Fig.1 Package Specification
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU8272GUW
● Pin Diagram
F
E
D
C
B
A
VDDI2C VDDIO2GPIO18 GPIO16 GPIO14 GPIO13
VDD VDDIO1GPIO0 GPIO1 GPIO3
INT GPIO7GPIO2 GPIO4 GPIO6
SCL
GND
GND GND
GPIO5
GPIO9
ADR GPIO10SDA GND GND GPIO11
1
2
3
4
5
Technical Note
GPIO8XRST
GPIO12GPIO19 GPIO17 GPIO15 VDD
6
Fig.2 Pin Diagram（Bottom View）
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© 2009 ROHM Co., Ltd. All rights reserved.
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BU8272GUW
● Block Diagram
INT
VDDI2C
ADR
SCL
SDA
XRST
VDD
Input
Filter
Reset
Functional Block Diagram
Interrupt
Logic
I2C Bus
Control
Fig.3 Functional Block Diagram
INT_MASK
IN/OUT
Control
Shift
Register
Write Pulse
Read Pulse
8bit
12bit
GPIO
[7:0]
GPIO
[19:8]
Technical Note
VDDIO1
8bit
GPIO[7:0]
12bit
GPIO[19:8]
VDDIO2
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BU8272GUW
● Electrical Specification
VDD=1.8V, VDDIO=3.0V, VDDI2C=3.0V, Ta=25 oC，without output load conditions
Item Symbol
Min. Typ. Max.
Input H Voltage VIH 0.75xVDDIO - - V Input L Voltage VIL - - 0.25xVDDIO V -
Limit
Unit comment
Technical Note
Input H Current IIH 0 - 3
Input L Current IIL -3 - 0
Output H Voltage VOH VDDIO－0.2 - - V IOH=-1.0mA
Output L Voltage VOL - - 0.2 V IOL=1.0mA
SCL clk frequency fSCL - - 400 KHz
Bus free time tBUF 1.3 - （repeat）Start condition
Setup Time
（repeat）Start condition
Hold Time
SCL Low Time tLOW 1.3 - SCL High Time tHIGH 0.6 - Data Setup Time tSU:DAT 100 - - ns
Data Hold Time tHD:DAT 0 - - ns
Stop condition
Setup Time
Interrupt Valid tIV - - 0.1
Interrupt Reset tIR - - 1.0
Output Data Valid tDV - - 0.8
Input Data Setup Time tDS 100 - - ns
tSU:STA 0.6 - -
tHD:STA 0.6 - -
tSU:STO 0.6 - -
A
A
s
s
s
s
s
s
s
s
s
-
-
Input Data Hold Time tDH 0 - Standby Current I
- - 3.0
STBY
s
A
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© 2009 ROHM Co., Ltd. All rights reserved.
2009.09 - Rev.A
BU8272GUW
*
1
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
*
2
● Pin-out Functional Descriptions
1. Pin table
PIN
No.
Land
number
PIN name I/O
Power
source
system
1 A1 VDDI2C - 2 (NC) - - 3 C3 GND - 4 C1 ADR IN VDDI2C
5 C2 SDA INOUT VDDI2C
6 D1 SCL IN VDDI2C
7 D2 XRST IN VDDI2C
8 E1 INT OUT VDDI2C
9 E2 GND - 10 F1 VDD - 11 F2 GPIO0 INOUT VDDIO1
12 D3 GND - 13 F3 GPIO1 INOUT VDDIO1
14 E3 GPIO2 INOUT VDDIO1
15 F4 GPIO3 INOUT VDDIO1
16 E4 GPIO4 INOUT VDDIO1
17 F5 GPIO5 INOUT VDDIO1
18 E5 GPIO6 INOUT VDDIO1
19 F6 VDDIO1 - 20 E6 GPIO7 INOUT VDDIO1
21 D4 GND - 22 D6 GPIO8 INOUT VDDIO2
23 D5 GPIO9 INOUT VDDIO2
24 C6 GPIO10 INOUT VDDIO2
25 C5 GPIO11 INOUT VDDIO2
26 B6 GPIO12 INOUT VDDIO2
27 B5 VDD
28 A6 VDDIO2 - 29 A5 GPIO13 INOUT VDDIO2
30 C4 GND - 31 A4 GPIO14 INOUT VDDIO2
32 B4 GPIO15 INOUT VDDIO2
33 A3 GPIO16 INOUT
34 B3 GPIO17 INOUT
VDDIO2 General purpose inout. Pull-up to VDD
VDDIO2 General purpose inout. Pull-up to VDD
35 A2 GPIO18 INOUT VDDIO2
36 B2 GPIO19 INOUT
*1
The Low Active or High Active of interrupt output level and specific bit mask control are decided by internal register value.
*2
When IOSEL register is set to “1”, please pull-up IO output to the same value as VDDIO1 or VDDIO2 voltages respectively.
VDDIO2 General purpose inout. Pull-up to VDD
Technical Note
Function
B
Serial data inout for 2-Wire A
Clock for 2-Wire B
Reset（Low Active）
Interrupt signal
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
General purpose inout. Pull-up to VDD
Cell
Type
B
C
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
A
XRST
-
Hi-z
-
L
-*3
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
Hi-z
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2009.09 - Rev.A
BU8272GUW
2. Equivalent IO circuit diagram
ABC
Fig.4 Equivalent IO circuit diagram
Technical Note
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BU8272GUW
Technical Note
● Functional Description
1 2-Wire Bus Interface
1.1 Slave address
Please pull-up SDA and SCL to the same potential of voltage as DVDDI2C.
BU8272GUW is controlled by using an on-chip 2-Wire slave interface. Two kinds of the device address, “0001111” at
ADR=”1” or “0001000” at ADR=”0” can be used. The transfer bit rate supports Fast-mode up to max 400Kbps.
A7 A6 A5 A4 A3 A2 A1 W/R
ADR=0 0 0 0 1 0 0 0
ADR=1 0 0 0 1 1 1 1
2-Wire Slave address
0/1
Fig. 5 Slave address
1.2 Data transfer
One bit of data is transferred during SCL = “1”. During the bit transfer SCL = “1” cycle, the signal SDA should keep the
value. If SDA changes during SCL = “1”, a START condition or STOP condition occur and it is interpreted as a control
signal.
SDA
SCL
Data is valid
when SDA is
stable
SDA is
variable
Fig. 6 Data transfer
1.3 START-STOP conditions
When SDA and SCL are “1”, the data isn’t transferred on the 2-wire bus. If SCL remains “1” and SDA transfers from “1” to
“0”, it means a “Start condition” is occurred and access is started.
If SCL remains “1” and SDA transfers from “0” to “1”, it means a “Stop condition” is occurred and access is stopped.
SDA
SCL
S P
START
condition
STOP
condition
Fig. 7 START-STOP conditions
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BU8272GUW
Technical Note
1.4 Acknowledge
After start condition is occurred, 8 bits data will be transferred. Then the “Master” opens SDA and “Slave” de-asserts SDA to
“0” as an “Acknowledge” returned.
SDA output
from “Master”
Not acknowledge
SDA output
from “Slave”
SCL 1 2 8 9
START condition
S
Acknowledg
Clock pulse
For Acknowledgs
e
Fig. 8 Acknowledge
1.5 Writing protocol
A writing protocol is shown in Fig.8-5 below. GPIO register address in BU8272GUW is transferred after one byte of slave
address with a write commend. The 3rd byte data is written to internal register which defined by the 2nd byte. After the each
byte transfer, the register address will be automatically increased. However, when the register address increased to the final
address (09h), it will be reset to (00h) after the byte transfer.
GPIO register address (00h) is assigned to GPIO register[7:0], the register address (01h) is assigned to GPIO register[15:8],
and the register address (02h) is assigned to GPIO register[19:16]. Only the 4 bits LSB data are valid in the register with
GPIO register address (02h).
S A A A P
XXXX XX 0X
R/W=0(write)
Transmit from master
Transmit from slave
D7D6D5D4 D3 D2D1D0 D7D6D5D4D3 D2D1D0XXXXA3A2A1A0
data
A=acknowledge
A
=not acknowledge
S=Start condition
P=Stop condition
A
Register address
increment
dataRegister addressSlave address
Register address
Fig. 9 Writing protocol
increment
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BU8272GUW
Technical Note
1.6 Reading protocol
After Writing the slave address and Read/Write commend bits, the next byte is read. The reading register address is next of
previous accessed address. Therefore, the data is read with address increment. When the address in increased to the last,
the following read address will be reset to (00h). When the GPIO port [19:16] is read, 4 bits of “0” will be added from MSB,
and the value of 4 bits from GPIO port [19:16] is read from 2-wire interface.
XXX X X X X D7D6D5D4D3D2D1 D0 D7D6D5 D4D3 D2 D1D0
Salve address
1S A P
data
R/W=1(Read)
A
Register Address
increment
data
A
Register address
increment
Transmit fronm master
Transmit from slave
A=acknowledge
A
=not acknowledge
S=Start conditio n
P=Stop condition
Fig. 10 Readout protocol
1.7 Complex reading protocol
After the specifying the internal register address, a resending start condition occurs and the direction of data transfer is
changed then reading access is done. Therefore, the data is read followed by address increment. If the address is
increased to the last, it will be reset to (00h).
S A A A
XXXX XX0X
Slave address
R/W=0(write)
X X X X A3 A2A1 A0
Register address
Sr 1
XXXX XXX
Slave address
R/W=1(read)
D7 D6D5D4 D3D2 D1D0
data
Transmit from master
Transmit from slave
A
Register address
increment
D7 D6 D5D4 D3D2 D1D0
data
Register address
A=acknowledge
=not aclnowledge
A
S=Start condition
P=Stop condition
Sr=Start cond ition
increment
P
A
Fig. 11
Complex reading protocol
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BU8272GUW
1.8 Timing Diagram
Transfer
state
SCL
SDA
(Repeat) Start
condition
tSU;STA
tBUF tHD;STA
Technical Note
BIT 7 BIT 6 Ack Stop condition
tLOW tHIGH 1/fSCLK
tSU;DAT tHD;DAT tSU;STO
Fig. 12 Timing Diagram
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2009.09 - Rev.A
BU8272GUW
Technical Note
2. GPIO･INT Interface
The default mode of all GPIO [19:0] ports are input mode upon the power-on. By setting the specific bit of Interrupt Mask Sel
register to “1”, the corresponding bit of Interrupt will be masked. There are two kinds of ways to control input / output operations.
The first way is to change read / write register value in each corresponding bit. Second way is to write each GPIO register a “0”
value for ‘Output operation’ and a “1” value for ‘input operation’. It is necessary to pull up the output to the same voltage value
as the corresponding I/O power supply in the second way.
Interrupt Logic
Interrupt Mask
Read Data Register
Please pull up the output to the same
voltage value as the corresponding I/O
power supply
GPI Reg
S
Read Configuration
XRST
Pulse
0
1
GPIO[19:0]
Write Configuration
Data From
Shift Register
Pulse
GPO Reg
S
0
1
IOSEL Reg
Data From
Shift Register
R/W Reg
S
Fig. 13 GPIO・INT system
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BU8272GUW
Technical Note
2.1 Write to GPIO Port
After setting the internal register address, the data from master is written from MSB.
After Acknowledge is returned, the value of each GPIO port will be changed.
・IOSEL=1
In the condition that IOSEL register is “1”, after sending Acknowledge, a value “0” is output from the GPIO port which the
corresponding bit is transferred as ‘0’, and a input-mode(Hi-Z) is output from GPIO port which the corresponding bit is
transferred as ‘1’.
SCL
SDA
GPIO
[7:0]
GPIO
[15:8]
123456789
S X X X X X X X 0 Ack AckReg AddressMSB LSB AckData1 (GPIO[7:0])MSB LSB AckData2 (GPIO[15:8])MSB LSB P
Start Condition
Write Acknowledge From Slave
Acknowledge From Slave
tDV
Acknowledge From Slave
Stop Condition
Data1 Valid
tDV
Fig. 14 Write to GPIO port （Pull-up-mode）
・IOSEL=0
In the condition that IOSEL register is “0”, data input or output is defined by the value of RWSEL register. Therefore, after
“0” is written to each bit of RWSEL register, the data is output from GPIO port. If “0” is written to RWSEL register at first, the
data will be output immediately from the GPIO port after the acknowledge signaling.
SCL
SDA
GPIO
[7:0]
GPIO
[15:8]
123456789
S X X X X X X X 0 Ack AckReg AddressMSB LSB AckData1 (GPIO[7:0])MSB LSB AckRWSEL = Write ModeMSB LSB P
Start Condition
Write Acknowledge From Slave
Acknowledge From Slave
Acknowledge From Slave
Stop Condition
tDV
tDV
Fig. 15 Write to GPIO port （RWSEL-mode）
Data2
Data1
Valid
Data2
Valid
Valid
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2009.09 - Rev.A
BU8272GUW
Technical Note
2.2 Read From GPIO Port
After slave address and R/W bit is written, the GPIO ports value will be read into the GPIO registers. (refer to section 8.1.6
for 2-wire reading protocol.) The data fixed between tow consecutive acknowledges will be transferred to the Master.
SDA
GPIO
2.3 Interrupt Valid/Reset
The transition of each GPIO port de-asserts the interrupt signal (INT), generates the interrupt signal by asserting the INT
after each acknowledge signaling.
Either a “High-Active” or a “Low-Active” interrupt signaling can be defined by changing the INTSEL register value
beforehand.
SDA
GPIO
INT
123456789SCL
S X X X X X X X 1 Ack Ack NAData1MSB LSB
Start Condition
Data0
Read Acknowledge From Slave
Data0MSB LSB
Acknowledge From Master
No Acknowledge From Master
Data1 Data2
tDHtDS
Fig. 16 Read from GPIO port
123456789SCL
S X X X X X X X 1 Ack Ack NAData3MSB LSB
Start Condition
Data1 Data2 Data3
tIV tIR
Read Acknowledge From Slave
Data2MSB LSB
Acknowledge From Master
No Acknowledge From Master
P
Stop Condition
P
Stop Condition
Fig. 17 Interrupt Valid/Reset
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BU8272GUW
Technical Note
● The Setting Registers
When setting address is written beyond 00h~09h, the register address will be forced to value 00h.
When the final address is set to 09h, then the next address 00h will be written.
By making XRST “Low”, the setting register value will be initialed shown in following register map.
1. Register map
Addr Init Type D7 D6 D5 D4 D3 D2 D1 D0
00h ffh R/W GPIO7 GPIO6 GPIO5 GPIO4 GPIO3 GPIO2 GPIO1 GPIO0
01h ffh R/W GPIO15 GPIO14 GPIO13 GPIO12 GPIO11 GPIO10 GPIO9 GPIO8
02h 0fh R/W - - - - GPIO19 GPIO18 GPIO17 GPIO16
03h 00h R/W MASK7 MASK6 MASK5 MASK4 MASK3 MASK2 MASK1 MASK0
04h 00h R/W MASK15 MASK14 MASK13 MASK12 MASK11 MASK10 MASK9 MASK8
05h 00h R/W - - - - MASK19 MASK18 MASK17 MASK16
06h ffh R/W RWSEL7 RWSEL6 RWSEL5 RWSEL4 RWSEL3 RWSEL2 RWSEL1 RWSEL0
07h ffh R/W
08h 0fh R/W - - - -
RWSEL15 RWSEL14 RWSEL13 RWSEL12 RWSEL11 RWSEL1
0
RWSEL19 RWSEL18 RWSEL17 RWSEL1
RWSEL9 RWSEL8
6
09h 03h R/W - - - - - INTSEL IOSEL2 IOSEL1
2. Register functional explanations
Symbol Addr Init Description
GPIO7
～
GPIO0
GPIO15
～
GPIO8
GPIO19
～
GPIO16
MASK7
～
MASK0
MASK15
～
MASK8
MASK19
～
MASK16
RWSEL7
～
RWSEL0
RWSEL15
～
RWSEL8
RWSEL19
～
RWSEL16
IOSEL1
IOSEL2 1h
INTSEL 0h
00h ffh Read or write data of GPIO bit 0 to 7.
01h ffh Read or write data of GPIO bit 8 to 15.
02h 0fh
03h 00h
04h 00h
05h 00h
06h ffh
07h Ffh
08h 0fh
1h
09h
Read or write data of GPIO bit 16 to bit 19.
In writing mode, 4 bits of MSB is ignored and in reading mode, 4 bits of
“0” is filled up from MSB.
0: Interrupt is not masked when “0” is written to GPIO bit 0 to 7
1: Interrupt is masked when “0” is written to GPIO bit 0 to 7
0: Interrupt is not masked When “0” is written to GPIO bit 8 to 15
1: Interrupt is masked When “0” is written to GPIO bit 8 to 15
0: Interrupt is not masked when “0” is written to GPIO bit 16 to 19
1: Interrupt is masked when “0” is written to GPIO bit 16 to 19
In writing mode, 4 bit of MSB is ignored and in reading mode, 4 bits of
“0” is filled up from MSB.
0: GPIO bit 0 through 7 becomes output mode.
1: GPIO bit 0 through 7 becomes input mode.
0: GPIO bit 8 through 15 becomes output mode.
1: GPIO bit 8 through 15 becomes input mode.
0: GPIO bit 16 through 19 becomes output mode.
1: GPIO bit 16 through 19 becomes input mode.
0: RWSEL bit 0 through 7 becomes available.
1: Change to pull-up mode.
0: RWSEL bit 8 through 19 becomes available.
1: Change to pull-up mode.
0: Make Interrupt “Low active”.
1: Make Interrupt “High active”.
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BU8272GUW
Technical Note
● Appendix
1. About difference between I2C and 2-Wire
2-wire interface logic uses a normal IN/OUT cell (Hi-Z or only “0” output) instead of an Open-Drain cell in normal I2C interface.
For this reason, the VDDI2C voltage level must be same as the connected other normal I2C masters’. Therefore, any other I2C
slave with same bus level can be connected to the bus.
2 .In case of illegal access
The current data will be canceled and next access is necessary.
*1
In case of a consecutive Start-condition and Stop-condition occurred.
In case of Resend-condition or Stop-condition occurred during a slave address or R/W bit witting cycles.
In case of Resend-condition or Stop-condition occurred during data witting cycles.
*1
during 2-Wire data transference
3. About the handling of the no using GPIO port
Any no using GPIO port must be pulled-up or connected to GND. In order to prevent from any unexpected interrupt happening
when a no using GPIO is connected to GND, the corresponding bit of GPIO Mask register must be disabled by Mask register
access, or simply read the GPIO value into corresponding internal GPIO port register. The no using GPIO port power supply
(VDDIO1 or VDDIO2) must be connected to the voltage value defined in this specification, never left it open.
4. Caution of power on sequence
The BU8272GUW can not works correctly even one of the power supply among the core power supply (VDD) and the I/O power
supply ( VDDI2C, VDDIO1, VDDIO2) is not connected to specified conditions described in this specification.
The power on sequence must be designed to give core power supply first then I/O power. Inversely, the I/O power supply must
be switched off before the core power down in the device power down sequence.
5. Reset release timing
Core power supply (VDD) and I/O power supply (VDDI2C, VDDIO1, VDDIO2) first. Afterwards, release XRST.
VD
VDDI2C
VDDIO1(2)
,
Release XRST
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●Ordering part number
Technical Note
B U 8 2 7 2 G U W - E 2
Part No. Part No.
VBGA035W040
1PIN MARK
4.0 ± 0.1
35-φ0.295±0.05
0.08 S
0.75 ± 0.1
M
φ
0.05
P=0.5×5
F
ABS
E
D
C
B
A
123456
4.0 ± 0.1
0.9MAX.
0.10
S
A
0.5
0.75 ± 0.1
B
P=0.5×5
(Unit : mm)
Package
GUW:
VBGA035W040
<Tape and Reel information>
Embossed carrier tape (with dry pack)Tape
Quantity
Direction
of feed
2500pcs
E2
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
1pin
Packaging and forming specification
E2: Embossed tape and reel
Order quantity needs to be multiple of the minimum quantity.
∗
Direction of feed
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2009.09 - Rev.A
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other par ties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
Notice
The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specied in this document are not designed to be radiation tolerant.
While ROHM always makes ef forts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specied herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
www.rohm.com
© 2009 ROHM Co., Ltd. All rights reserved.
http://www.rohm.com/contact/
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