ROHM BU7964GUW Technical data
MSDL (Mobile Shrink Data Link) Transceivers for Mobile Phones
Data rate 1350Mbps
RGB Interface
BU7964GUW
●Description
BU7964GUW is a differential serial interface connecting mobile phone LCD modules to the host CPU. Unique technology is
utilized for lower power consumption and EMI. MSDL minimizes the number of wires required - an important consideration
in hinge phones - resulting in greater reliability and design flexibility.
●Features
1) MSDL3 high-speed differential interface with a maximum transfer rate of 1350 Mbps.
2) Compatible with24-bit RGB video mode for LCD controller-to-LCD interface.
3) Pixel clock frequency range from 4 to 45MHz.
4) Depending on the data transfer rate, either, two or three differential data channels can be selected.
●Applications
Serial Interface for LCD Display Interface of Mobile Devices Application.
●Absolute Maximum Ratings
Parameter Symbol Ratings Unit Remarks
Power Supply Voltage
Input Voltage VIN
Output Voltage VOUT
Input Current IIN -10 ~ +10 mA -
Output Current IOUT -70 ~ +70 mA -
Preservation Temperature Tstg -55 ~ +125 ℃ -
●Operating Conditions
Parameter Symbol
Supply Voltage for DVDD V
Supply Voltage for MSVDD V
Data Transmission Rate DR 120 - 450 Mbps/ch -
Operating Temperature Range T
DVDD -0.3 ~ +2.5 V -
MSVDD -0.3 ~ +2.5 V -
-0.3 ~ MSVDD+0.3 V I/O terminals of MSVDD line
-0.3 ~ DVDD+0.3 V I/O terminals of DVDD line
-0.3 ~ MSVDD+0.3 V I/O terminals of MSVDD line
-0.3 ~ DVDD+0.3 V I/O terminals of DVDD line
Ratings
Min Typ Max
1.65 1.80 1.95 V
DVDD
1.65 1.80 1.95 V
MSVDD
-30 25 85 ℃ -
opr
Unit Conditions
= V
V
DVDD
No.10058EAT04
MSVDD
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
1/18
2010.04 - Rev.A
BU7964GUW
●Package View
MARK
0.75±0.1
63-φ0.295±0.05
M
0.05
1PIN
0.08 S
S
AB
BU7964
LOT NO.
5.0±0.1
A
P = 0.5×7
0.5
H
G
F
E
D
C
B
A
23456
1
Fig.1. Package View (VBGA063W50)
78
Technical Note
5.0±0.1
0.9 MAX
S
0.10
0.75±0.1
B
P = 0.5×7
(UNIT:mm)
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
2/18
2010.04 - Rev.A
BU7964GUW
●Block Diagram
D 0
-
D 0
+
MSVDD
High Speed I/F
Technical Note
DVDD
D 1
D 1
D 2
D 2
CLK
CLK
DRVR
-
+
-
+
-
+
Link
Monitor
Reference
Serial
to
Parallel
PLL
Reset
Generator
Error
Detection
Timing
Generator
Control
Logic
I / F
Logic
PCLK
Control
PD
CPO
PCLK
XSD
LS
F_XS
PLLBW
TEST
DGNDMSGND
Fig.2. Block Diagram
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
3/18
2010.04 - Rev.A
BU7964GUW
●Pin Layout
1 2 3 4 5 6 7 8
A TEST0 PD19 PD17 PD16 PD14 PD13 PD10 CPO
B PCLK PD18 PD15 PD12 PD11 PD9 PD8
C PD22 PD20 PLL_BW0 DVDD N.C. F_XS PD7 PD6
D PD23 PD21 N.C. DGND DGND DVDD PD4 PD5
E PD25 PD24 DVDD DGND MSGND N.C. PD1 PD3
Technical Note
F PD26 LS0 MSVDD MSGND MSVDD N.C. XSD PD2
G LS1 PLL_BW1 D2- D1- CLK- D0- N.C. PD0
H N.C. N.C. D2+ D1+ CLK+ D0+ DRVR TEST1
Fig.3. Pin Layout (Top View)
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
4/18
2010.04 - Rev.A
BU7964GUW
●Pin Functions
Power Supply / Ground: 10-pin
Name Width Functions
DVDD 3 Logic core, CMOS I/O power supply.
MSVDD 2 Analog core power supply.
DGND 3 CMOS I/O and logic core ground.
MSGND 2 Analog core ground.
High-Speed Serial Interface: 8-pin
Name Width Level I/O Functions Shutdown
CLK+ 1 Analog I CLK+pin. Pull Down D
CLK- 1 Analog I CLK-pin. Pull Down D
D0+ 1 Analog I D0+pin. Pull Down D
Technical Note
Table 1. Power Supply and Ground
Table 2. MSDL3
Equivalent
Schematic
D0- 1 Analog I D0-pin. Pull Down D
D1+ 1 Analog I D1+pin. Pull Down D
D1- 1 Analog I D1-pin. Pull Down D
D2+ 1 Analog I D2+pin. Pull Down D
D2- 1 Analog I D2-pin. Pull Down D
Table 3. Analog
Analog: 1-pin
Name Width Level I/O Functions Shutdown
DRVR 1 Analog -
Parallel Data Interface: 29-pin
Name Width Level I/O Functions Shutdown
PCLK 1 CMOS O PCLK interface. ‘L’ C
PD[26:0] 27 CMOS O Parallel data interface. ‘L’ C
CPO 1 CMOS O
10kΩ ± 5% register should be connected between
DRVR and MSGND.
Table 4. Parallel Data Interface
Parity error toggled output, normally ‘L,’ output is
toggled during one PCLK period when a parity error
is detected
- D
‘L’ C
Equivalent
Schematic
Equivalent
Schematic
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
5/18
2010.04 - Rev.A
BU7964GUW
A
Name Width Level I/O Functions Shutdown
XSD 1 CMOS I
Table 5. Control
Control: 8-pin
Shutdown pin.
‘L’: shutdown.
‘H’: normal operation.
Technical Note
Equivalent
Schematic
Input A
LS0 1
CMOS I
LS1 1
F_XS 1 CMOS I
PLL_BW0 1
CMOS I Selection of PLL bandwidth. Input A
PLL_BW1 1
TEST0 1
Pull
down
TEST1 1 B
B C
DVDD
Selection of the number of data channel and the
data format. Refer to section 0.
* Set the same number of data channel bet
wean the TX device and the RX device.
Selection of CMOS output rising and falling slope
‘L’: slow
‘H’: fast
Test mode pins.
‘L’: normal mode.
I
‘H’: test mode.
Must be open or ‘L.’
DVDD
Fig.4. Equivalent Schematics
DVDD
Input A
Input A
B
Input
MSVDD
D
www.rohm.com
© 2010 ROHM Co., Ltd. All rights reserved.
6/18
2010.04 - Rev.A
Loading...