·Maximum transmission rate of highspeed differential interface MSDL3 is 900Mbps.
·Support LCD interface with 24bit parallel RGB video mode.
·Pixel clock frequency is 4~30MHz
Absolute maximum
1.
Parameter SymbolRated valuesUnitRemarks
Power supply voltage for IOVDD IOVDD-0.3 ~ +4.5 V
Power supply voltage for DVDD DVDD -0.3 ~ +2.5 V
Power supply voltage for MSVDD MSVDD-0.3 ~ +2.5 V
-0.3 ~ IOVDD+0.3 V I/O terminals of IOVDD line
Input voltage VIN
Input current IIN -10 ~ +10 mA
Package power dissipation Pd 300 * mW Without board mounted
Preservation temperature Tstg -55 ~ +125
*
When it uses by Ta=25oC or higher, reduce by 3.0 mW/°C (for a single package).
-0.3 ~ +3.6 V XSD terminal
-0.3 ~ MSVDD+0.3 V I/O terminals of MSVDD line
°C
Operating Condition
2.
Paramete
Supply voltage for IOVDD VIOVDD1.651.803.60V
Supply voltage for DVDD VDVDD1.651.801.95V
Supply voltage for MSVDD VMSVDD1.651.801.95V
SubLVDS data rate DR 120- 450 Mbps/ch
Operating temperature range Topr -3025 +85
These goods are specific machines. Because the exclusive goods which are specially designed for the device are
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As for contents of mention of these materials. A service in the foreign exchange and foreign trade control law
(Technology in the design, the manufacture and the use). Be careful of handling because it is likely to correspond.
This product is not designed against radioactive ray.
SymbolMinTypMaxUnitRemarks
VDVDD=VMSVDD≤VIOVDD
°C
REV. A
2/4
r
r
ELECTRICAL CHARACTERISTICS
3.
3.1 CMOS INOUT CHARACTERISTICS
Ta =2 5℃, DVDD=MSVDD=1.80V, IOVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted
Parameter Symbol MinTypMaxUnit Conditions
‘L’ input voltage1 VIL1 DGND - 0.3*IOVDD V
‘H’ input voltage1 VIH1 0.7*IOVDD - IOVDD V
‘L’ input voltage2 VIL2 MSGND - 0.3*MSVDDV
‘H’ input voltage2 VIH2 0.7*MSVDD- MSVDD V
‘H’ input voltage3 VIH3 0.7*IOVDD - 3.6 V XSD terminal
‘L’ output voltage1 VOL1 DGND - 0.3*IOVDD V IO=1mA
‘H’ output voltage1 VOH1 0.7*IOVDD - IOVDD V IO=-1mA
‘L’ output voltage2 VOL2 DGND - 0.3*IOVDD V IO=3mA
‘H’ output voltage2 VOH2 0.7*IOVDD - IOVDD V IO=-3mA
PCLK frequency1 fPCLK1 4.0 - 15.0 MHz LS0=L
PCLK frequency2 fPCLK2 8.0 - 30.0 MHz LS0=H
POL_PCLK,
PLL_BW[1:0],
LS0, F_XS, TEST3
terminals
LS1, LS_EN terminals
F_XS=L,
PCLK, CPO,
PD[26:0]
terminals
F_XS=H,
PCLK, CPO,
PD[26:0]
terminals
PCLK
terminal
PCLK duty cycle DPCLKO 40 50 60 % PCLK terminal
Data setup to PCLK TDSO 10.0 - - ns
Data hold to PCLK tDHO 10.0 - - ns
PD[26:0] terminals
3.2 MSDL3 RX CHARACTERISTICS
Ta =2 5℃, DVDD=MSVDD=1.80V, IOVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted
Paramete
Differential voltage range Vdiff_rx 70 100 200 mVpp
Common mode voltage range Vcm_rx 0.6 0.9 1.2 V
RX pull down current Ipull_rx 12 30 90 μA
Threshold voltage of RX link
detection
SubLVDS data rate DR_rx 120 - 450 Mbps/ch
3.3 CURRENT COMSUMPTION
Paramete
Shutdown current Iop_sht_rx - 0.2 10.0 μAXSD=L
Standby current Iop_stb_rx - 41.8 90.0 μAXSD=H
Active current of
1ch27bit format
Active current of
2ch27bit format
Active current of
1ch13bit format
*1 : Total operating current(IDVDD+IMSVDD+IIOVDD) with PD[26:0] outputs toggling 0x2AAAAAA and 0x5555555.
*2 : Total operating current(IDVDD+IMSVDD+IIOVDD) with PD[26:15],PD[2] outputs toggling 0x0AAA and 0x1555.
SymbolMinTypMaxUnit Conditions
Vlink_rx 0.2 0.3 0.4 V
Ta =2 5℃, DVDD=MSVDD=1.80V, IOVDD=1.80V, DGND=MSGND=0.00V, unless otherwise noted
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operatingconditions, etc., can
break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any
special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety
measures including the use of fuses, etc.
(2) Operating conditions
These conditions represent a range within which characteristics can be provided approximately as
expected. The electrical characteristics are guaranteed under the conditions of each parameter.
(3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown
due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply
terminal.
(4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.In this regard,
for the digital block power supply and the analog block power supply, even though these power supplies has the same level
of potential, separate the power supply pattern for the digital block from that for the analog block, thus suppressing the
diffraction of digital noises to the analog block power supply resulting from impedance common to the wiring patterns. For
the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At
the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be
used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant.
(5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.
Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric
transient.
(6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can
break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the
terminal and the power supply or the GND terminal, the ICs can break down.
(7) Operation in strong electromagnetic field
(8) Inspection with set PCB
(9) Input terminals
(10) Ground wiring pattern
(11) External capacitor
Be noted that using ICs in the strong electromagnetic field can malfunction them.
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.
Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set
PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig.
After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition,
for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the
input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a
voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to
the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is
applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND pattern
from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that resistance to
the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the small-signal
GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration
given to a degradation in the nominal capacitance due to DC bias and changes in the capacitance due to
temperature, etc.
(12) No Connecting input terminals
In terms of extremely high impedance of CMOS gate, to open the input terminals causes unstable state. And unstable state
brings the inside gate voltage of p-channel or n-channel transistor into active. As a result, battery current may increase. And
unstable state can also causes unexpected operation of IC. So unless otherwise specified, input terminals not being used
should be connected to the power supply or GND line.
REV. A
Notes
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