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◇Structure Silicon Monolithic integrated circuit
◇Product name Audio interface LSI
◇Type BU76310AGU
◇Applications DVC, DSC, etc
◇Functions ＜Audio part＞
・Stereo 16 bit ΔΣCODEC
・2-input stereo selector
・Stereo microphone amplifier with ALC function
・Stereo line amplifier
・BTL output speaker amplifier (400mW@8Ω, THD+N=10%, VDD=3.3V)
・64-step electronic volume with ALC function
・PLL built-in（Reference clock：12MHz、24MHz、27MHz、16fs、32fs、64fs）
＜PLL mode＞ 8kHz, 11.025 kHz, 12 kHz, 16 kHz
22.05 kHz, 24kHz, 32kHz, 44.1kHz, 48 kHz
＜non-PLL mode＞ 8kHz ～ 48kHz
・Master clock output
Three-line serial interface （power on reset function）
Audio IF format MSB First,2’s compliment
＜ADC＞ 16bit word lengths Left justified, I
＜DAC＞ 16bit word lengths Left, Right justified, I
◇Absolute maximum ratings （Ta=25℃）
Parameter Symbol Limits Unit Comment
Supply voltage VDD -0.3～4.5 Ｖ AVDD、DVDD、SPVDD
Input voltage VIN -0.3～supply voltage +0.3 Ｖ keep each limits upon
Storage temperature range TSTG -50～125 ℃
Operating temperature range TOPE -20～85 ℃
Power dissipation *1 PD 920*1 ｍＷ
＊１：In the case of use at Ta=25℃ or more, 9.2mW should be reduced per 1℃.
Radiation resistance design is not arranged.
◇Operating conditions （Ta=25℃）
Parameter Symbol Limits Unit Comment
Supply voltage VDD 2.7～3.6 Ｖ AVDD、DVDD、SPVDD
（note） AVDD、DVDD、SPVDD、are not needed to be same voltage.
（note） Please do not set SPVDD lower than AVDD-0.3V.
（note） Please do not surpass package permissible loss, when SPVDD is set.
2
S DSP
2
S DSP
REV. A
2/4
S
SC
CS
◇Electrical characteristics
（Unless specified, Ta=25℃、AVDD=SPVDD=DVDD= 3.3V、AVSS=SPVSS=DVSS= 0V、B.W.=22Hz～22kHz、fs=48kHz、fin=1kHz）
Parameter Symbol Limits Unit Condition
MIN. TYP. MAX.
< Current consumption > #MASTER=0 MCLK=24MHz
Power-down mode IDDS - 0.03 0.1 ｍＡ #PWAP=0
Rec mode/PLL mode IDDR - 10.3 19 ｍＡ #MDREC=MDPLL=1
Play mode/PLL mode IDDP - 8.4 16 ｍＡ #MDPB=MDSP=MDPLL=1
<ＭＲＥＧ>
output voltage VOREG 0.75AVDD-0.2 0.75AVDD 0.75AVDD+0.2 Ｖ 2.2kΩ load
< Logic interface >
Ｌ input voltage VIL DVSS － 0.3DVDD V
Ｈ input voltage VIH 0.7DVDD － DVDD V
Ｌ Input current IIL － － 10 μA
Ｈ Input current IIH － － 10 μA
Ｌ output voltage VOL 0 － 0.5 V IOL=-1mA
Ｈ output voltage VOH DVDD-0.5 － DVDD V IOL=1mA
<REC path （MICIN→ADOUT）> #ALC1=OFF, MGAIN=42dB, MLIM=-37.5dB, DVOL=-4.5dB
Distortion THD+N 62 72 - dB DOUT=-10dBFS@1kHz
ＳＮＲ SNR 78 88 - dB B.W.=JIS-A
<REC path （MICIN→ADOUT）> #ALC1=OFF, MGAIN=48dB
Input impedance ZIN 70 100 130 kΩ
Input level VIN -52 -50 -48 dBV DOUT=0dBFS
L/R gain mismatch △GV -1.0 0 +1.0 dB DOUT=0dBFS
Distortion THD+N 43 58 - dB DOUT=-6dBFS@1kHz
ＳＮＲ SNR 60 66 - dB B.W.=JIS-A
L/R separation SEPR 58 83 - dB DOUT=-6dBFS@1kHz
ＡＬＣ１ output level DOALC - -7.3 - dBFS ALC1=ON
<PB path1 （DAIN→LINEOUT）> #LGAIN=+5dB
Output level VO -5.5 -4.0 -2.5 dBV DIN=-6dBFS
L/R gain mismatch △GV -1.0 0 +1.0 dB DIN=-6dBFS
Distortion THD+N 70 80 - dB DIN=-6dBFS@1kHz
ＳＮＲ SNR 82 90 - dB B.W.=JIS-A
L/R separation SEPR 80 100 - dB DIN=-6dBFS@1kHz
<PB path2 （DAIN→EVROUT→SPIN→SPOUT BTL output）> #ALC2=OFF, EVR=-6dB, RL=8Ω
Output level VO 1.0 3.0 5.0 dBV DIN=0dBFS
Distortion THD+N 50 60 - dB DIN=0dBFS@1kHz
ＳＮＲ SNR 76 83 - dB B.W.=JIS-A
ＡＬＣ２ output level VOALC 1.0 3.0 5.0 dBV ALC2=ON, EVR=8dB
<PB path3 （BEEPIN→SPOUT BTL output）> #BVOL=13.5dB, RL=8Ω
Output level GV 11.5 13.5 15.5 dB
Input impedance ZIN 25 41 60 dB
（note） Input level of REC is relative to AVDD.
（note） Output level of PB is relative to AVDD.
（note） Input impedance oｆ BEEPIN is changed to 20kΩ～163kΩ by BVOL.
（note） Output level 3.0dBV of SPPOS/SPNEG is about 250mW at RL=8Ω.
◇
Serial interface
Control commands are entered on the SEN, SCLK, and SDATA pins, using 3 line 16 bit serial input (MSB first).
The input cycle is started on the CSB falling edge, and each bit of data is read in on the SCLK rising edge.
The data is loaded to register on the CSB rising edge.
B
LK
DATA
“x”
1 0 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
Register Address : A5 - A0
Control Data : D7 - D0
“x”
◇Register map
REV. A
3/4
Address Register
00H
01H
03H
04H
05H
06H
07H
08H
09H
0AH
0BH
0CH
0DH
0EH
0FH
10H
12H
13H
17H
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
20H
21H
22H
23H
24H
25H
26H
27H
28H
29H
2AH
2BH
（note） Do not write to the address except for the above.
Power control
Power control
Gain control
Gain control
Clock control
Clock control
Clock control
ALC control
ALC control
ALC control
Time control
Volume control
Filter control
Volume control
Volume control
Volume control
Fade control
ALC control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
Filter control
D7 D6 D5 D4 D3 D2 D1 D0
0 PWSV PWAP PWMRG 0 0 0 PWDRG
0 COMENB 0 0 MDSP MDPB MDREC MDPLL
0 0 ADA 0 0 LGAIN MGAIN1 MGAIN0
SLMIN1 SLMIN0 0 0 MUSP MUBSP MULO MUDVL
FMCK1 FMCK0 FBCK1 FBCK0 0 DIF2 DIF1 DIF0
0 FRCK2 FRCK1 FRCK0 SFS1 SFS0 DIV1 DIV0
MASTER BFPD 0 DLEN 0 MCKO 0 0
0 MDALC1 MDEVR1 MDEVR0 0 0 0 MDDVL
ATMC1 ATMC0 RCMC1 RCMC0 ATSP1 ATSP0 RCSP1 RCSP0
RC2MC1 RC2MC0 CVRG1 CVRG0 RCLM 0 0 0
RINI2 RINI1 RINI0 PINI1 PINI0 0 DVLT EVRT
0 MLIM6 MLIM5 MLIM4 MLIM3 MLIM2 MLIM1 MLIM0
0 0 DEM1 DEM0 HPFR3 HPFR2 HPFR1 HPFR0
DVOL7 DVOL6 DVOL5 DVOL4 DVOL3 DVOL2 DVOL1 DVOL0
0 0 EVR5 EVR4 EVR3 EVR2 EVR1 EVR0
0 0 SPVOL1 SPVOL0 0 BVOL2 BVOL1 BVOL0
0 0 0 0 DVLSK DVLT2 DVLT1 DVLT0
0 0 0 0 0 ATTO 0 0
DFMRP OLDFM 0 DFMEN4 DFMEN3 DFMEN2 DFMEN1 DFMEN0
DF0M1 DF0M0 DF0A13 DF0A12 DF0A11 DF0A10 DF0A9 DF0A8
DF0A7 DF0A6 DF0A5 DF0A4 DF0A3 DF0A2 DF0A1 DF0A0
0 0 DF0B13 DF0B12 DF0B11 DF0B10 DF0B9 DF0B8
DF0B7 DF0B6 DF0B5 DF0B4 DF0B3 DF0B2 DF0B1 DF0B0
DF1M1 DF1M0 DF1A13 DF1A12 DF1A11 DF1A10 DF1A9 DF1A8
DF1A7 DF1A6 DF1A5 DF1A4 DF1A3 DF1A2 DF1A1 DF1A0
0 0 DF1B13 DF1B12 DF1B11 DF1B10 DF1B9 DF1B8
DF1B7 DF1B6 DF1B5 DF1B4 DF1B3 DF1B2 DF1B1 DF1B0
DF2M1 DF2M0 DF2A13 DF2A12 DF2A11 DF2A10 DF2A9 DF2A8
DF2A7 DF2A6 DF2A5 DF2A4 DF2A3 DF2A2 DF2A1 DF2A0
0 0 DF2B13 DF2B12 DF2B11 DF2B10 DF2B9 DF2B8
DF2B7 DF2B6 DF2B5 DF2B4 DF2B3 DF2B2 DF2B1 DF2B0
DF3M1 DF3M0 DF3A13 DF3A12 DF3A11 DF3A10 DF3A9 DF3A8
DF3A7 DF3A6 DF3A5 DF3A4 DF3A3 DF3A2 DF3A1 DF3A0
0 0 DF3B13 DF3B12 DF3B11 DF3B10 DF3B9 DF3B8
DF3B7 DF3B6 DF3B5 DF3B4 DF3B3 DF3B2 DF3B1 DF3B0
DF4M1 DF4M0 DF4A13 DF4A12 DF4A11 DF4A10 DF4A9 DF4A8
DF4A7 DF4A6 DF4A5 DF4A4 DF4A3 DF4A2 DF4A1 DF4A0
0 0 DF4B13 DF4B12 DF4B11 DF4B10 DF4B9 DF4B8
DF4B7 DF4B6 DF4B5 DF4B4 DF4B3 DF4B2 DF4B1 DF4B0
◇Pin Functional Descriptions
No Pin name Function No
C6 LNFR NF input for MIC Rch E5 SPVDD
D4 MICINR2 MIC Rch input2 F5 SPPOS
D3 MICINR1 MIC Rch input1 E4 BEEPIN BEEP input
E2 MREG
E1 MICINL1 MIC Lch input1 B6 DREG LDO18 output (1.8V)
D5 MICINL2 MIC Lch input2 B1 DVDD
D2 LNFL NF input for MIC Lch A5 DAIN
D1 BIAS
C1,F1 AVSS
F2 AVDD
C5 LINEOUTR LINE Rch output A4 MCLK
F3 LINEOUTL LINE Lch output C2,A1,A6 DVSS
F4 EVROUT EVR output B5 SDATA
E3 SPIN SP input B4 SCLK
D6 SPNEG SP negative output C4 CSB
E6,F6 SPVSS SP ground - - -
MIC power supply
Bias （1/2AVDD）
Analog ground
Analog power supply
REV. A
Pin
name
B2 MCLKO
A2 ADOUT
A3 BCLK
B3 LRCLK
Function
SP power supply
SP positive output
CODEC master clock input
Digital power supply
CODEC DA serial data input
CODEC AD serial data output
CODEC bit clock in/output
CODEC LR clock in/output
CODEC master clock output
Digital ground
3-wire serial data input
3-wire serial clock input
3-wire serial chip select input
4/4
◇Block diagram・External dimensions
BIAS
LNFL
MICINL1
MICINL2
MICINR2
MICINR1
LNFR
SCLK
CSB
SDATA
MREG
ALC1ALC1
＋
ADCDAC
Digital Filte rs
Audio Interface
Control
PLL
LDO18
(DREG)
DVDD
DVSS
DREG
MCLK
LRCLK
BCLK
ADOUT
DAIN
MCLKO
1PIN MARK
76310A
U76280
Lot. No.
3.1±0.05
AVSS
AVDD
LINEOUTR
LINEOUTL
EVROUT
SPIN
BEEPIN
BIAS
EVR
ALC2
＋
SPNEG
(Note) Place the capacitors for AVDD, BIAS pins close to each
SPVDD
SPPOS
SPVSS
Figure1 Block diagram
AVSS AVDD LINEOUTL EVROUT SPPOS SPVSS
F
MICINL1 MREG SPIN BEEPIN SPVDD SPVSS
E
BIAS LNFL MICINR1 MICINR2 MICINL2 SPNEG
D
AVSS DVSS CSB LINEOUTR LNFR
C
DVDD MCLKO FCLK SCLK SDATA DREG
B
DVSS ADOUT BCLK MCLK DAIN DVSS
A
123456
35
34-φ0.30±0.05
0.05
(φ0.15) INDEX POST
A
B
F
E
D
C
0.3±0.05
B
A
1234
P=0.5×5
S0.06
A
B
56
Figure2 Pin assign (bottom face) Figure3 External dimension（Unit：ｍｍ）
◇Caution
（１） About absolute maximum rating
Please design overheating malfunction preventive circuit with an enough margin in consideration of a permissible loss in the state of using actually.
Use in strong electromagnetic field has the possibility of malfunctioning and evaluate it enough, please.
When the absolute maximum rating such as the applied voltage and the ranges of the operating temperature is exceeded, LSI might be destroyed.
Please apply neither voltage nor the temperature that exceeds the absolute maximum rating.
Please execute physical measures for safety such as fuse when it is thought to exceed the absolute maximum rating, and examine it so that
the condition to exceed the absolute maximum rating is not applied to LSI.
（２） About GND Voltage
In any state of operation must be the lowest voltage about the voltage of the terminal GND. Please actually confirm the voltage of each terminal
is not a voltage that is lower than the terminal GND including excessive phenomenon.
（３） About design of overheating malfunction preventive circuit
（４） About the short between terminals and the mounting by mistake
Please note the direction and the gap of position of LSI enough about LSI when you mount on the substrate. LSI might be destroyed when mounting
by mistake and energizing. Moreover, LSI might be destroyed when short-circuited by entering of the foreign substances between the terminal
and GND, between terminals, between the terminal and the power supply of LSI.
（５） About operation in strong electromagnetic field
（６） Please note not to be beyond the package permissible range, When SPVDD is set.
（７） No guarantee connection for A1, A6, F1 and F6. Please connect another pin of same name, too.
（８） About operation in strong light
Use in strong light has the possibility of malfunctioning. Please shield from the light, if needed.
3.1±0.05
0.25±0.1
0.3±0.05
P=0.5×5
1.0MAX
S
REV. A
Notes
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A
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