●Description
Low Voltage CMOS Op-Amp integrates one or two independent outputs full swing Op-Amps and phase compensation
capacitors on a single chip. Especially, this series is operable with low voltage, low supply current and low input bias current.
Note: Absolute maximum rating item indicates the condition which must not be exceeded.
Application of voltage in excess of absolute maximum rating or use out absolute maximum rated temperature environment
may cause deterioration of characteristics.
(*1) The voltage difference between inverting input and non-inverting input is the differential input voltage.
Then input terminal voltage is set to more than VSS.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
●Electrical characteristics
○BU7461 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])
Limits
Parameter Symbol
Temperature
Range
Unit Condition BU7461G, BU7461SG
Min. Typ. Max.
Technical Note
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
(*2)
Vio 25℃ - 1 6 mV -
(*2)
Iio 25℃ - 1 - pA -
(*2)
Ib 25℃ - 1 - pA -
(*3)
IDD
25℃ - 150 350
Full range- - 450
RL=∞ All Op-Amps
μA
AV=0[dB], VIN=0.9[V]
High Level Output Voltage VOH 25℃ VDD-0.1- - V RL=10[kΩ]
Low Level Output Voltage VOL 25℃ - - VSS+0.1V RL=10[kΩ]
Large Signal Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode
Voltage Range
Common-mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Source Current
(*4)
IOH 25℃ 4 8 - mA VDD-0.4[V]
Vicm 25℃0 - 1.8 V VSS ~ VDD-1.2[V]
CMRR 25℃ 45 60 - dB -
PSRR 25℃ 60 80 - dB -
Output Sink Current
(*4)
IOL 25℃ 6 12 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 1.0 - V/μs CL=25[pF]
Gain Band width FT 25℃ - 1 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50 - ° CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %
(*2) Absolute value
(*3) Full range: BU7461: Ta=-40[℃] to +85[℃] BU7461S: Ta=-40[℃] to +105[℃]
(*4) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
○BU7462 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])
Limits
Parameter Symbol
Temperature
Range
BU7462F/FVM/NUX
BU7462S F/FVM/NUX
Unit Condition
Min. Typ. Max.
Technical Note
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
(*5)
Vio 25℃ - 1 6 mV -
(*5)
Iio 25℃ - 1 - pA -
(*5)
Ib 25℃ - 1 - pA -
(*6)
IDD
25℃ - 300 700
Full range- - 900
RL=∞ All Op-Amps
μA
AV=0[dB], VIN=0.9[V]
High Level Output Voltage VOH 25℃ VDD-0.1- - V RL=10[kΩ]
Low Level Output Voltage VOL 25℃ - - VSS+0.1V RL=10[kΩ]
Large Signal Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode
Voltage Range
Common-mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Source Current
(*7)
IOH 25℃ 4 8 - mA VDD-0.4[V]
Vicm 25℃0 - 1.8 V VSS ~ VDD-1.2[V]
CMRR 25℃ 45 60 - dB -
PSRR 25℃ 60 80 - dB -
Output Sink Current
(*7)
IOL 25℃ 6 12 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 1.0 - V/μs CL=25[pF]
Gain Band width FT 25℃ - 1 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50 - ° CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %
VOUT=1[Vp-p] ,
f=1[kHz]
Channel Separation CS 25℃ - 100 - dB AV=40[dB]
(*5) Absolute value
(*6) Full range: BU7261, BU7262: Ta=-40[℃] to +85[℃] BU7462S: Ta=-40[℃] to +105[℃]
(*7) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
○BU7464 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])
Limits
Parameter Symbol
Temperature
Range
BU7464F
BU7464SF
Unit Condition
Min. Typ. Max.
Technical Note
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
(*5)
Vio 25℃ - 1 6 mV -
(*5)
Iio 25℃ - 1 - pA -
(*5)
Ib 25℃ - 1 - pA -
(*6)
IDD
25℃ - 600 1400
Full range- - 1800
RL=∞ All Op-Amps
μA
AV=0[dB], VIN=0.9[V]
High Level Output Voltage VOH 25℃ VDD-0.1- - V RL=10[kΩ]
Low Level Output Voltage VOL 25℃ - - VSS+0.1V RL=10[kΩ]
Large Signal Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode
Voltage Range
Common-mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Source Current
(*7)
IOH 25℃ 4 8 - mA VDD-0.4[V]
Vicm 25℃0 - 1.8 V VSS ~ VDD-1.2[V]
CMRR 25℃ 45 60 - dB -
PSRR 25℃ 60 80 - dB -
Output Sink Current
(*7)
IOL 25℃ 6 12 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 1.0 - V/μs CL=25[pF]
Gain Band width FT 25℃ - 1 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50 - ° CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %
VOUT=0.8[Vp-p],
f=1[kHz]
Channel Separation CS 25℃ - 100 - dB AV=40[dB]
(*8) Absolute value
(*9) Full range: BU7464: Ta=-40[℃] to +85[℃] BU7464S: Ta=-40[℃] to +105[℃]
(*10) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
○BU7465 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])
Limits
Parameter Symbol
Temperature
Range
BU7465HFV
BU7465SHFV
Unit Condition
Min. Typ. Max.
Technical Note
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
(*5)
Vio 25℃ - 1 6 mV -
(*5)
Iio 25℃ - 1 - pA -
(*5)
Ib 25℃ - 1 - pA -
(*6)
IDD
25℃ - 120 300
Full range- - 400
RL=∞ All Op-Amps
μA
AV=0[dB], VIN=0.9[V]
High Level Output Voltage VOH 25℃ VDD-0.1- - V RL=10[kΩ]
Low Level Output Voltage VOL 25℃ - - VSS+0.1V RL=10[kΩ]
Large Signal Voltage Gain AV 25℃ 60 100 - dB RL=10[kΩ]
Input Common-mode
Voltage Range
Common-mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Source Current
(*7)
IOH 25℃ 4 8 - mA VDD-0.4[V]
Vicm 25℃0 - 1.8 V VSS ~ VDD-1.2[V]
CMRR 25℃ 45 60 - dB -
PSRR 25℃ 60 80 - dB -
Output Sink Current
(*7)
IOL 25℃ 9 18 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 1.0 - V/μs CL=25[pF]
Gain Band width FT 25℃ - 1.2 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 60 - ° CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %
(*11) Absolute value
(*12) Full range: BU7465: Ta=-40[℃] to +85[℃] BU7465S: Ta=-40[℃] to +105[℃]
(*13) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
(*14) Absolute value
(*15) Full range: BU7441: Ta=-40[℃] to +85[℃] BU7441S: Ta=-40[℃] to +105[℃]
(*16) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
(*17) Absolute value
(*18) Full range: BU7442: Ta=-40[℃] to +85[℃] BU7442S: Ta=-40[℃] to +105[℃]
(*19) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
○BU7444 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])
Limits
Parameter Symbol
Temperature
Range
Unit Condition BU7444F, BU7444SF
Min. Typ. Max.
Technical Note
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
(*20)
Vio 25℃ - 1 6 mV -
(*20)
Iio 25℃ - 1 - pA -
(*20)
Ib 25℃ - 1 - pA -
(*21)
IDD
25℃ - 200 480
Full range- - 960
μA
RL=∞ All Op-Amps
AV=0[dB], VIN=0.9[V]
High Level Output Voltage VOH 25℃ VDD-0.1- - V RL=10[kΩ]
Low Level Output Voltage VOL 25℃ - - VSS+0.1V RL=10[kΩ]
Large Signal Voltage Gain AV 25℃ 70 95 - dB RL=10[kΩ]
Input Common-mode
Voltage Range
Common-mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Source Current
(*22)
Vicm 25℃ 0 - 1.8
CMRR 25℃ 45 60 -
V VSS ~ VDD-1.2[V]
dB -
PSRR 25℃ 60 80 - dB -
IOH 25℃ 3 6 - mA VDD-0.4[V]
Output Sink Current
(*22)
IOL 25℃ 5 10 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 0.3 - V/μs CL=25[pF]
Gain Band width FT 25℃ - 0.6 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 50 - °CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %
VOUT=0.8[Vp-p],
f=1[kHz]
Channel Separation CS 25℃ - 100 - dB AV=40[dB]
(*20) Absolute value
(*21) Full range: BU7444: Ta=-40[℃] to +85[℃] BU7444S: Ta=-40[℃] to +105[℃]
(*22) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
○BU7445 family (Unless otherwise specified VDD=+3[V], VSS=0[V], Ta=25[℃])
Limits
Parameter Symbol
Temperature
Range
Unit Condition BU7445HFV, BU7445SHFV
Min. Typ. Max.
Technical Note
Input Offset Voltage
Input Offset Current
Input Bias Current
Supply Current
(*23)
Vio 25℃ - 1 6 mV -
(*23)
Iio 25℃ - 1 - pA -
(*23)
Ib 25℃ - 1 - pA -
(*24)
IDD
25℃ - 40 90
Full range- - 120
μA
RL=∞ All Op-Amps
AV=0[dB], VIN=0.9[V]
High Level Output Voltage VOH 25℃ VDD-0.1- - V RL=10[kΩ]
Low Level Output Voltage VOL 25℃ - - VSS+0.1V RL=10[kΩ]
Large Signal Voltage Gain AV 25℃ 60 100 - dB RL=10[kΩ]
Input Common-mode
Voltage Range
Common-mode
Rejection Ratio
Power Supply
Rejection Ratio
Output Source Current
(*25)
Vicm 25℃ 0 - 1.8
CMRR 25℃ 45 60 -
V VSS ~ VDD-1.2[V]
dB -
PSRR 25℃ 60 80 - dB -
IOH 25℃ 4 8 - mA VDD-0.4[V]
Output Sink Current
(*25)
IOL 25℃ 9 18 - mA VSS+0.4[V]
Slew Rate SR 25℃ - 0.25 - V/μs CL=25[pF]
Gain Band width FT 25℃ - 0.4 - MHz CL=25[pF], AV=40[dB]
Phase Margin θ 25℃ - 60 - °CL=25[pF], AV=40[dB]
Total Harmonic Distortion THD 25℃ - 0.05 - %
(*23) Absolute value
(*24) Full range: BU7445: Ta=-40[℃] to +85[℃] BU7445S: Ta=-40[℃] to +105[℃]
(*25) Under the high temperature environment, consider the power dissipation of IC when selecting the output current.
When the terminal short circuits are continuously output, the output current is reduced to climb to the temperature inside IC.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
●Examples of circuit
○Voltage follower
○Inverting amplifier
Vin
Fig.190 Voltage follower
R1
Vin
○Non-inverting amplifier
R1
Vin
Fig.192 Non-inverting amplifier
VDD
VSS
R2
VDD
R1//R2
Fig.191 Inverting amplifier
VSS
R2
VDD
VSS
Vout
Vout
Voltage gain is 0 [dB].
This circuit controls output voltage (Vout) equal input
voltage (Vin), and keeps V out with stable because of high
input impedance and low output impedance.
Vout is shown next formula.
Vout=Vin
For inverting amplifier, Vin is amplified by voltage gain
decided R1 and R2, and phase reversed voltage is
outputted.
Vout is shown next formula.
Vout=-(R2/R1)・Vin
Input impedance is R1.
For non-inverting amplifier, Vin is amplified by voltage
gain decided R1 and R2, and phase is same with Vin.
Vout is shown next formula.
Vout=(1+R2/R1)・Vin
Vout
This circuit realizes high input impedance because Input
impedance is operational amplifier’s input Impedance.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
A
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
●Examples of circuit
○Adder circuit
Vin1
Vin2
○Differential amplifier
Vin1
Vin2
R1
R2
Fig.193 Adder circuit
R1
R3
R4
Fig.194 Differential amplifier
R3
R2
VDD
VSS
VDD
VSS
Vout
Vout
dder circuit output the voltage that added up Input
voltage. A phase of the output voltage turns orver,
because non-inverting circuit is used.
Vout is shown next formula.
Vout = -R3(Vin1/R1+Vin2/R2)
When three input voltage is as above, it connects
with input through resistance like R1 and R2.
Differential amplifier output the voltage that
amplified a difference of input voltage.
In the case of R1=R3=Ra, R2=R4=Rb
Vout is shown next formula.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
●Description of electrical characteristics
Described here are the terms of electric characteristics used in this technical note. Items and symbols used are also shown.
Note that item name and symbol and their meaning may differ from those on another manufacture’s document or general
document.
1. Absolute maximum ratings
Absolute maximum rating item indicates the condition which must not be exce eded. Application of voltage in e xcess of absolute
maximum rating or use out of absolute maximum rated temperature environment may cause deterioration of characteristics.
1.1 Power supply voltage (VDD/VSS)
Indicates the maximum voltage that can be applied between the positive po wer supply terminal and negative po wer
supply terminal without deterioration or destruction of characteristics of internal circuit.
1.2 Differential input voltage (Vid)
Indicates the maximum voltage that can be applied between non-inverting terminal and inverting ter minal without
deterioration and destruction of characteristics of IC.
1.3 Input common-mode voltage range (Vicm)
Indicates the maximum voltage that can be applied to non-inverting terminal and inverting terminal without
deteri orat ion or destr uction of character istics. Input comm on-mode voltage range of t he maximum ratings not assures
normal operation of IC. When normal Operation of IC is desired, the input common-mode voltage of characteristics
item must be followed.
1.4 Power dissipation (Pd)
Indicates the power that can be consumed by specified mounted board at the ambient temperature 25℃(normal temperature).
As for package product, Pd is determined by the temperature that can be permitted by IC chip in the package
(maximum junction temperature) and thermal resistance of the package.
2.Electrical characteristics item
2.1 Input offset voltage (Vio)
Indicates the voltage difference between non-inverting terminal and inverting terminal. It can be translated into the
input voltage difference required for setting the output voltage at 0 [V].
2.2 Input offset current (Iio)
Indicates the difference of input bias current between non-inverting terminal and inverting terminal.
2.3 Input bias current (Ib)
Indicates the current that flows into or out of the input terminal. It is defined by the average of input bias current at
non-inverting terminal and input bias current at inverting terminal.
2.4 Circuit current (ICC)
Indicates the IC current that flows under specified conditions and no-load steady status.
2.5 High level output voltage / Low level output voltage (VOH/VOL)
Indicates the voltage range that can be output by the IC und er specified load condition. It is typically divided into
high-level output voltage and low-level output voltage. High-level output voltage indicates the upper limit of output
voltage. Low-level output voltage indicates the lower limit.
2.6 Large signal voltage gain (AV)
Indicates the amplifying rate (gain) of output voltage against the voltage difference between non-inve rting terminal
and inverting terminal. It is normally the amplifying rate (gain) with reference to DC voltage.
Av = (Output voltage fluctuation) / (Input offset fluctuation)
2.7 Input common-mode voltage range (Vicm)
Indicates the input voltage range where IC operates normally.
2.8 Common-mode rejection ratio (CMRR)
Indicates the ratio of fluctuation of input offset voltage when in-phase input voltage is changed. It is normall y the
fluctuation of DC.
CMRR = (Change of Input common-mode voltage)/(Input offset fluctuation)
2.9 Power supply rejection ratio (PSRR)
Indicates the ratio of fluctuation of input offset voltage when supply voltage is changed. It is normally the fluctuation of DC.
PSRR= (Change of power supply voltage)/(Input offset fluctuation)
2.10 Channel separation (CS)
Indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage
of driven channel.
2.11 Slew rate (SR)
Indicates the time fluctuation ratio of voltage output when step input signal is applied.
2.12 Unity gain frequency (ft)
Indicates a frequency where the voltage gain of Op-Amp is 1.
2.13 Total harmonic distortion + Noise (THD+N)
Indicates the fluctuation of input offset voltage or that of output voltage with reference to the change of output voltage
of driven channel.
2.14 Input referred noise voltage (Vn)
Indicates a noise voltage generated inside the operational amplifier equivalent by ideal voltage source connected in
series with input terminal.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
(
)
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
Technical Note
●Derating curve
Power dissipation (total loss) indicates the power that can be consumed by IC at Ta=25℃(normal temperature). IC is heated
when it consumed power, and the temperature of IC ship becomes higher than ambient temperature. T he temperature that
can be accepted by IC chip depends on circuit configuration, manufacturing process, and co nsumable power is limited.
Power dissipation is determined by the temperature allowed in IC chip (maximum junction temperature) and thermal
resistance of package (heat dissipation capability).The maximum junction temperature is typically equal to the maximum
value in the storage package (heat dissipation capability).The maximum junction temperature is typically equal to the
maximum value in the storage temperature range. Heat generated by consumed power of IC radiates from the mold resin or
lead frame of the package. The parameter which indicates this heat dissipation capability (hardness of heat release) is called
thermal resistance, represented by the symbol θj-a[℃/W]. The temperature of IC insid e the package can be estimated by
this thermal resistance. Fig.195 (a) shows the model of thermal resistance of the package. Thermal resistance θja, ambient
temperature Ta, junction temperature Tj, and power dissipation Pd can be calculated by the equation below:
θja = (Tj-Ta) / Pd [℃/W] ・・・・・ (Ⅰ)
Derating curve in Fig.195(b) indicates power that can be consumed by IC with reference to ambient temperature. Power that
can be consumed by IC begins to attenuate at certain ambient temperature. This gradient iis determined by thermal
resistance θja. Thermal resistance θja depends on chip size, power consumptio n, package, ambient temperature, package
condition, wind velocity, etc even when the same of package is used. Thermal reduction curve indicates a reference value
measured at a specified condition. Fig196 (c)-(h) show a derating curve for an example Ground Sense Low Voltage
Operation CMOS Operational Amplifiers series.
θja = ( Tj ーTa ) / Pd [℃/W]
Ambient temperature Ta [℃]
Chip surface temp er ature Tj [℃]
Power dissipation P [W]
1000
800
600
400
(a) Thermal resistance
Fig.195 Thermal resistance and derating
BU7461G(*26)
540[mW]
BU7441G(*26)
BU7465HFV(*30)
535[mW]
BU7445HFV(*30)
1000
800
600
400
P2
P1
620[mW]
480[mW]
412[mW]
[W]
Pd(max)
θja1
0
25125
7510050
Ambient temperature Ta [℃]
(b) Derating curve
BU7462F(*27)
BU7442F(*27)
BU7462FVM(*28)
BU7442FVM(*28)
BU7462NUX(*29)
BU7442NUX(*29)
1000
800
600
400
θja2 <θja1
θja2
Tj(max)
488[mW]
BU7464F(*31)
BU7444F(*31)
200
POWER DISSIPATION [mW]
0
050100150
1000
AMBIENT TEMPERATURE[℃]
(c) BU7461G BU7441G
BU7465HFV BU7445HFV
800
600
400
200
POWER DISSIPATION [mW]
85
540[mW]
535[mW]
BU7461SG(*26)
BU7441SG(*26)
BU7465SHFV(*30)
BU7455SHFV(*30)
200
POWER DISSIPATION [mW]
0
050100150
AMBIENT TEMPERATURE[℃]
85
(d) BU7462F/FVM/NUX BU7442F/FVM/NUX
620[mW]
480[mW]
412[mW]
BU7462SF(*27)
BU7442SF
*27
BU7462SFVM(*28)
BU7442SFVM(*26)
BU7462SNUX(*29)
BU7442SNUX(*29)
POWER DISSIPATION [mW]
1000
800
600
400
200
200
POWER DISSIPATION [mW]
0
050100150
AMBIENT TEMPERATURE[℃]
85
(e) BU7464F BU7444F
1000
800
600
400
200
POWER DISSIPATION [mW]
488[mW]
BU7461SG(*31)
BU7441SG(*31)
0
050100150
AMBIENT TEMPERATURE[℃]
(f) BU7461SG BU7441SG
BU7465SHFV BU7445SHFV
105
(*26) (*27) (*28)
5.4 6.2 4.8
0
050100150
AMBIENT TEMPERATURE[℃]
105
(g)BU7462S F/FVM/NUX BU7442S F/FVM/NUX
(*29)
4.12
(*30)
5.35
When using the unit above Ta=25[℃], subtract the value above per degree[℃]. Permissible dissipation is the value.
When FR4 glass epoxy board 70[mm]×70[mm]×1.6[mm] (cooper foil area below 3[%]) is mounted.
BU7461/BU7461S family, BU7441/BU7441S family, BU7462/BU7462S family, BU7442/BU7442S family
BU7464/BU7464S family, BU7444/BU7444S family, BU7465/BU7465S family, BU7445/BU7445S family
●Cautions on use
1) Absolute maximum ratings
Absolute maximum ratings are the values which indicate the limits, within which the given voltage range ca n be safely
charged to the terminal. However, it does not guarantee the circuit operation.
2) Applied voltage to the input terminal
For normal circuit operation of voltage comparator, please input voltage for its input terminal within input common mode
voltage VDD + 0.3[V]. Then, regardless of power supply voltage, VSS-0.3[V] can be applied to input terminals without
deterioration or destruction of its characteristics.
3) Operating power supply (split power supply/single power supply)
The voltage comparator operates if a given level of voltage is applied bet ween VDD and VSS. Therefore, the operational
amplifier can be operated under single power supply or split power supply.
4) Power dissipation (pd)
If the IC is used under excessive power dissipation. An increase in the chip temperatur e will cause deterioration of the
radical characteristics of IC. For example, reduction of current capability. Take consideration of the effective power
dissipation and thermal design with a sufficient margin. Pd is reference to the provided power dissipation curve.
5) Short circuits between pins and incorrect mounting
Short circuits between pins and incorrect mounting when mounting the IC on a printed circuits board, take notice of the
direction and positioning of the IC. If IC is mounted erroneously, It may be damaged. Also, when a foreign object is
inserted between output, between output and VDD terminal and VSS terminal which causes short circuit, the IC may be
damaged.
6) Using under strong electromagnetic field
Be careful when using the IC under strong electromagnetic field because it may malfunction.
7) Usage of IC
When stress is applied to the IC through warp of the printed circuit board, The characteristics may fluctuate due to the
piezo effect. Be careful of the warp of the printed circuit board.
8) Testing IC on the set board
When testing IC on the set board, in cases where the capacitor is connected to the low impedance, make sure to
discharge per fabrication because there is a possibility that IC may be damaged by stress. When removing IC from the set
board, it is essential to cut supply voltage. As a countermeasure against the static electricit y, observe proper grounding
during fabrication process and take due care when carrying and storage it.
9) The IC destruction caused by capacitive load
The transistors in circuits may be damaged when VDD terminal and VSS terminal is shorted with the charged output
terminal capacitor.When IC is used as a operational amplifier or as an application circuit, where oscillation is not activated
by an output capacitor, the output capacitor must be kept below 0.1[μF] in order to prevent the damage mentioned above.
10) Latch up
Be careful of input voltage that exceed the VDD and VSS. When CMOS device have sometimes occur latch up operation.
And protect the IC from abnormaly noise
11) Decupling capacitor
Insert the decupling capacitance between VDD and VSS, for stable operation of operational amplifier.
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