These Clock Generators incorporates compact package compared to oscillators, which provides the generation of
high-frequency CCD, USB, VIDEO clocks necessary for digital still cameras and digital video cameras.
●Features
1) SEL pin allowing for the selection of frequencies
2) Selection of OE pin enabling Power-down function
3) Crystal-oscillator-level clock precision with high C/N characteristics and low jitter
4) Micro miniature HVSOF6 Package incorporated
5) Single power supply of 3.3 V
●Applications
Digital Still Camera, Digital Video Camera, and others
Power-down function Provided Provided Provided Provided Provided Provided
Operating current (Typ.) 10mA 11mA 11mA 12mA 10mA 12mA
Package HVSOF6 HVSOF6 HVSOF6 HVSOF6 HVSOF6 HVSOF6
●Absolute Maximum Ratings(Ta=25℃)
Parameter Symbol Ratings Unit
Supply voltage VDD -0.3 ~ 4.0 V
Input voltage VIN -0.3 ~ VDD+0.3 V
Storage temperature range Tstg -30 ~ 125 ℃
Power dissipation Pd 410 mW
*1 Operating is not guaranteed.
*2 In the case of exceeding Ta = 25℃, 4.1mW should be reduced per 1℃.
*3 The radiation-resistance design is not carried out.
*4 Power dissipation is measured when the IC is mounted to the printed circuit board.
Output H voltage VOH 2.8 - - V IOH=-4.0mA
Output L voltage VOL - - 0.5 V IOL=4.0mA
Consumption current 1 IDD1 - 10 15 mA OE=H, at no load
Consumption current 2 IDD2 - 1 1.3 mA OE=L
Output frequency - 54.0000- MHzIN*264/35/4
The following parameters represent design guaranteed performance.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ PJsSD - 50 - psec※1
Period-Jitter MIN-MAX PJsABS - 300 - psec※2
Period of transition time required for the
Rise time tr - 2.5 - nsec
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Period of transition time required for the
Fall time tf - 2.5 - nsec
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time tLOCK - - 1 msec ※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 28.6363MHz, the output frequency will be as listed above.
Output H voltage VOH 2.8 - - V IOH=-4.0mA
Output L voltage VOL - - 0.5 V IOL=4.0mA
Consumption current 1 IDD1 - 11 16 mAPD=H, at no load
Consumption current 2 IDD2 - - 5 µA PD=L
The following parameters represent design guaranteed performance.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ PJsSD - 35 - psec※1
Long-Term-Jitter
MIN-MAX
LTJsABS - 0.9 1.5 nsec
MIN-MAX of long-term jitter
(100 µsec from trigger)
Period of transition time required for the
Rise time tr - 2.5 - nsec
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Period of transition time required for the
Fall time tf - 2.5 - nsec
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time tLOCK - - 1 msec ※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 48.0000MHz, the output frequency will be as listed above.
Output H voltage VOH 2.8 - - V IOH=-4.0mA
Output L voltage VOL - - 0.5 V IOL=4.0mA
Consumption current 1 IDD1 - 11 16 mAPD=H, at no load
Consumption current 2 IDD2 - - 5 mAPD=L
The following parameters represent design guaranteed performance.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ PJsSD - 45 - psec※1
Long-Term-Jitter
MIN-MAX
LTJsABS - 0.9 1.5 nsec
MIN-MAX of long-term jitter
(100 µsec from trigger)
Period of transition time required for the
Rise time tr - 2.5 - nsec
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Period of transition time required for the
Fall time tf - 2.5 - nsec
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time tLOCK - - 1 msec ※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 48.0000MHz, the output frequency will be as listed above.
Output H voltage VOH 2.8 - - V IOH=-4.0mA
Output L voltage VOL - - 0.5 V IOL=4.0mA
Pull-down resistance Rpd 25 50 100 KΩPull-down resistance on input pin
Consumption current 1 IDD1 - 10 15 mA54MHz output, at no load
Consumption current 2 IDD2 - 12 18 mA67.5MHz output, at no load
Standby current IDDst - - 1 µA OE=L
Output frequency
CLK_54 - 54.0000 - MHzSEL=L, IN*48/6/4
CLK_67.5 - 67.5000- MHzSEL=H, IN*60/6/4
The following parameters represent design guaranteed performance.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ PJsSD - 50 - psec※1
Period-Jitter MIN-MAX PJsABS - 300 - psec※2
Period of transition time required for the
Rise time tr - 1.5 - nsec
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Period of transition time required for the
Fall time tf - 1.5 - nsec
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time tLOCK - - 200 µsec※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Output H voltage VOH 2.8 - - V IOH=-4.0mA
Output L voltage VOL - - 0.5 V IOL=4.0mA
Pull-down resistance Rpd 25 50 100 kΩPull-down resistance on input pin
Consumption current 1 IDD - 10 13.5 mA49.5MHz output, at no load
Consumption current 2 IDD2 - 9.5 13.0 mA36.0MHz output, at no load
Standby current IDDst - - 1 µA OE=L
Output frequency
CLK_49.5 - 49.5000- MHzSEL=L, IN*66/6/6
CLK_36 - 36.0000 - MHzSEL=H, IN*64/6/8
The following parameters represent design guaranteed performance.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ PJsSD - 50 - psec※1
Period-Jitter MIN-MAX PJsABS - 300 - psec※2
Period of transition time required for the
Rise time tr - 2.5 - nsec
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Period of transition time required for the
Fall time tf - 2.5 - nsec
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time tLOCK - - 200 µsec※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Output H voltage VOH 2.8 - - V IOH=-4.0mA
Output L voltage VOL - - 0.5 V IOL=4.0mA
Pull-down resistance Rpd 25 50 100 kΩPull-down resistance on input pin
Consumption current 1 IDD1 - 11 15 mAOE=H, SEL=L, at no load
Consumption current 2 IDD2 - 12 16.5 mAOE=H, SEL=H, at no load
Standby current IDDst - - 1 µA OE=L
The following parameters represent design guaranteed performance.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ PJsSD - 50 - psec※1
Period-Jitter MIN-MAX PJsABS - 300 - psec※2
Period of transition time required for the
Rise time tr - 1.5 - nsec
output to reach 80% from 20% of VDD.
Provided with 15pF output load.
Period of transition time required for the
Fall time tf - 1.5 - nsec
output to reach 20% from 80% of VDD.
Provided with 15pF output load.
Output Lock time tLOCK - - 200 µsec※3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to IN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Common to BU3071HFV, BU3072HFV, BU3073HFV, BU3076HFV, BU7322HFV, BU7325HFV
※1 Period-Jitter 1σ This parameter represents standard deviation (=1σ) on cycle distribution data at the time when the output clock cycles are sampled 1000 times
consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※2 Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock cycles are sampled 1000 times
consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
※3 Output Lock Time
This parameter represents elapsed time after power supply turns ON to reach a voltage of 3.0 V, after the system is switched from Power-Down state to
normal operation state, or after the output frequency is switched, until it is stabilized at a specified frequency, respectively.
1 VDD Power supply
2 VSS GND
3 OUT Clock output terminal
4 OE Output enable (L: disable, H: enable), equipped with Pull-down function, output fixed to L at disable
5 TEST TEST pin, equipped with Pull-down function
6 IN Clock input pin (28.6363 MHz input)
For VDD and VSS, insert a bypass capacitor of approx. 0.1 µF as close as possible to the pin.
Bypass capacitors with good high-frequency characteristics are recommended.
Even though we believe that the typical application circuit is worth of a recommendation, please be sure to thoroughly recheck the characteristics before use.
1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr),
etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit.
If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical
safety measures including the use of fuses, etc.
2) Recommended operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The
electrical characteristics are guaranteed under the conditions of each parameter.
3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown
due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply
terminal.
4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.
In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has
the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus
suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the
wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At
the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to
be used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the
constant.
5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.
Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.
6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can
break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between
the terminal and the power supply or the GND terminal, the ICs can break down.
7) Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.
Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set
PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig.
After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition,
for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
9) Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the
input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a
voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to
the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is
applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current
small-signal GND. Pay attention not to cause fluctuations in the GND wiring pattern of external parts as well.
11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a
degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
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Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
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The technical information specied herein is intended only to show the typical functions of and
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Notice
The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, communication devices, electronic appliances and amusement devices).
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