ROHM BU2508FV, BU2507FV Technical data
DACs for Electronic Adjustment
High-precision 10bit
4ch/6ch D/A Converters
BU2508FV, BU2507FV
●Description
BU2508FV and BU2507FV ICs are high performance 10bit R-2R-type DACs with 4ch and 6ch outputs, respectively.
Each channel incorporates a full swing output-type buffer amplifier with high speed output response characteristics, resulting
in a greatly shortened wait time. The ICs also utilize the TTL level input method.
●Features
1) High performance, multi-channels R-2R-type 10bit D/A converter built-in
(BU2508FV: 4 channels, BU2507FV: 6 channels)
2) Full swing output type buffer amplifier incorporated at each output channel
3) The RESET terminal can keep the voltage of all channels within the lower reference voltage range
4) Digital input compatible with TTL levels
5) 14bit 3-line serial data + RESET signal input (address 4bit + data 10bit)
6) Compact package: 14 pins, 0.65mm pitch (SSOP-B14)
●Applications
DVDs, CD-Rs, CD-RWs, digital cameras
●Lineup
Parameter BU2507FV BU2508FV
Power source voltage range
Number of channels
Differential non linearity error
Integral non linearity error
Data transfer frequency
Package
●Absolute Maximum Ratings (Ta=25℃)
Parameter Symbol Ratings Unit
Power source voltage VCC -0.3 to 6.0 V
D/A converter upper standard voltage VDD -0.3 to 6.0 V
Input voltage VIN -0.3 to 6.0 V
Output voltage VOUT -0.3 to 6.0 V
4.5 to 5.5V 4.5 to 5.5V
6ch 4ch
±1.0LSB ±1.0LSB
±3.5LSB ±3.5LSB
10MHz 10MHz
SSOP-B14 SSOP-B14
No.11052ECT02
Storage temperature range Tstg -55 to 125 ℃
Power dissipation Pd 350 * mW
* Derated at 3.5mW/℃ at Ta>25℃, mounted on a 70x70x1.6mm FR4 glass epoxy board (copper foil area less than 3%)
Note: These products are not robust against radiation
●Recommended Operating Conditions (Ta=25℃)
Parameter Symbol Limits Unit
Power supply voltage range VCC 4.5 to 5.5 V
Operating temperature range Topr -30 to 85 ℃
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2011.08 - Rev.C
BU2508FV,BU2507FV
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Technical Note
●Electrical Characteristics (Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃)
Parameter Symbol
Limits
MIN. TYP. MAX.
Unit Conditions
<Digital unit>
Power source current ICC
- 0.85 2.8 mA At CLK = 10MHz, IAO = 0uA
Input leak current IILK -5 - 5 μA VIN=0 to VCC
Input voltage L VIL - - 0.8 V Input voltage H VIH 2.0 - - V Output voltage L VOL 0 - 0.4 V IOL=2.5mA
Output voltage H VOH 4.6 - 5 V IOH=-2.5mA
<Analog unit>
Consumption current IrefH
D/A converter upper standard voltage
setting range
D/A converter lower standard voltage
setting range
VrefH 3.0 - 5 V
VrefL 0 - 1.5 V
Buffer amplifier output voltage range VO
Buffer amplifier output drive range IO -2 - 2 mA
- 4.5 7.5 mA
- 2.0 3.4 mA
Data condition : at maximum current
(*1)
Outputs does not necessarily take a
value in standard voltage setting range.
Value that output may take is in the buffer
amplifier output voltage range (VO).
0.1 - 4.9
0.2 - 4.75 IO=±1.0mA
V
IO=±100μA
Upper side satu
(on full scale setting, current sourcing )
Lower side saturation voltage =0.23V
ation voltage =0.35V
(on zero scale setting, current sinking )
Precision
Differential non-linearity error DNL -1.0 - 1.0
Integral non-linearity error INL -3.5 - 3.5
Zero point error SZERO -25 - 25
Full scale error SFULL -25 - 25
LSB
mV
=4.796V
VrefH
VrefL=0.7V
VCC=5.5V (4mV/LSB)
No load (IO = +0mA)
Buffer amplifier output impedance RO - 5 15 Ω -
Input voltage 0V
Pull-up I/O internal resistance value Rup 12.5 25 37.5 kΩ
(Resistance value changes according
to voltage to be impressed.)
*1: Value in the case where CH1 ~ CH4 are set to maximum current (after reset)
●Timing Characteristics (Unless otherwise specified, VCC=5V, VrefH=5V, VrefL=0V, Ta=25℃)
Parameter Symbol
Limits
MIN. TYP. MAX.
Reset L pulse width tRTL 50 - -
Unit
Judgment level is 80% / 20% of VCC.
Conditions
Clock L pulse width tCKL 50 - - Clock H pulse width tCKH 50 - - Clock rise time tcr - - 50 Clock fall time tcf - - 50 Data setup time tDCH 20 - - -
nS
Data hold time tCHD 40 - - Load setup time tCHL 50 - - Load hold time tLDC 50 - - Load H pulse width tLDH 50 - - -
CL≦100pF, VO:0.5V⇔4.5V .
DA output settling time tLDD - 7 20 μS
Until output value deference from final
value becomes 1/2LSB
RESET
CLK
DI
LD
Output
tRTL
tcr tCKH tcf
tCKL
tDCH tCHD
tCHL
tLDC
tLDH
tLDD
(note) LD signal is level triggered. When LD input is on H level, internal shift-register state is loaded to DAC control latch.
Clock transition during LD=H is inhibited.
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© 2011 ROHM Co., Ltd. All rights reserved.
2/8
2011.08 - Rev.C
BU2508FV,BU2507FV
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Technical Note
●DAC Variable Output Range Function
With the variable output range function, the upper / lower limits of the output voltage as well as the power supply voltage can be set.
The upper limit value setting terminal VrefH is used as the power supply terminal, while the lower limit value setting terminal
VrefL is used as the GND terminal (1LSB ≒ 5mV). In the example below, VrefH = 3.5V / VrefL = 1.5V. Further adjustments
can be made in order to achieve greater accuracy (1LSB ≒ 2mV).
VOUT
5V
1024
step
ステップ
VOUT
5V
3.5V
1.5V
1024
step
ステップ
VrefH
VrefL
0V
Input Code3FFh
0V
Input Code 3FFh
1LSB≒5.0mV 1LSB≒2.0mV
●Block Diagrams
BU2507FV BU2508FV
891011121314
VCC
L
AO6LDCLKDIAO1GND
D/A
6
D13
12
11
D10
D9
8
14bit
7
6
5
シフトレジスタ
4
Shift registe
3
2
1
D0
10bit R-2R
D/Aｺﾝﾊﾞｰﾀ
DA converte
・・・
ｱﾄﾞﾚｽ
ﾃﾞｺｰﾀﾞ
decoder
Address
10bit Latch
CH1
L
D/A
5
L
D/A
4
L
D/A
3
10bit R-2R
D/Aｺﾝﾊﾞｰﾀ
10bit Latch
DA converte
CH2
Buffer
7654321
VDD
(VrefH)
AO5AO4ResetAO3AO2VSS
ﾊﾞｯﾌｧ
ｵﾍﾟｱﾝﾌﾟ
amplifier
operation
(VrefL)
891011121314
VCC
L
AO4LDCLKDIAO1GND
D/A
4
D13
12
11
D10
D9
8
14bit
7
6
5
シフトレジスタ
4
Shift register
3
2
1
D0
10bit R-2R
D/Aｺﾝﾊﾞｰﾀ
DA converte
・・・
ｱﾄﾞﾚｽ
ﾃﾞｺｰﾀﾞ
decoder
Address
10bit Latch
CH1
L
D/A
3
10bit R-2R
D/Aｺﾝﾊﾞｰﾀ
10bit Latch
DA converte
CH2
7654321
ﾊﾞｯﾌｧ
Buffer
ｵﾍﾟｱﾝﾌﾟ
amplifier
operation
VDD
(VrefH)
AO3TEST2ResetTEST1AO2VSS
(VrefL)
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© 2011 ROHM Co., Ltd. All rights reserved.
3/8
2011.08 - Rev.C
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