DVD-video Reference
Clock Generators for A/V Equipments
BU2280FV, BU2360FV, BU2362FV
●Description
These clock generators are an IC generating three types of clocks - VIDEO, AUIDIO and SYSTEM clocks – necessary for
DVD player systems, with a single chip through making use of the PLL technology. Particularly, the AUDIO clock is a
DVD-Video reference and yet achieves high C/N characteristics to provide a low level of distortion factor.
●Features
1) Connecting a crystal oscillator generates multiple clock signals with a built-in PLL.
2) AUDIO clock of high C/N characteristics providing a low level of distortion factor
3) The AUDIO clock provides switching selection outputs.
4) Single power supply of 3.3 V
●Applications
DVD players
●Lineup
Part name BU2280FV BU2360FV BU2362FV
Power source voltage [V] 3.0 ~ 3.6 2.7 ~ 3.6 2.7 ~ 3.6
*1 In the case of exceeding Ta = 25℃, 6.3mW to be reduced per 1℃
*2 In the case of exceeding Ta = 25℃, 4.5mW to be reduced per 1℃
*Operating is not guaranteed.
*The radiation-resistance design is not carried out.
*Power dissipation is measured when the IC is mounted to the printed circuit board.
VDD -0.5 ~ +7.0 -0.5 ~ +7.0 -0.5 ~ +7.0 V
VIN -0.5~VDD+0.5 -0.5~VDD+0.5 -0.5~VDD+0.5 V
Tstg
PD 630
-30 ~ +125 -30 ~ +125 -30 ~ +125 ℃
*1
450
*2
450
*2
●Recommended Operating Range
Parameter Symbol BU2280FV BU2360FV BU2362FV Unit
Parameter VDD 3.0 ~ 3.6 2.7 ~ 3.6 2.7 ~ 3.6 V
Supply voltage VIH 0.8VDD~VDD 0.8VDD~VDD 0.8VDD~VDD V
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ P-J 1σ - 70 - psec*1
Period-Jitter MIN-MAX
Rise Time Tr - 2.5 - nsec
Fall Time Tf - 2.5 - nsec
P-J
MIN-MAX
- 420 - psec*2
Period of transition time required for the
output reach 80% from 20% of VDD.
Period of transition time required for the
output reach 20% from 80% of VDD.
Output Lock-Time Tlock - - 1 msec*3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
◎BU2360FV(VDD=3.3V, Ta=25℃, Crystal frequency 27.0000MHz, unless otherwise specified.)
Parameter
Symbol
Min. Typ. Max.
Limits
Unit Conditions
Output L voltage VOL - - 0.4 V IOL=4.0mA
Output H voltage VOH 2.4 - - V IOH=-4.0mA
FSEL input VthL VthL 0.2VDD - - V *4
FSEL input VthH VthH - - 0.8VDDV *4
Hysteresis range Vhys0.2 - - V Vhys = VthH - VthL *4
Action circuit current IDD - 27.0 40.5 mA At no load
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ P-J 1σ - 70 - psec*1
Period-Jitter MIN-MAX
Rise Time Tr - 2.5 - nsec
Fall Time Tf - 2.5 - nsec
P-J
MIN-MAX
- 420 - psec*2
Period of transition time required for the
output reach 80% from 20% of VDD.
Period of transition time required for the
output reach 20% from 80% of VDD.
Output Lock-Time Tlock - - 1 msec*3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Duty Duty 45 50 55 % Measured at a voltage of 1/2 of VDD
Period-Jitter 1σ P-J 1σ - 70 - psec*1
Period-Jitter MIN-MAX
Rise Time Tr - 2.5 - nsec
Fall Time Tf - 2.5 - nsec
P-J
MIN-MAX
- 420 - psec*2
Period of transition time required for the
output reach 80% from 20% of VDD.
Period of transition time required for the
output reach 20% from 80% of VDD.
Output Lock-Time Tlock - - 1 msec*3
Note) The output frequency is determined by the arithmetic (frequency division) expression of a frequency input to XTALIN.
If the input frequency is set to 27.0000MHz, the output frequency will be as listed above.
Common to BU2280FV, BU2360FV and BU2362FV:
*1 Period-Jitter 1σ
This parameter represents standard deviation (1 ) on cycle distribution data at the time when the output clock cycles
are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
*2 Period-Jitter MIN-MAX
This parameter represents a maximum distribution width on cycle distribution data at the time when the output clock
cycles are sampled 1000 times consecutively with the TDS7104 Digital Phosphor Oscilloscope of Tektronix Japan, Ltd.
*3 Output Lock-Time
The Lock-Time represents elapsed time after power supply turns ON to reach a 3.0V voltage, after the system is
switched from Power-Down state to normal operation state, or after the output frequency is switched, until it is stabilized
at a specified frequency, respectively.
BU2360FV
4 This parameter represents lower and upper limit voltages at the Schmitt trigger input PIN having hysteresis
characteristics shown in figure below. The width requested by these differences is assumed to be a hysteresis width.
Note) Basically, mount ICs to the printed circuit board for use.
(If the ICs are not mounted to the printed circuit board, the characteristics of ICs may not be fully demonstrated.)
Mount 0.1F capacitors in the vicinity of the IC PINs between 1PIN (VDD1) and 2PIN (VSS1), 5PIN-6PIN (AVDD) and 7PIN (AVSS), 10PIN (VSS2) and
11PIN (VDD2), 13PIN(VSS2) and 14PIN (VDD2), 17PIN-18PIN (DVSS) and 19PIN(DVDD), respectively.
Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the power supply and GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU2280FV from the printed circuit board or to insert a
capacitor (of 1 or less), which bypasses high frequency desired, between the power supply and the GND terminal.
Note) Basically, mount ICs to the printed circuit board for use.
(If the ICs are not mounted to the printed circuit board, the characteristics of ICs may not be fully demonstrated.)
Mount 0.1F capacitors in the vicinity of the IC PINs between 1PIN (VDD2) and 2PIN (VSS2), 5PIN (AVDD) and 6PIN (AVSS), 11PIN (DVSS) and 12PIN
(DVDD), respectively.
Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the power supply and GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU2360FV from the printed circuit board or to insert a
capacitor (of 1 or less), which bypasses high frequency desired, between the power supply and the GND terminal.
Input pin for TEST : with pull-down
(Please set ”L” or OPEN, normally)
5 AVDD Power supply for Analog block
6 AVSS GND for Analog block
7 XTALOUT Crystal output terminal
8 XTALIN Crystal input terminal
9 CLKA CLKA output terminal (16.9344MHz or 36.8640MHz)
10 CLK512FS 512fs Clock output terminal (22.5792MHz or 24.5760MHz)
11 DVSS Power supply for Digital block
12 DVDD GND for Digital block
13 CLK16M 16.9344MHz Clock output terminal
14 FSEL1 CLKA or CLK512FS pin output select : with pull-up
15 CLK33M 33.8688MHz Clock output terminal
16 CLK36M 36.8640MHz Clock output terminal
●Notes for use (BU2362FV)
Basically, mount ICs to the printed circuit board for use. (If the ICs are not mounted to the printed circuit board, the
characteristics of ICs may not be fully demonstrated.)
Mount 0.1F capacitors in the vicinity of the IC PINs between 1PIN (VDD2) and 2PIN (VSS2), 5PIN (AVDD) and 6PIN
(AVSS), 11PIN (DVSS) and 12PIN (DVDD), respectively.
For the fine-tuning of frequencies, insert several numbers of pF in the 7PIN and 8PIN to GND.
Depending on the conditions of the printed circuit board, mount an additional electrolytic capacitor between the power supply
and GND terminal.
For EMI protection, it is effective to put ferrite beads in the origin of power supply to be fed to BU2362FV from the printed
circuit board or to insert a capacitor (of 1Ω or less), which bypasses high frequency desired, between the power supply and
the GND terminal.
*Even though we believe that the example of recommended circuit is worth of a recommendation, please be sure to thoroughly recheck the characteristics
1) Absolute Maximum Ratings
An excess in the absolute maximum ratings, such as applied voltage (VDD or VIN), operating temperature range (Topr),
etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit.
If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical
safety measures including the use of fuses, etc.
2) Recommended operating conditions
These conditions represent a range within which characteristics can be provided approximately as expected. The
electrical characteristics are guaranteed under the conditions of each parameter.
3) Reverse connection of power supply connector
The reverse connection of power supply connector can break down ICs. Take protective measures against the breakdown
due to the reverse connection, such as mounting an external diode between the power supply and the IC’s power supply
terminal.
4) Power supply line
Design PCB pattern to provide low impedance for the wiring between the power supply and the GND lines.
In this regard, for the digital block power supply and the analog block power supply, even though these power supplies has
the same level of potential, separate the power supply pattern for the digital block from that for the analog block, thus
suppressing the diffraction of digital noises to the analog block power supply resulting from impedance common to the
wiring patterns. For the GND line, give consideration to design the patterns in a similar manner.
Furthermore, for all power supply terminals to ICs, mount a capacitor between the power supply and the GND terminal. At
the same time, in order to use an electrolytic capacitor, thoroughly check to be sure the characteristics of the capacitor to be
used present no problem including the occurrence of capacity dropout at a low temperature, thus determining the constant.
5) GND voltage
Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state.
Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric
transient.
6) Short circuit between terminals and erroneous mounting
In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can
break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between
the terminal and the power supply or the GND terminal, the ICs can break down.
7) Operation in strong electromagnetic field
Be noted that using ICs in the strong electromagnetic field can malfunction them.
8) Inspection with set PCB
On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress.
Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set
PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig.
After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition,
for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the
transportation and the storage of the set PCB.
9) Input terminals
In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the
parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the
input terminal. Therefore, pay thorough attention not to handle the input terminals, such as to apply to the input terminals a
voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to
the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is
applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of
electrical characteristics.
10) Ground wiring pattern
If small-signal GND and large-current GND are provided, It will be recommended to separate the large-current GND
pattern from the small-signal GND pattern and establish a single ground at the reference point of the set PCB so that
resistance to the wiring pattern and voltage fluctuations due to a large current will cause no fluctuations in voltages of the
small-signal GND. Pay attention not to caus
11) External capacitor
In order to use a ceramic capacitor as the external capacitor, determine the constant with consideration given to a
degradation in the nominal capacitance due to DC bias and changes in the capacitance due to temperature, etc.
e fluctuations in the GND wiring pattern of external parts as well.
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