ROHM BU21008MUV Technical data

Capacitive Sensor Control IC Series

Capacitive Sensor Switch
Control IC

BU21008MUV

●Description

BU21008MUV are the capacitive sensor controller with 16 channels respectively. Half of sensor ports are available to use to
LED driver with PWM function. PWM function can control light ambient. Also gesture function can recognize the short touch,
long touch and finger motion.

●Features

1) Gesture function

2) LED driver with PWM available

3) 2 wire serial interface

4) Power supply = 2.5V to 3.3V, I/O power supply = 1.7V to 3.3V

5) Integrated 10bit AD converter, clock and reset

6) Package VQFN032V5050

●Applications

It is possible to use it widely as a switch such as a Mobile phone, Portable equipment, and Audiovisual apparatuses.

●Absolute Maximum Ratings (Ta=25℃)

PARAMETER SYMBOL

APPLIED VOLTAGE

INPUT VOLTAGE

STORAGE TEMPERATURE RANGE Tstg -55 125 ℃

POWER DISSIPATION Pd 304 mW

Ambient temperature reduces a permission loss by 3.1mW per case more than 25 degrees Celsius, 1 degree Celsius.

●Recommended Operating conditions

PARAMETER SYMBOL

APPLIED VOLTAGE

OPERATINGTEMPERATURE RANGE Topr -40 25 85 ℃

AVD D - 0 . 3 4. 5

DVDD -0.3 4.5

AIN -0.3 AVDD+0.3

V

VDIN -0.3 DVDD+0.3

AVDD 2.5 3.0 3.3 V

DVDD 1.7 3.0 3.3 V

MIN MAX

MIN TYP MAX

RATING

RATING

No.09048EBT04

UNIT

V

V

UNIT

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1/16

2009.04 - Rev.B

BU21008MUV

●Electrical characteristics(Especially, Topr=25℃ and AVDD=DVDD=0 as long as it doesn't specify it.)

PARAMETER SYMBOL

H INPUT VOLTAGE VIHIO

L INPUT VOLTAGE VILIO

Output "H" voltage VOHIO

VOLLED

Output "L" voltage

VOLTXD

VOLINT

Input leakage current IIZ

MIN TYP MAX

DVDDx0.8 - DVDD+0.3 V

DVSS-0.3

DVDD-0.7

AVSS

DVSS

DVSS

-1

RATING

-

-

-

-

-

-

UNIT Condition

DVDDx0.2 V

DVDD V

0.5

0.5

DVDDx0.3

0.5

IOH=-2[mA]. Overshoot is excluded.

I

OL=8[mA]. Undershoot is excluded. LED output.

I

OL=3[mA]. Undershoot is

excluded. SDA/TXD

V

application.

OL=2[mA]. Undershoot is excluded. INT

I
application.

1 μA

Technical Note

DVDD > 2[V]

DVDD ≦ 2[V]

Off leakage current IOZ

Standby current IST

Current of operation IDD

-1

-

- - 2 μA

- 300 - μA

1 μA

Shutdown (SDN＝”L”)

●A/D Converter

PARAMETER SYMBOL

MIN TYP MAX

RATING

UNIT Condition

Resolution - 10 - bit

Analog Input voltage VAIN AVSS - AVDD V
change clock frequency fadck 0.2 - 2.0 MHz
change time ftim - 77 - μsec fadck = 1[MHz]
Zero scale voltage - - AVSS+0.07 V
full scale voltage AVDD-0.07 - - V
differential Non line accurate DNL - - ±3 LSB
Integrate Non line accurate INL - - ±3 LSB

●CR Oscillator characteristic

PARAMETER SYMBOL

Frequency Oscillation

f

cr

MIN TYP MAX

0.4 0.8 2.0 MHz

RATING

UNIT Condition

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2/16

2009.04 - Rev.B

BU21008MUV

●Block Diagram, Pin configuration

AVDD DVDD

Technical Note

SDA/TXD

CLK_EXT

SCL

RXD

SDN

CS

TSTD

INT

SREF

SIN[15:0]

CS

SCL

SDA/TXD

RXD

SDN

CLK_EXT

Sensor I/F、
CV translate
circuit

Reset

generation

Power
on
Reset

Conversion

sequence control

Clock

generation

CR
oscill
ation

AVSS

ADC

Data correction and

making to format

Data register

host I/F

DVSS

Power

management

INT

MODE[1:0]

DVSS

DVDD

AVDD

SREF

SIN[0]

SIN[1]/LED[0]

SIN[2]

SIN[3]/LED[1]

MODE[1]

MODE[0]

AVSS

TSTA

SIN[15]/LED[7]

SIN[4]

SIN[13]/LED[6]

SIN[13]/LED[6]

SIN[12]

SIN[11]/LED[5]

SIN[10]

SIN[9]/LED[4]

SIN[8]

SIN[7]/LED[3]

SIN[6]

SIN[13]/LED[6]

SIN[4]

SIN[5]/LED[2]

・Sensor I/F CV translate circuit

This module selects between sensor inputs. The selection sequences between all 16 channels.

・AD Conversion

The voltage into which CV is converted is converted into a digital value.
Conversion is 10 bit and full scale corresponds to AVDD.

・Conversion sequence control

Performs timing generation for the analogue circuitry and a sequencer circuit for selection of the sensor channel for
conversion.

・Data correction and making to format

This module provides the digital intelligence of the sensor.
The block includes, amongst other things, scaling, adding offsets and input filtering for de-bouncing.
Registers are formatted to simplify usage by the software application.
The block implements auto-calibration to manage drift in temperature, process variation, voltage variation and aging
effects.

・Data register

This stores the results for the software application. Please refer to the register map for details.

・HOST I/F

2 wire serial interface.

・Power management

The power management block provides smart power control.
When the sensors are not in use, the Controller automatically transitions into a low-power mode.
When a sensor is touched, then the device automatically wakes up and enters its normal operation.
The chip drives an INT pin for alerting the controller device in this case.

・Reset generation

The circuit is initialized by a either a soft reset command or by the external SDN pin.

・Clock generation

The device has an internal oscillator.
Provision is also made if the application would like to make use of an external clock input.

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2009.04 - Rev.B

BU21008MUV

●Pin Description

Pin
No.

10 SIN13/LED6 AIn/Out

11 SIN14 AIn

12 SIN15/LED7 AIn/Out

13 TSTA AIn

14 AVSS Ground

Name I/O Function Note

1 SIN4 AIn

2 SIN5/LED2 AIn/Out

3 SIN6 AIn

4 SIN7/LED3 AIn/Out

5 SIN8 AIn

6 SIN9/LED4 AIn/Out

7 SIN10 AIn

8 SIN11/LED5 AIn/Out

9 SIN12 AIn

sensor input4

sensor input 5
/PW Drive LEDcontrol output 2

sensor input6

sensor input 7
/PWM Drive LED control output 3

sensor input8

sensor input 9
/LED control output 4

sensor input10

sensor input 11
/LED control output 5

sensor input12

sensor input 13
/LED control output 6

sensor input14

sensor input 15
/LED control output 7

Test input for analog block

Analog ground -

- AVDD "Hi-Z" ④

sensor input , LED drive
select

- AVDD "Hi-Z" ④

sensor input ,
LED drive select

- AVDD "Hi-Z" ④

sensor input ,
LED drive select

- AVDD "Hi-Z" ④

sensor input ,
LED drive select

- AVDD "Hi-Z" ④

sensor input ,
LED drive select

- AVDD "Hi-Z" ④

sensor input , LED drive
select
NC on the substrate is
recommended.

Technical Note

Supply

Reference

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

- - -

Reset

Level

I/O

Pad

15 MODE[0] In

16 MODE[1] In

17 TSTD In

18 CLK_EXT In

19 INT Out

20 SDA/TXD In/Out

21 SCL In

22 RXD In

23 CS In

24 SDN In

25 DVSS Ground

26 DVDD Power

27 AVDD Power

28 SREF AIn

Mode selection, input0

Mode selection, input1

Digital part test input Usually must be tide to "L"

External system clock input Usually tide to"L"

Output of interrupt

Communication data sending and
receiving(2wires serial)

Communication
synchronous clock input
system clock input
(2wires serial)
Slave address selection
(2wires serial mode)

Shutdown input

Digital part ground

Digital part Power supply

Analog part Power supply

Standard capacitor input

00 = 2wires serial,
internal clock

"L" : Active mode
"H" : Idle mode ※2

- DVDD

- DVDD - ②

"L" : Internal clock
"H" : external clock
"L" : 5Ah
"H" : 5Bh
"L" : Halt condition
"H" : state of operation

- - - -

- - - -

- - - ④

- AVDD "Hi-Z" ④

DVDD - ①

DVDD - ①

DVDD - ①

DVDD - ①

DVDD "L" ③

"Hi-Z"

-

DVDD - ②

DVDD - ②

DVDD - -

⑤
②

29 SIN0 AIn

30 SIN1/LED0 AIn/Out

31 SIN2 AIn

32 SIN3/LED1 AIn/Out

*1 Initial State When internal organs power-on reset is effective
Halt condition SDN=”L”

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sensor input 0

sensor input 1
/PWM Drive LEDcontrol output 0

sensor input 2

sensor input 3
/PWM Drive LEDcontrol output 1

4/16

- AVDD "Hi-Z" ④

sensor input ,
LED drive select

AVDD "Hi-Z" ④

sensor input ,
LED drive select

AVDD "Hi-Z" ④

AVDD "Hi-Z" ④

2009.04 - Rev.B

BU21008MUV

●I/O Circuit

①CMOS INPUT ②CMOS Schmitt INPUT ③CMOS OUTPUT

Technical Note

CIN

④CMOS 3stute OUTPUT with

ANALOG-SW

PAD

⑤CMOS Schmitt INOUT

ASW

AIN

PADI

OE

CIN

OEN

PADCIN

PADI

I

PAD

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5/16

2009.04 - Rev.B

BU21008MUV

Technical Note

●HOST I/F
・2 wire serial, BUS (Pin configuration, MODE［1:0］＝00b)

Slave mode only
Slave Address = 5Ah,5Bh selection possible.
Normal (Normal mode. 100kHz Transfer rate)
Fs mode (Fast mode. 400kHz Transfer rate) also.
Not adapting sequential read / write.

【Data format】

t

HD;STA

t

SU;STO

SDA

t

SU;DAT

t

HD;DAT

SCL

Address

Read

ACK

Data Data

ACK

ACK

Parameter

Standard mode High Speed mode

MIN MAX MIN MAX
fSCL : SCL Clock Freq 0 100 0 400 kHz
tHD;STA : START condition hold time 4.0 - 0.6 - μsec
tLOW : SCL “L” 4.7 - 1.3 - μsec
tHIGH : SCL “H” 4.0 - 0.6 - μsec
tHD;DAT : Data hold time 0.1 3.45 0.1 0.9 μsec
tSU;DAT : Data setup time 0.25 - 0.1 - μsec
tSU;STO : START condition hold time 4.0 - 0.6 - μsec
tBUF : Free time of bus between STOP condition and
START condition

4.7 - 1.3 - μsec

【PROTOCOL】

Unit

・Write Protocol

S SLAVE ADDRESS W

7bit = 5Ah or 5Bh 8bit 8bit

・Read Protocol

S SLAVE ADDRESS W

7bit = 5Ah or 5Bh 8bit 7bit = 5Ah or 5Bh 8bit

from Master to Slave S = START condition

from Slave to Master P = STOP condition

R = data direction READ (SDA HIGH)

W = data direction WRITE (SDA LOW)

A = acknowledge (SDA LOW)

N = not acknowledge (SDA HIGH)

A

A

REGISTER

ADDRESS

REGISTER

ADDRESS

A WRITE DATA AP

A S SLAVE ADDRESS R A READ DATA N P

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6/16

2009.04 - Rev.B