Universal Standard Specification Series Serial EEPROM Series
Advantage Series Serial EEPROMs
Microwire BUS
BR93C□□-10□U-1.8 family
●Description
The BR93C46/56/66 series ICs are serial EEPROMs of 1K/2K/4Kbits, respectively, which feature low voltage operation and
low power consumption, enabling compatibility with a wide range of applications. In addition, compact packages are
available, contributing to end-product miniaturization.
●Features
1) Microwire Bus interface
2) Single supply voltage: 1.8 to 5.5V
3) 16bit serial EEPROM
4) Automatic ERASE before WRITE and self-timed programming cycle
5) Ready /Busy status
6) 2MHz Clock Frequency, 10ms WRITE Time
7) Auto-increment of register address for READ mode
8) 1,000,000 WRITE/ERASE Cycles
9) 40-year data retention
●Pin configuration
Table1.Pin Configuration
Pin Name Function
CS Chip Select
SK Serial Data Clock
DI Serial Data Input
DO Serial Data Output
GND Ground
VCC Power Supply
DC Don’t Connect
These EEPROMs utilize a three line serial interface
consisting of Serial Data Input (DI), Serial Clock (SK), and
Serial Data Output (DO)
After one READ instruction segment is received, if the Chip
Select (CS) remains HIGH, the address pointer automatically
cycles to the next higher register address, giving a
continuous string of output data, depending on the device
and the starting address.
When a WRITE or WRAL instruction is received, the
previous data in the address locations are
automatically overwritten, eliminating the need for an ERASE
command.
When Chip Select (CS) is set to H after the WRITE command,
the Status signal (Ready/Busy) becomes active at the Serial
Data Output (DO) until the start bit of the next command. The
Status signal is active when Chip Select (CS) is HIGH, and
Serial Data Output (DO) pin outputs High – Z when Chip
Select (CS) is LOW.
●Operating Instructions
The BR93□□ has a seven instruction set, shown in Tables
6 and 7. The timing charts depicted in Figures 3 to 10.
Input Data are clocked in from Serial Data Input (DI) at the
rising edge of the Serial Clock (SK), while output data from
the Serial Data Output (DO) toggles at the rising edge of the
Serial Clock (SK) during READ mode.
Table 6: Instruction Set (BR93C46)
Instruction Start Bit Op CodeAddress*1 Data
Technical Note
The EEPROM recognizes the first 1 data received, after Chip
Select (CS) goes HIGH, as the START bit. The input of many
0’s before 1 will not make a difference – 1 will still be
recognized as the START bit.
READ
EWEN
ERASE
WRITE
ERAL
WRAL
EWDS
*1: * = Inconsequential bit
Table 7: Instruction Set (BR93C56 and BR93C66)
Instruction Start Bit Op CodeAddress
READ 1 10 A7 A6 A5 A4 A3 A2 A1 A0
EWEN 1 00 11***** *
ERASE 1 11 A7 A6 A5 A4 A3 A2 A1 A0
WRITE 1 01 A7 A6 A5 A4 A3 A2 A1 A0 D15~D0
ERAL 1 00 10***** *
1 10 A5A4A3A2A1 A0
1 00 1 1 * * * *
1 11 A5A4A3A2A1 A0
1 01 A5A4A3A2A1 A0 D15~D0
1 00 1 0 * * * *
1 00 0 1 * * * * D15~D0
1 00 0 0 * * * *
*1, *2
Data
WRAL 1 00 01***** * D15~D0
EWDS 1 00 00***** *
*1:*= Inconsequential bit
*2: Address bit A7 is not decoded by the BR93C56.
READ
The addressed 16 bits of data are clocked out after the
READ instruction is received. During clocking of the
11th(1) bit the clock is HIGH and the EEPROM outputs ‘0’
(dummy 0) as a sign to begin data output.
This device has an auto-increment feature that provides
the whole memory array data using just one READ
command.
It is recommended that Chip Select (CS) is HIGH and the
Serial Clock (SK) keep clocking, since the EEPROM will
output the next address data following the addressed 16
bits of data.
EWEN
The unit is in disable mode after power ON.
The EWEN instruction must precede any WRITE
commands. After EWEN is executed the EEPROM will be
in enable mode until power OFF or EWDS instruction is
received. Neither the EWEN nor the EWDS instruction has
any effect on the READ instruction. The state ( H or L) of
the Serial Data Input (DI) after the 6th clock of the Serial
Clock (SK) doesn’t matter, either. Therefore, it is
recommended that eight more Serial Clock (SK) signals be
inputted.
EWDS
This command puts the EEPROM into disable mode –
similar to the status after power ON. The READ command
can be preceded even in disable mode. It is recommended
that the EWDS command be executed after any WRITE
commands in order to prevent inadvertent writing. The
state (H or L) of Serial Data Input (DI) after the 6th clock of
the Serial Clock (SK) does not matter. Therefore, the
inputting of eight more Serial Clock (SK) signals is
recommended as well.
ERASE
The ERASE command writes ‘1’ to all bits in the specified
address. Between the rising edge of the 11th and 12th(2)
clock cycles the falling edge of Chip Select (CS) initiates a
high voltage cycle that writes the data into the non-volatile
memory array. The Serial Data Output (DO) pin indicates
the Ready/Busy status.
WRITE
The WRITE command writes 16 bits of data into the
specified address.
Between the rising edge of the 27th and 28th(3) clock
cycles the falling edge of Chip Select (CS) initiates a high
voltage cycle that writes the data into the non-volatile
memory array.
The Serial Data Output (DO) pin indicates the Ready/Busy
status. During this high voltage cycle (busy state), the
EEPROM does not receive any commands.
The unit will not write the data into non-volatile memory
array if Chip Select (CS) is L after input of the 28th(4) or
more cycle of the Serial Clock (SK)
Technical Note
ERAL
The ERAL command writes ‘1’ in all bits at the specified
address. Between the rising edge of 11th and 12th
cycles the falling edge of Serial Clock (SK) initiates a high
voltage cycle that writes the data into the non-volatile
memory array. Serial Data Output (DO) gives an indication
of the Ready/Busy status. The time from the rising edge of
the 11th
than t
WRAL
This command writes 16 bits of data to the specified
address. It takes maximum 5ms, since all of the data are
written into the memory array at the same time. Between
the rising edge of the 27th and 28th
falling edge of Chip Select (CS) initiates a high voltage
cycle that writes the data into the non-volatile memory
array. The EEPROM will not write the data into the
non-volatile memory array if Chip Select (CS) is L after
input of the 28th
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