ROHM BR24T Technical data
High Reliability Serial EEPROMs
I2C BUS
BR24□□□□family
BR24T□□□□Series
●Description
BR24T□□□-W series is a serial EEPROM of I
●Features
1) Completely conforming to the world standard I
All controls available by 2 ports of serial clock (SCL) and serial data(SDA)
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 1.7V～5.5V single power source action most suitable for battery use
4) 1.7V～5.5Vwide limit of action voltage, possible FAST MODE 400KHz action
5) Page write mode useful for initial value write at factory shipment
6) Auto erase and auto end function at data write
7) Low current consumption
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various packages
10) Data rewrite up to 1,000,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
●BR24T series
Capacity Bit format Type
1Kbit 128×8 BR24T01-W 1.7～5.5V ● ● ● ● ● ● ● ●
Power source
Voltage
2
C BUS interface method
2
C BUS.
DIP-T8 SOP8 SOP-J8 SSOP-B8 TSSOP-B8 TSSOP-B8J MSOP8
No.11001EAT21
VSON008
X2030
2Kbit 256×8 BR24T02-W 1.7～5.5V ● ● ● ● ● ● ● ●
4Kbit 512×8 BR24T04-W 1.7～5.5V ● ● ● ● ● ● ● ●
8Kbit 1K×8 BR24T08-W 1.7～5.5V ● ● ● ● ● ● ● ●
16Kbit 2K×8 BR24T16-W 1.7～5.5V ● ● ● ● ● ● ● ●
32Kbit 4K×8 BR24T32-W 1.7～5.5V ● ● ● ● ● ● ● ●
64Kbit 8K×8 BR24T64-W 1.7～5.5V ● ● ● ● ● ● ● ●
128Kbit 16K×8 BR24T128-W 1.7～5.5V ● ● ● ● ● ● ● ●
256Kbit 32K×8 BR24T256-W 1.7～5.5V ● ● ● ● ●
512Kbit 64K×8 BR24T512-W 1.7～5.5V ☆ ☆ ☆ ☆ ☆
1024Kbit 128K×8 BR24T1M-W 1.7～5.5V ☆ ☆ ☆
☆:Developing
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1/21
2011.03 - Rev.A
BR24T□□□□Series
t
t
t
Technical Note
●Absolute maximum ratings (Ta=25℃) ●Memory cell characteristics (Ta=25℃, Vcc=1.7～
5.5V)
Parameter Symbol Ratings Unit
Impressed voltage VCC -0.3～+6.5 V
450 (SOP8)*1
450 (SOP-J8)*2
300 (SSOP-B8)*3
Permissible
dissipation
Storage
temperature range
Action
temperature range
Pd
Ts tg －65～+150 ℃
Topr －40～+85 ℃
330 (TSSOP-B8)*4
310 (TSSOP-B8J)
310 (MSOP8)
*6
300 (VSON008X2030)
800 (DIP-T8)*8
mW
*5
*7
●Recommended operating conditions
Terminal voltage ‐ -0.3～Vcc+1.0*9 V
Junction
temperature
*1,*2 When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
*3,*7 When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
*4 When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
*5, *6 When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
*8 When using at Ta=25℃ or higher 8.1mW to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not under -1.0V. (BR24T16/32/64/128/256/512/1M-W)
the Min value of Terminal Voltage is not under -0.8V. (BR24T01/02/04/08-W)
*10 Junction temperature at the storage condition.
*10
Tjmax 150 ℃
Parameter
Number of data
rewrite times
Data hold years
*1Not 100% TESTED
1,000,000 － － Times
*1
*1
Parameter Symbol Ratings Unit
Power source
voltage
Input voltage VIN 0～Vcc
Limits
Min. Typ. Max
Unit
40 － － Years
Vcc 1.7～5.5
V
●Electrical characteristics (Unless otherwise specified, Ta=－40～+85℃,
Parameter Symbol
“H” input voltage 1 V
“L” input voltage 1 V
“L” output voltage 1 V
“L” output voltage 2 V
Min. Typ. Max.
0.7Vcc － Vcc+1.0 V
IH1
-0.3*2 － 0.3Vcc V
IL1
－ － 0.4 V IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)
OL1
－ － 0.2 V IOL=0.7mA, 1.7V≦Vcc＜2.5V (SDA)
OL2
Limits
VCC=1.7～5.5V)
Unit Conditions
Input leak current ILI －1 － 1 µA VIN=0～Vcc
Output leak current ILO －1 － 1 µA V
－ － 2.0
=0～Vcc (SDA)
OUT
Vcc=5.5V,f
=400kHz,
SCL
Byte write, Page write
WR
=5ms,
BR24T01/02/04/08/16/32/64-W
I
CC1
－ － 2.5
mA
Byte write, Page write
Vcc=5.5V,f
=400kHz,
SCL
WR
=5ms,
BR24T128/256-W
Current consumption
at action
I
CC2
－ － 4.5
Byte write, Page write
BR24T512/1M-W
Vcc=5.5V,f
Vcc=5.5V,f
－ － 0.5
－ － 2.0
Random read, current read, sequential read
BR24T01/02/04/08/16/32/64/128/256-W
mA
Vcc=5.5V,f
Random read, current read, sequential read
=400kHz,
SCL
=400kHz
SCL
=400kHz
SCL
WR
=5ms,
BR24T512/1M-W
Vcc=5.5V, SDA・SCL=Vcc
－ － 2.0
Standby current ISB
－ － 3.0
A0,A1,A2=GND,WP=GND
BR24T01/02/04/08/16/32/64/128/256-W
µA
Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24T512/1M-W
○ Radiation resistance design is not made.
*1 BR24T512/1M-W is a target value because it is developing.
*2 When the pulse width is 50ns or less, it is -1.0V. (BR24T16/32/64/128/256/512/1M-W)
When the pulse width is 50ns or less, it is -0.8V. (BR24T01/02/04/08-W)
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2/21
2011.03 - Rev.A
BR24T□□□□Series
Technical Note
●Action timing characteristics (Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)
Parameter Symbol
Min. Typ. Max.
Limits
SCL frequency fSCL － － 400 kHz
Data clock “HIGH“ time tHIGH 0.6 － － µs
Data clock “LOW“ time tLOW 1.2 － － µs
SDA, SCL rise time *1 tR － － 1.0 µs
SDA, SCL fall time *1 tF － － 1.0 µs
Start condition hold time tHD:STA 0.6 － － µs
Start condition setup time tSU:STA 0.6 － － µs
Input data hold time tHD:DAT 0 － － ns
Input data setup time tSU:DAT 100 － － ns
Output data delay time tPD 0.1 － 0.9 µs
Output data hold time tDH 0.1 － － µs
Stop condition setup time tSU:STO 0.6 － － µs
Bus release time before transfer start tBUF 1.2 － － µs
Internal write cycle time tWR － － 5 ms
Noise removal valid period (SDA, SCL terminal) tI － － 0.1 µs
WP hold time tHD:WP 1.0 － － µs
WP setup time tSU:WP 0.1 － － µs
WP valid time tHIGH:WP 1.0 － － µs
*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns
●Sync data input / output timing
SCL
70%
SDA
(input)
SDA
(output)
○Input read at the rise edge of SCL
○
Data output in sync with the fall of SCL
70% 70%
tBUF
Fig.1-(a) Sync data input / output timing
tR tF tHIGH
30%
tSU:DAT
70% 70%
70%
30%
30%
tLOW
70%
30%
70%
30%
tHD:D AT
70%
30%
tDHtPD
70%
30%
70%
DATA(n)
ACK
tHD:WP
STOP CONDITION
70%
tWR
30%
D1
DATA(1)
D0 ACK
30%
tSU:WP
Fig.1-(d) WP timing at write execution
70%
tSU:STA tHD:STA
70%
70%
30%
START COND ITION
tSU:STO
70%
30%
STOP C ONDIT ION
DATA(1)
D1 ACK
D0
tHIGH:WP
70%
DATA(n)
70%
ACK
tWR
70%
Fig.1-(b) Start-stop bit timing
Fig.1-(e) WP timing at write cancel
(n-th address)
ACK
D0
Fig.1-(c) Write cycle timing
70%
70%
tWRwrite data
START CONDITIONSTOP CON DITION
Unit
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3/21
2011.03 - Rev.A
BR24T□□□□Series
P
●Block diagram
*2
A0
*2
A1
*2
A2
GND
1
2
3
*1
Address
decoder
Control circuit
High voltage
generating circuit
1Kbit～1024Kbit EEPROM array
*1
7bit
13bit
8bit
14bit
Word
9bit
15bit
10bit
16bit
address register
11bit
17bit
12bit
START STOP
ACK
ower source
voltage detection
8bit
Data
register
*
1 7bit: BR24T01-W
8bit: BR24T02-W
9bit: BR24T04-W
10bit: BR24T08-W
11bit: BR24T16-W
12bit: BR24T32-W
13bit: BR24T64-W
14bit: BR24T128-W
15bit: BR24T256-W
16bit: BR24T512-W
17bit: BR24T1M-W
*2 A0= Don't use : BR24T04-W, BR24T1M-W
A0, A1=Don't use: BR24T08-W
A0, A1, A2=Don't use: BR24T16-W
Fig.2 Block diagram
●Pin assignment and description
Terminal
Name
A0 Input
A1 Input
A2 Input
GND －
SDA
Input/
Output
Input/
output
BR24T01-W BR24T02-W BR24T04-W BR24T08-W BR24T16-W
Slave address setting Don’t use*
Slave address setting Don’t use* Slave address setting
Slave address setting Don’t use* Slave address setting
Reference voltage of all input / output, 0V
Serial data input serial data output
SCL Input
WP Input
Vcc －
*Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.
Connect the power source.
●Characteristic data (The following values are Typ. ones.)
8
Vcc
WP
7
6
SCL
5 4
SDA
A0
A1
A2
GND
Serial clock input
Write protect terminal
1
BR24T01-W
BR24T02-W
BR24T04-W
2
BR24T08-W
BR24T16-W
BR24T32-W
3
BR24T64-W
BR24T128-W
BR24T256-W
BR24T512-W
4
BR24T1M-W
BR24T32/64/
128/256/512-W
Slave address
setting
Technical Note
Vcc
8
WP
7
SCL
6
5
SDA
BR24T1M-W
Don’t use*
6
5
(V)
IH1
H INPUT VOLTAGE : V
(V)
OL2
L OUTPUT VOLTAGE : V
Ta=-40℃
Ta=25℃
4
Ta=85℃
3
2
1
0
0123456
1
0.8
0.6
0.4
0.2
0
0123456
Fig.6 'L' output voltage V
SPEC
SUPPLY VOLTAGE : Vcc(V)
Fig.3 'H' input voltage V
(A0,A1,A2,SCL,SDA,WP)
Ta=-40℃
Ta=25℃
Ta=85℃
L OUTPUT CURRENT : I
SPEC
OL2-IOL
IH1
(mA)
OL
(Vcc=2.5V)
6
5
(V)
IL1
L INPUT VOLTAGE : V
(uA)
LI
INPUT LEAK CURRENT : I
Ta=-40℃
Ta=25℃
Ta=85℃
4
3
2
1
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.4 'L' input voltage V
1.2
1
0.8
0.6
Ta=-40℃
0.4
Ta=25℃
Ta=85℃
0.2
0
0123456
SUPPLYVOLTAGE : Vcc(V)
Fig.7 Input leak current I
SPEC
(A0,A1,A2,SCL,SDA,WP)
SPEC
(A0,A1,A2,SCL,WP)
1
Ta=-40℃
Ta=25℃
0.8
(V)
OL1
L OUTPUT VOLTAGE : V
IL1
(uA)
LO
OUTPUT LEAK CURRENT : I
LI
Ta=85℃
0.6
SPEC
0.4
0.2
0
0123456
L OUTPUT CURRENT : I
Fig.5 'L' output voltage V
1.2
1
0.8
0.6
Ta=-40℃
Ta=25℃
0.4
Ta=85℃
0.2
0
0123456
Fig.8 Output leak current I
SPEC
SUPPLY VOLTAGE : Vcc(V)
OL
OL1-IOL
(mA)
(Vcc=1.7V)
(SDA)
LO
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4/21
2011.03 - Rev.A
BR24T□□□□Series
(
)
●Characteristic data (The following values are Typ. ones.)
2.5
2
1.5
CURRENT CONSUMPTION
CURRENT CONSUMPTION
Ta=-40℃
Ta=25℃
Ta=85℃
1
AT WRITING : Icc1(mA)
0.5
0
0123456
Fig.9 Current consumption at WRITE operation ICC1
(fscl=400kHz BR24T01/02/04/08/16/32/64-W)
0.6
0.5
0.4
0.3
0.2
0.1
AT READING : Icc2(mA)
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
0
0123456
Fig.12 Current consumption at READ operation ICC2
(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)
2.5
(uA)
2
SB
(us)
LOW
ＤＡＴＡ CLK L TIME : t
The plan for
inserting data.
1.5
(BR24T512/1M-W)
1
STANBY CURRENT : I
0.5
0
0123456
Fig.15 Stanby operation I
(fscl=400kHz BR24T512/1M-W)
1.5
1.2
0.9
Ta=-40℃
Ta=25℃
Ta=85℃
0.6
0.3
0
0123456
Fig.18 Data clock Low Period t
SPEC
SPEC
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc(V)
SUPPLY VOLTAGE : Vcc（V）
SB
SPEC
LOW
3.5
3
2.5
2
Ta=-40℃
Ta=25℃
1.5
Ta=85℃
1
0.5
AT WRITING : Icc1(mA)
CURRENT CONSUMPTION
0
0123456
Fig.10 Current consumption at WRITE operation Icc1
0.6
0.5
0.4
0.3
0.2
AT READING : Icc2(mA)
0.1
CURRENT CONSUMPTION
0
0123456
Fig.13 Current consumption at READ operation ICC2
10000
）
Z
1000
100
10
1
SCL FREQUENCY : fｓｃｌ（ｋH
0.1
0123456
1
(us)
HD : STA
0.8
0.6
0.4
0.2
0
START CONDITION HO LD TIME : t
Fig.19 Start Condition Hold Time t
SUPPLY VOLTAGE : Vcc(V)
(fscl=400kHz BR24T128/256-W)
The plan for
inserting data.
(BR24T512/1M-W)
SUPPLY VOLTAGE : Vcc(V)
(fscl=400kHz BR24T512/1M-W)
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
Fig.16 SCL frequency f
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0123456
SUPPLY VOLTAGE : Vcc(V)
50
(ns)
0
HD: STA
-50
Ta=-40℃
-100
Ta=25℃
Ta=85℃
-150
INPUT DATA HOLD TIME : t
-200
0123456
Fig.21 Input Data Hold Time t
SUPPLY VOLTAGE : Vcc(V)
SPEC
HD : DAT
（HIGH）
50
(ns)
0
HD :DAT
-50
-100
-150
-200
INPUT DATA HOLD TIME : t
0123456
Fig.22 Input Data Hold Time
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
SUPPLY VOLTAGE : Vcc(V)
6
SPEC
SPEC SPEC
SCL
HD : STA
(LOW）
ｔ
HD : DAT
5
The plan for
4
inserting data.
3
(BR24T512/1M-W)
2
1
AT WRITING : Icc1(mA)
CURRENT CONSUMPTION
0
0123456
Fig.11 Current consumption at WRITE operation Icc1
2.5
2
(uA)
SB
1.5
1
0.5
STANBY CURRENT : I
0
0123456
fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W
0.8
(us)
HIGH
0.6
0.4
0.2
DATA CLK H TIME : t
1.1
0.9
0.7
0.5
0.3
START CONDITION
0.1
SET UP TIME : tSU:STA(us)
-0.1
Fig.20 Start Condition Setup Time t
300
(ns)
200
SU: DAT
100
-100
-200
INPUT DATA SET UP TI ME : t
SUPPLY VOLTAGE : Vcc(V)
(fscl=400kHz BR24T512/1M-W)
SPEC
SUPPLY VOLTAGE : V cc(V)
Fig.14 Stanby operation I
1
Ta=-40℃
Ta=25℃
Ta=85℃
0
0123456
SUPPLY VOLTAGE : V cc(V)
Fig.17 Data clock High Period t
SPEC
Ta=-40℃
Ta=25℃
Ta=85℃
0123456
SUPPLY VOLTAGE : Vcc( V)
SPEC
0
Ta=-40℃
Ta=25℃
Ta=85℃
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.23 Input Data Setup Time
Technical Note
Ta=-40℃
Ta=25℃
Ta=85℃
SB
HIGH
SU : STA
(HIGH)
ｔ
SU: DAT
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5/21
2011.03 - Rev.A
BR24T□□□□Series
●Characteristic data (The following values are Typ. ones.)
300
(ns)
200
SU : DAT
100
0
Ta=-40℃
Ta=25℃
-100
Ta=85℃
-200
INPUT DATA SET UP TIME : t
0123456
SPEC
SUPPLY VOLTAGE : Vcc(V)
Fig.24 Input Data setup time t
2.0
:STO(us)
su
Ta=-40℃
Ta=25℃
1.5
Ta=85℃
1.0
0.5
0.0
-0.5
STOP CONDITION SETUP TIME : t
0123456
SUPPLY VOLTAGE : Vcc( V)
Fig.27 Stop condition setup time
0.6
0.5
0.4
(SCL H) (us)
l
0.3
0.2
NOISE REDUCTION
0.1
EFECTIVE TIME : t
0
0123456
:STO
ｔ
SU
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
SUPPLY VOLTAGE : Vcc(V)
Fig.30 Noise reduction efection time
SU : DAT
SPEC
(LOW)
t
（SCL H）
l
2.0
(us)
PD
OUTPUT DATA DELAY TIME : t
BUS OPEN T IME
Ta=-40℃
Ta=25℃
1.5
Ta=85℃
1.0
0.5
SPEC
0.0
0123456
SUPPLY VOLTAGE : Vcc(V)
' Data output delay time
Fig.25 'L
2
(us)
BUF
1.5
1
Ta=-40℃
Ta=25℃
Ta=85℃
0.5
0
BEFORE TRANSMISSION : t
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.28 BUS open time before transmission
0.6
Ta=-40℃
0.5
Ta=25℃
0.4
(SCL L)(us)
l
NOISE REDUCTION
EFECTIVE TIME : t
Ta=85℃
0.3
0.2
0.1
0
0123456
Fig.31 Noise reduction efective time
SUPPLY VOLTAGE : Vcc(V)
2.0
(us)
PD
SPEC SPEC
OUTPUT DATA DELAY TIME : t
0
t
PD
(ms)
WR
INTERNAL WRITING
CYCLE TIME : t
(SDA H)(us)
l
NOISE REDUCTION
EFECTIVE TIME : t
Fig.32 Noise resuction efecctive time
SPEC
SPEC
t
l
ｔ
（SCL L）
BUF
Ta=-40℃
1.5
Ta=25℃
Ta=85℃
1.0
0.5
SPEC
0.0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.26 'H' Data output delay time
6
5
4
3
2
Ta=-40℃
Ta=25℃
1
Ta=85℃
0
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.29 Internal writing cycle time
0.6
Ta=-40℃
0.5
Ta=25℃
Ta=85℃
0.4
0.3
0.2
0.1
0
0123456
SUPPLY VOLATGE : Vcc(V)
Technical Note
ｔ
1
PD
SPEC
ｔ
WR
SPEC
ｔ
（SDA H）
ｌ
0.6
Ta=-40℃
0.5
Ta=25℃
Ta=85℃
0.4
(SAD L)(us)
l
0.3
0.2
NOISE REDUCT ION
0.1
EFFECTIVE TIME : t
0
0123456
Fig.33 Noise reduction efective time t
1.2
(us)
1.0
HIGH : WP
0.8
0.6
0.4
0.2
WP EFFECTIVE TIME : t
0.0
SUPPLY VOLTAGE : Vcc(V)
Ta=-40℃
Ta=25℃
Ta=85℃
0123456
Fig.36 WP efective time
SPEC
SUPPLYVOLTAGE : Vcc( V)
SPEC
t
HIGH : WP
SDA L
（
l
1.2
Ta=-40℃
Ta=25℃
Ta=85℃
SPEC
(us)
1.0
HD : WP
0.8
0.6
0.4
0.2
WP DATA HOLD TIME : t
0.0
0123456
SUPPLYVOLTAGE : Vcc(V)
）
Fig.34 WP data hold time tHD:WP
0.2
0.1
(us)
0.0
Ta=-40℃
SU : WP
WP SET UP TIME : t
Ta=25℃
-0.1
Ta=85℃
-0.2
-0.3
-0.4
-0.5
-0.6
0123456
SUPPLY VOLTAGE : Vcc(V)
Fig.35 WP setup time
SPEC
t
SU : WP
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6/21
2011.03 - Rev.A
BR24T□□□□Series
S
Technical Note
●I2C BUS communication
○I2C BUS data communication
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
I
and acknowledge is always required after each byte. I
2
C BUS carries out data transmission with plural devices connected
by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7 1-7
SCL
S P
START R/W ACK
condition condition
89 89 89
1-7
Fig.37 Data transfer timing
ACK STOPACKDATA DATAADDRES
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・ Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ /
WRITE
) of slave address is used for designating write or read action,
and is as shown below.
Setting
Setting
W/R
to 0 ------- write (setting 0 to word address setting of random read)
W/R
to 1 ------- read
Slave address
Type
BR24T01-W,BR24T02-W 1 0 1 0 A2 A1 A0 R/W―― 8
Maximum number of
Connected buses
BR24T04-W 1 0 1 0 A2 A1 P0 R/W―― 4
BR24T08-W 1 0 1 0 A2 P1 P0 R/W―― 2
BR24T16-W 1 0 1 0 P2 P1 P0 R/W―― 1
BR24T32-W,BR24T64-W,BR24T128-W,
BR24T256-W,BR24T512-W
BR24T1M-W
P0～P2 are page select bits.
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© 2011 ROHM Co., Ltd. All rights reserved.
1 0 1 0 A2 A1 A0 R/
1 0 1 0 A2 A1 P0 R/
7/21
――
W
8
――
W
4
2011.03 - Rev.A
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