●Absolute maximum ratings (Ta=25℃) ●Memory cell characteristics (Ta=25℃, Vcc=1.7~
5.5V)
Parameter SymbolRatings Unit
Impressed voltage VCC -0.3~+6.5 V
450 (SOP8)*1
450 (SOP-J8)*2
300 (SSOP-B8)*3
Permissible
dissipation
Storage
temperature range
Action
temperature range
Pd
Ts tg -65~+150 ℃
Topr -40~+85 ℃
330 (TSSOP-B8)*4
310 (TSSOP-B8J)
310 (MSOP8)
*6
300 (VSON008X2030)
800 (DIP-T8)*8
mW
*5
*7
●Recommended operating conditions
Terminal voltage ‐ -0.3~Vcc+1.0*9 V
Junction
temperature
*1,*2 When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
*3,*7 When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
*4 When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
*5, *6 When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
*8 When using at Ta=25℃ or higher 8.1mW to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not under -1.0V. (BR24T16/32/64/128/256/512/1M-W)
the Min value of Terminal Voltage is not under -0.8V. (BR24T01/02/04/08-W)
*10 Junction temperature at the storage condition.
○ Radiation resistance design is not made.
*1 BR24T512/1M-W is a target value because it is developing.
*2 When the pulse width is 50ns or less, it is -1.0V. (BR24T16/32/64/128/256/512/1M-W)
When the pulse width is 50ns or less, it is -0.8V. (BR24T01/02/04/08-W)
SCL frequency fSCL - - 400 kHz
Data clock “HIGH“ time tHIGH 0.6 - - µs
Data clock “LOW“ time tLOW 1.2 - - µs
SDA, SCL rise time *1 tR - - 1.0 µs
SDA, SCL fall time *1 tF - - 1.0 µs
Start condition hold time tHD:STA 0.6 - - µs
Start condition setup time tSU:STA 0.6 - - µs
Input data hold time tHD:DAT 0 - - ns
Input data setup time tSU:DAT 100 - - ns
Output data delay time tPD 0.1 - 0.9 µs
Output data hold time tDH 0.1 - - µs
Stop condition setup time tSU:STO 0.6 - - µs
Bus release time before transfer start tBUF 1.2 - - µs
Internal write cycle time tWR - - 5 ms
Noise removal valid period (SDA, SCL terminal) tI - - 0.1 µs
WP hold time tHD:WP 1.0 - - µs
WP setup time tSU:WP 0.1 - - µs
WP valid time tHIGH:WP1.0 - - µs
*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns
●I2C BUS communication
○I2C BUS data communication
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,
I
and acknowledge is always required after each byte. I
2
C BUS carries out data transmission with plural devices connected
by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-71-7
SCL
SP
STARTR/W ACK
conditioncondition
898989
1-7
Fig.37 Data transfer timing
ACK STOPACKDATADATAADDRES
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is
'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is
satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・ Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When
acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.
The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ /
WRITE
) of slave address is used for designating write or read action,
and is as shown below.
Setting
Setting
W/R
to 0 ------- write (setting 0 to word address setting of random read)
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write
continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write
bytes is specified per device of each capacity. Up to 256 arbitrary bytes can be written.(In the case of BR24T1M-W)
SDA
LINE
S
T
A
R
T
1 1 0 0
ADDRESS
Note)
SLAVE
W
R
I
T
E
A1 A2
A0
R
A
/
C
W
K
WA
7
WORD
ADDRESS
WA
DATA
D7
0
A
C
K
Fig.38 Byte write cycle (BR24T01/02/04/08/16-W)
D0
S
T
O
P
A
C
K
As for WA7, BR24T01-W becomes Don't care.
SDA
LINE
S
T
A
R
T
1 1 0 0
W
R
I
T
SLAVE
ADDRESS
A1 A2
A0 D0
Note)
1st WORD
E
ADDRESS
WA
WA
WA
WA
WA
14
13
12
11
15
R
A
/
C
W
K
*1
2nd WORD
ADDRESS
WA
0
A
C
K
A
C
K
D7
DATA
S
T
O
P
*1 As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8Byte (BR24T01-W, BR24T02-W)
Up to 16Byte (BR24T04-W, BR24T08-W, BR24T16-W)
Up to 32Byte (BR24T32-W, BR24T64-W)
Up to 64Byte (BR24T128-W, BR24T256-W)
Up to 128Byte (BR24T512-W)
Up to 256Byte (BR24T1M-W)
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P10.)
・As for page write cycle of BR24T01-W and BR24T02-W, after the significant 4 bits (in the case of BR24T01-W) of word
address, or the significant 5 bits (in the case of BR24T02-W) of word address are designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be
written.
・As for page write command of BR24T04-W, BR24T08-W and BR24T16-W, after page select bit ’P0’(in the case of
BR24T04-W), after page select bit ’P0,P1’(in the case of BR24T08-W), after page select bit ’P0,P1,P2’(in the case of
BR24T16-W) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of
insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.
・As for page write cycle of BR24T32-W and BR24T64-W, after the significant 7 bits (in the case of BR24T32-W) of word
address, or the significant 8 bits (in the case of BR24T64-W) of word address are designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can
be written.
・As for page write cycle of BR24T128-W and BR24T256-W, after the significant 8 bits (in the case of BR24T128-W) of
word address, or the significant 9 bits (in the case of BR24T256-W) of word address are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64
bytes can be written.
・As for page write cycle of BR24T512-W after the significant 9 bits of word address is designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 7 bits is incremented internally, and data up to 128 bytes can
be written.
・As for page write cycle of BR24T1M-W after page select bit ’P0’ and the significant 8 bit of word address are designated
arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and
data up to 256 bytes can be written.
Number of Pages 8Byte 16Byte 32Byte 64Byte 128Byte 256Byte
Product number
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
BR24T01-W
BR24T02-W
BR24T04-W
BR24T08-W
BR24T16-W
In the case BR24T256-W, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max.)
○Internal address increment
Page write mode (in the case of BR24T16-W)
WA7WA4 WA3 WA2 WA1 WA0
000000
000001
000010
0Eh
001110
001111
000000
Significant bit is fi xed.
No digit up
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do
not use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
BR24T32-W
BR24T64-W
Increment
BR24T128-W
BR24T256-W
BR24T512-W BR24T1M-W
For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h・・・ which please note.
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a
command to read data by designating address, and is used generally. Current read cycle is a command to read data of
internal address register without designating address, and is used when to verify just after write cycle. In both the read
cycles, sequential read cycle is available, and the next address data can be read in succession.
S
SDA
LINE
T
A
R
ADDRESS
T
10 0 1 A0 A1 A2
SLAVE
SDA
LINE
SDA
LINE
Note)
Fig.43 Random read cycle (BR24T01/02/04/08/16-W)
S
T
A
SLAVE
R
ADDRESS
T
A2
10 0
1
Note)
Fig.44 Random read cycle (BR24T32/64/128/256/512/1M-W)
S
T
A
SLAVE
R
ADDRESS
T
10 0 1 A0 A1 A2 D0 D7
Fig.45 Current read cycle
S
T
A
SLAVE
R
ADDRESS
T
SDA
LINE
1
10 0
Note)
Fig.46 Sequential read cycle (in the case of current read cycle)
W
R
I
T
E
R
/
W
W
R
I
T
E
WA
WA
A1
A0 D7 D0
15
14
A
R
C
/
K
W
Note)
R
E
A
D
A0
A2
A1
R
/
W
WORD
ADDRESS(n)
WA
7
*1
A
C
K
1st WORD
ADDRESS
WA
13 WA12WA11
A
*1
C
K
R
E
A
D
R
W
A
C
K
DATA(n)
A
C
/
K
DATA
D7D0
S
T
A
R
T
WA
0
A
C
K
2nd WORD
ADDRESS(n)
A
C
K
D0
A
C
K
SLAVE
ADDRESS
10 0 1A1 A2
S
T
A
R
ADDRESS
T
WA
100
0
A
C
K
S
T
O
P
R
E
A
D
A0 D0
R
W
SLAVE
A1
A0
A2
1
A
C
K
/
W
D7
D7
A
C
K
R
E
A
D
A
R
C
/
K
DATA(n)
DATA(n)
DATA(n+x
A
C
K
S
T
O
P
A
C
K
S
T
O
P
A
C
K
S
T
O
P
*1 As for WA7,BR24T01-W be come Don’t care.
*1 As for WA12, BR24T32-W become Don’t care.
As for WA13, BR24T32/64-W become Don’t care.
As for WA14, BR24T32/64/128-W become Don’t care.
As for WA15, BR24T32/64/128/256-W become Don’t care.
*1 As for WA7, BR24T01-W becomes Don't care.
*2 As for BR24T01/02-W becomes (n+7)
*1 As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.
*2 As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)
As for BR24T1M-W becomes (n+255)
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next
address data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL
signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
1
0
*1 *2 *3
0
A2
A1
1A0
*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T08/16/1M-W, A0 becomes P0.
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48-(a), Fig.48-(b), Fig.48-(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
SCL
SDA
Dummy clock×14
1 2 13 14
Star t×2
Normal command
Normal command
Fig.48-(a) The case of dummy clock +START+START+ command input
SCL
SDA
Start
Dummy clock×9
2 1 8 9
Start
Normal command
Normal command
Fig.48-(b) The case of START +9 dummy clocks +START+ command input
SCL
SDA
1 2 3 8 9 7
Star t×9
Normal command
Normal command
Fig.48-(c) START×9+ command input
※Start command from START input.
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously,
W/R
= 0, when to carry out current read cycle after write, slave address
W/R
= 1 is sent,
and if ACK signal sends back 'L', then execute word address input and data output and so forth.
First write command
S
T
A
Write command
R
T
S
S
T
T
O
P
A
R
T
Slave
address
Second write command
During internal write,
ACK = HIGH is sent back.
S
T
tWR
A
R
T
Slave
address
C
K
H
C
…
K
H
…
S
T
A
R
T
Slave
address
tWR
C
K
H
S
T
A
R
T
Slave
address
Word
C
K
address
L
After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.
C
K
L
Data
C
K
L
S
T
O
P
Fig.49 Case to continuously write by acknowledge polling
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.
・Rise of D0 taken clock
・Rise of SDA
SCL
SDA
D0 ACK
D1
Enlarged view
SCL
SDA
ACK D0
Enlarged view
SDA
WP
S
T
A
R
T
A
Slave
address
Word
C
K
address
L
WP cancel invalid area
A
C
K
L
D7 D6
D5
D4
D3
D2
D0
D1
Data is not written.
A
C
Data
K
L
WP cancel valid area
A
C
K
L
O
S
T
P
tWR
WP cancel invalid area
Fig.50 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1 1 0 0
Start condition Stop condition
Fig.51 Case of cancel by start, stop condition during slave address input
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R
this resistance value from microcontroller V
limited. The smaller the R
, the larger the consumption current at action.
PU
, IL, and VOL-I
IL
characteristics of this IC. If RPU is large, action frequency is
OL
○Maximum value of RPU
The maximum value of R
is determined by the following factors.
PU
①SDA rise time to be determined by the capacitance (CBUS) of bus line of R
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential
SDA bus and R
should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including
PU
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to
○
recommended noise margin 0.2Vcc.
CC-ILRPU-0.2 VCC≧ VIH
V
IHCC
VV8.0
R
PU
I
L
Microcontroller
Ex.) VCC =3V IL=10µA VIH=0.7 VCC
from②
37.038.0
R
PU
1010
6
300 [kΩ]
Technical Note
), select an appropriate value to
PU
and SDA should be tR or below.
PU
BR24TXX
RPU
A
L
I
Bus line
capacity
CBUS
SDA
IL
terminal
Fig.52 I/O circuit diagram
○ Minimum value of RPU
The minimum value of R
When IC outputs LOW, it should be satisfied that V
OLCC
VV
OL
I
PU
R
VVR
②V
PU
OLMAX= should secure the input 'L' level (V
OLCC
OL
I
is determined by the following factors.
PU
OLMAX
) of microcontroller and EEPROM
IL
=0.4V and I
OLMAX
=3mA.
including recommended noise margin 0.1Vcc.
OLMAX≦ VIL-0.1 VCC
V
CC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM V
Ex.) V
4.03
from①
R
PU
867[Ω]
And
VOL=0.4[V]
3
103
=0.3Vcc
IL
VIL=0.3×3
=0.9[V]
Therefore, the condition ② is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
In I
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
①SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
②The bus electric potential
sufficiently secure the input 'L' level (V
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
○
) of microcontroller including recommended noise margin 0.1Vcc.
IL
OLCC
VV
V
IL
Micro controller
V
CC
Bus line
capacity
CBUS
R
PU
S
R
I
OL
V
OL
EEPROM
Ex)VCC=3VVIL=0.3VCCVOL=0.4VRPU=20kΩ
Fig.55 I/O Circuit Diagram
SPU
RR
OLCC
VV
SR
R
ILCC
VV1.1
31.04.033.0
S
R
33.031.1
]k[67.1Ω
PU
ILCCOL
VV1.0V
3
1020
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.
At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H’
, t
2. Start power source so as to satisfy the recommended conditions of t
CC
V
tR
Recommended conditions of tR, tOFF,Vbot
, and Vbot for operating POR circuit.
R
OFF
tR tOFF Vbot
tOFF
0
Fig.59 Rise waveform diagram
Vbot
10ms or below 10ms or larger 0.3V or below
100msor below 10msor larger 0.2V or below
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
V
CC
SCL
tLOW
SDA
fter Vcc becomes stable
Fig.60 When SCL= 'H' and SDA= 'L'
tSU:DAT
tDH
fter Vcc becomes stable
Fig.61
When SCL='L' and SDA='L'
tSU:DAT
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P12).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●Vcc noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it
that conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4) GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that
of GND terminal.
(5) Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6) Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
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other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
The Products specied in this document are intended to be used with general-use electronic
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Product may fail or malfunction for a variety of reasons.
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