ROHM BR24T Technical data

High Reliability Serial EEPROMs

I2C BUS
BR24□□□□family

BR24T□□□□Series

●Description

BR24T□□□-W series is a serial EEPROM of I

●Features

1) Completely conforming to the world standard I
All controls available by 2 ports of serial clock (SCL) and serial data(SDA)

2) Other devices than EEPROM can be connected to the same port, saving microcontroller port

3) 1.7V～5.5V single power source action most suitable for battery use

4) 1.7V～5.5Vwide limit of action voltage, possible FAST MODE 400KHz action

5) Page write mode useful for initial value write at factory shipment

6) Auto erase and auto end function at data write

7) Low current consumption

8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage

9) DIP-T8/SOP8/SOP-J8/SSOP-B8/TSSOP-B8/TSSOP-B8J/MSOP8/VSON008X2030 various packages

10) Data rewrite up to 1,000,000 times

11) Data kept for 40 years

12) Noise filter built in SCL / SDA terminal

13) Shipment data all address FFh

●BR24T series

Capacity Bit format Type

1Kbit 128×8 BR24T01-W 1.7～5.5V ● ● ● ● ● ● ● ●

Power source

Voltage

2

C BUS interface method

2

C BUS.

DIP-T8 SOP8 SOP-J8 SSOP-B8 TSSOP-B8 TSSOP-B8J MSOP8

No.11001EAT21

VSON008

X2030

2Kbit 256×8 BR24T02-W 1.7～5.5V ● ● ● ● ● ● ● ●

4Kbit 512×8 BR24T04-W 1.7～5.5V ● ● ● ● ● ● ● ●

8Kbit 1K×8 BR24T08-W 1.7～5.5V ● ● ● ● ● ● ● ●

16Kbit 2K×8 BR24T16-W 1.7～5.5V ● ● ● ● ● ● ● ●

32Kbit 4K×8 BR24T32-W 1.7～5.5V ● ● ● ● ● ● ● ●

64Kbit 8K×8 BR24T64-W 1.7～5.5V ● ● ● ● ● ● ● ●

128Kbit 16K×8 BR24T128-W 1.7～5.5V ● ● ● ● ● ● ● ●

256Kbit 32K×8 BR24T256-W 1.7～5.5V ● ● ● ● ●

512Kbit 64K×8 BR24T512-W 1.7～5.5V ☆ ☆ ☆ ☆ ☆

1024Kbit 128K×8 BR24T1M-W 1.7～5.5V ☆ ☆ ☆

☆:Developing

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1/21

2011.03 - Rev.A

BR24T□□□□Series

t

t

t

Technical Note

●Absolute maximum ratings (Ta=25℃) ●Memory cell characteristics (Ta=25℃, Vcc=1.7～

5.5V)

Parameter Symbol Ratings Unit

Impressed voltage VCC -0.3～+6.5 V

450 (SOP8)*1

450 (SOP-J8)*2

300 (SSOP-B8)*3

Permissible
dissipation

Storage
temperature range
Action
temperature range

Pd

Ts tg －65～+150 ℃

Topr －40～+85 ℃

330 (TSSOP-B8)*4

310 (TSSOP-B8J)

310 (MSOP8)

*6

300 (VSON008X2030)

800 (DIP-T8)*8

mW

*5

*7

●Recommended operating conditions

Terminal voltage ‐ -0.3～Vcc+1.0*9 V

Junction
temperature

*1,*2 When using at Ta=25℃ or higher 4.5mW to be reduced per 1℃.
*3,*7 When using at Ta=25℃ or higher 3.0mW to be reduced per 1℃.
*4 When using at Ta=25℃ or higher 3.3mW to be reduced per 1℃.
*5, *6 When using at Ta=25℃ or higher 3.1mW to be reduced per 1℃.
*8 When using at Ta=25℃ or higher 8.1mW to be reduced per 1℃.
*9 The Max value of Terminal Voltage is not over 6.5V.
When the pulse width is 50ns or less, the Min value of
Terminal Voltage is not under -1.0V. (BR24T16/32/64/128/256/512/1M-W)
the Min value of Terminal Voltage is not under -0.8V. (BR24T01/02/04/08-W)
*10 Junction temperature at the storage condition.

*10

Tjmax 150 ℃

Parameter

Number of data
rewrite times

Data hold years

*1Not 100% TESTED

1,000,000 － － Times

*1

*1

Parameter Symbol Ratings Unit

Power source
voltage

Input voltage VIN 0～Vcc

Limits

Min. Typ. Max

Unit

40 － － Years

Vcc 1.7～5.5

V

●Electrical characteristics (Unless otherwise specified, Ta=－40～+85℃,

Parameter Symbol

“H” input voltage 1 V

“L” input voltage 1 V

“L” output voltage 1 V

“L” output voltage 2 V

Min. Typ. Max.

0.7Vcc － Vcc+1.0 V

IH1

-0.3*2 － 0.3Vcc V

IL1

－ － 0.4 V IOL=3.0mA, 2.5V≦Vcc≦5.5V (SDA)

OL1

－ － 0.2 V IOL=0.7mA, 1.7V≦Vcc＜2.5V (SDA)

OL2

Limits

VCC=1.7～5.5V)

Unit Conditions

Input leak current ILI －1 － 1 µA VIN=0～Vcc

Output leak current ILO －1 － 1 µA V

－ － 2.0

=0～Vcc (SDA)

OUT

Vcc=5.5V,f

=400kHz,

SCL

Byte write, Page write

WR

=5ms,

BR24T01/02/04/08/16/32/64-W

I

CC1

－ － 2.5

mA

Byte write, Page write

Vcc=5.5V,f

=400kHz,

SCL

WR

=5ms,

BR24T128/256-W

Current consumption
at action

I

CC2

－ － 4.5

Byte write, Page write
BR24T512/1M-W
Vcc=5.5V,f

Vcc=5.5V,f

－ － 0.5

－ － 2.0

Random read, current read, sequential read
BR24T01/02/04/08/16/32/64/128/256-W

mA

Vcc=5.5V,f
Random read, current read, sequential read

=400kHz,

SCL

=400kHz

SCL

=400kHz

SCL

WR

=5ms,

BR24T512/1M-W
Vcc=5.5V, SDA・SCL=Vcc

－ － 2.0

Standby current ISB

－ － 3.0

A0,A1,A2=GND,WP=GND
BR24T01/02/04/08/16/32/64/128/256-W

µA

Vcc=5.5V, SDA・SCL=Vcc
A0, A1, A2=GND, WP=GND
BR24T512/1M-W

○ Radiation resistance design is not made.
*1 BR24T512/1M-W is a target value because it is developing.
*2 When the pulse width is 50ns or less, it is -1.0V. (BR24T16/32/64/128/256/512/1M-W)
When the pulse width is 50ns or less, it is -0.8V. (BR24T01/02/04/08-W)

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2/21

2011.03 - Rev.A

BR24T□□□□Series

Technical Note

●Action timing characteristics (Unless otherwise specified, Ta=－40～+85℃, VCC=1.7～5.5V)

Parameter Symbol

Min. Typ. Max.

Limits

SCL frequency fSCL － － 400 kHz
Data clock “HIGH“ time tHIGH 0.6 － － µs
Data clock “LOW“ time tLOW 1.2 － － µs

SDA, SCL rise time *1 tR － － 1.0 µs

SDA, SCL fall time *1 tF － － 1.0 µs
Start condition hold time tHD:STA 0.6 － － µs
Start condition setup time tSU:STA 0.6 － － µs
Input data hold time tHD:DAT 0 － － ns
Input data setup time tSU:DAT 100 － － ns
Output data delay time tPD 0.1 － 0.9 µs
Output data hold time tDH 0.1 － － µs
Stop condition setup time tSU:STO 0.6 － － µs
Bus release time before transfer start tBUF 1.2 － － µs
Internal write cycle time tWR － － 5 ms
Noise removal valid period (SDA, SCL terminal) tI － － 0.1 µs
WP hold time tHD:WP 1.0 － － µs
WP setup time tSU:WP 0.1 － － µs
WP valid time tHIGH:WP 1.0 － － µs

*1 Not 100% TESTED.
Condition Input data level:VIL=0.2×Vcc VIH=0.8×Vcc
Input data timing refarence level: 0.3×Vcc/0.7×Vcc
Output data timing refarence level: 0.3×Vcc/0.7×Vcc
Rise/Fall time : ≦20ns

●Sync data input / output timing

SCL

70%

SDA
(input)

SDA
(output)

○Input read at the rise edge of SCL
○

Data output in sync with the fall of SCL

70% 70%

tBUF

Fig.1-(a) Sync data input / output timing

tR tF tHIGH

30%

tSU:DAT

70% 70%

70%

30%

30%

tLOW

70%

30%

70%

30%

tHD:D AT

70%
30%

tDHtPD

70%

30%

70%

DATA(n)

ACK

tHD:WP

STOP CONDITION

70%

tWR

30%

D1

DATA(1)

D0 ACK

30%

tSU:WP

Fig.1-(d) WP timing at write execution

70%

tSU:STA tHD:STA

70%

70%

30%

START COND ITION

tSU:STO

70%

30%

STOP C ONDIT ION

DATA(1)

D1 ACK

D0

tHIGH:WP

70%

DATA(n)

70%

ACK

tWR

70%

Fig.1-(b) Start-stop bit timing

Fig.1-(e) WP timing at write cancel

(n-th address)

ACK

D0

Fig.1-(c) Write cycle timing

70%

70%

tWRwrite data

START CONDITIONSTOP CON DITION

Unit

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3/21

2011.03 - Rev.A

BR24T□□□□Series

P

●Block diagram

*2

A0

*2

A1

*2

A2

GND

1

2

3

*1

Address

decoder

Control circuit

High voltage
generating circuit

1Kbit～1024Kbit EEPROM array

*1

7bit

13bit

8bit

14bit

Word

9bit

15bit

10bit

16bit

address register

11bit

17bit

12bit

START STOP

ACK

ower source

voltage detection

8bit

Data

register

*

1 7bit: BR24T01-W
8bit: BR24T02-W
9bit: BR24T04-W
10bit: BR24T08-W
11bit: BR24T16-W

12bit: BR24T32-W
13bit: BR24T64-W
14bit: BR24T128-W
15bit: BR24T256-W
16bit: BR24T512-W
17bit: BR24T1M-W

*2 A0= Don't use : BR24T04-W, BR24T1M-W

A0, A1=Don't use: BR24T08-W
A0, A1, A2=Don't use: BR24T16-W

Fig.2 Block diagram

●Pin assignment and description

Terminal

Name

A0 Input

A1 Input

A2 Input

GND －

SDA

Input/

Output

Input/

output

BR24T01-W BR24T02-W BR24T04-W BR24T08-W BR24T16-W

Slave address setting Don’t use*

Slave address setting Don’t use* Slave address setting

Slave address setting Don’t use* Slave address setting

Reference voltage of all input / output, 0V

Serial data input serial data output

SCL Input

WP Input
Vcc －

*Pins not used as device address may be set to any of ‘H’, 'L', and 'Hi-Z'.

Connect the power source.

●Characteristic data (The following values are Typ. ones.)

8

Vcc

WP

7

6

SCL

5 4

SDA

A0

A1

A2

GND

Serial clock input

Write protect terminal

1

BR24T01-W
BR24T02-W
BR24T04-W

2

BR24T08-W
BR24T16-W
BR24T32-W

3

BR24T64-W
BR24T128-W
BR24T256-W
BR24T512-W

4

BR24T1M-W

BR24T32/64/

128/256/512-W

Slave address

setting

Technical Note

Vcc

8

WP

7

SCL

6

5

SDA

BR24T1M-W

Don’t use*

6

5

(V)

IH1

H INPUT VOLTAGE : V

(V)

OL2

L OUTPUT VOLTAGE : V

Ta=-40℃
Ta=25℃

4

Ta=85℃

3

2

1

0

0123456

1

0.8

0.6

0.4

0.2

0

0123456

Fig.6　'L' output voltage V

SPEC

SUPPLY VOLTAGE : Vcc(V)

Fig.3　'H' input voltage V

(A0,A1,A2,SCL,SDA,WP)

Ta=-40℃
Ta=25℃
Ta=85℃

L OUTPUT CURRENT : I

SPEC

OL2-IOL

IH1

(mA)

OL

(Vcc=2.5V)

6

5

(V)

IL1

L INPUT VOLTAGE : V

(uA)

LI

INPUT LEAK CURRENT : I

Ta=-40℃
Ta=25℃
Ta=85℃

4

3

2

1

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.4　'L' input voltage V

1.2

1

0.8

0.6

Ta=-40℃

0.4

Ta=25℃
Ta=85℃

0.2

0

0123456

SUPPLYVOLTAGE : Vcc(V)

Fig.7　Input leak current I

SPEC

(A0,A1,A2,SCL,SDA,WP)

SPEC

(A0,A1,A2,SCL,WP)

1

Ta=-40℃
Ta=25℃

0.8

(V)

OL1

L OUTPUT VOLTAGE : V

IL1

(uA)

LO

OUTPUT LEAK CURRENT : I

LI

Ta=85℃

0.6

SPEC

0.4

0.2

0

0123456

L OUTPUT CURRENT : I

Fig.5 'L' output voltage V

1.2

1

0.8

0.6

Ta=-40℃
Ta=25℃

0.4

Ta=85℃

0.2

0

0123456

Fig.8　Output leak current I

SPEC

SUPPLY VOLTAGE : Vcc(V)

OL

OL1-IOL

(mA)

(Vcc=1.7V)

(SDA)

LO

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4/21

2011.03 - Rev.A

BR24T□□□□Series

(

)

●Characteristic data (The following values are Typ. ones.)

2.5

2

1.5

CURRENT CONSUMPTION

CURRENT CONSUMPTION

Ta=-40℃
Ta=25℃
Ta=85℃

1

AT WRITING : Icc1(mA)

0.5

0

0123456

Fig.9 Current consumption at WRITE operation ICC1

(fscl=400kHz BR24T01/02/04/08/16/32/64-W)

0.6

0.5

0.4

0.3

0.2

0.1

AT READING : Icc2(mA)

SUPPLY VOLTAGE : Vcc(V)

Ta=-40℃
Ta=25℃
Ta=85℃

0

0123456

Fig.12 Current consumption at READ operation ICC2

(fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W)

2.5

(uA)

2

SB

(us)

LOW

ＤＡＴＡ CLK L TIME : t

The plan for
inserting data.

1.5

(BR24T512/1M-W)

1

STANBY CURRENT : I

0.5

0

0123456

Fig.15　Stanby operation I

(fscl=400kHz BR24T512/1M-W)

1.5

1.2

0.9

Ta=-40℃
Ta=25℃
Ta=85℃

0.6

0.3

0

0123456

Fig.18 Data clock Low Period　t

SPEC

SPEC

SUPPLY VOLTAGE : Vcc(V)

SUPPLY VOLTAGE : Vcc(V)

SUPPLY VOLTAGE : Vcc（V）

SB

SPEC

LOW

3.5

3

2.5

2

Ta=-40℃
Ta=25℃

1.5

Ta=85℃

1

0.5

AT WRITING : Icc1(mA)

CURRENT CONSUMPTION

0

0123456

Fig.10　Current consumption at WRITE operation Icc1

0.6

0.5

0.4

0.3

0.2

AT READING : Icc2(mA)

0.1

CURRENT CONSUMPTION

0

0123456

Fig.13 Current consumption at READ operation ICC2

10000

）

Z

1000

100

10

1

SCL FREQUENCY : fｓｃｌ（ｋH

0.1
0123456

1

(us)

HD : STA

0.8

0.6

0.4

0.2

0

START CONDITION HO LD TIME : t

Fig.19 Start Condition Hold Time t

SUPPLY VOLTAGE : Vcc(V)

(fscl=400kHz BR24T128/256-W)

The plan for
inserting data.
(BR24T512/1M-W)

SUPPLY VOLTAGE : Vcc(V)

(fscl=400kHz BR24T512/1M-W)

Ta=-40℃
Ta=25℃
Ta=85℃

SUPPLY VOLTAGE : Vcc(V)

Fig.16　SCL frequency f

SPEC

Ta=-40℃
Ta=25℃
Ta=85℃

0123456

SUPPLY VOLTAGE : Vcc(V)

50

(ns)

0

HD: STA

-50

Ta=-40℃

-100

Ta=25℃
Ta=85℃

-150

INPUT DATA HOLD TIME : t

-200
0123456

Fig.21　Input Data Hold Time t

SUPPLY VOLTAGE : Vcc(V)

SPEC

HD : DAT

（HIGH）

50

(ns)

0

HD :DAT

-50

-100

-150

-200

INPUT DATA HOLD TIME : t

0123456

Fig.22　Input Data Hold Time

SPEC

Ta=-40℃
Ta=25℃
Ta=85℃

SUPPLY VOLTAGE : Vcc(V)

6

SPEC

SPEC SPEC

SCL

HD : STA

(LOW）

ｔ

HD : DAT

5

The plan for

4

inserting data.

3

(BR24T512/1M-W)

2

1

AT WRITING : Icc1(mA)

CURRENT CONSUMPTION

0

0123456

Fig.11　Current consumption at WRITE operation Icc1

2.5

2

(uA)

SB

1.5

1

0.5

STANBY CURRENT : I

0

0123456

fscl=400kHz BR24T01/02/04/08/16/32/64/128/256-W

0.8

(us)

HIGH

0.6

0.4

0.2

DATA CLK H TIME : t

1.1

0.9

0.7

0.5

0.3

START CONDITION

0.1

SET UP TIME : tSU:STA(us)

-0.1

Fig.20　Start Condition Setup Time　t

300

(ns)

200

SU: DAT

100

-100

-200

INPUT DATA SET UP TI ME : t

SUPPLY VOLTAGE : Vcc(V)

(fscl=400kHz BR24T512/1M-W)

SPEC

SUPPLY VOLTAGE : V cc(V)

Fig.14　Stanby operation I

1

Ta=-40℃
Ta=25℃
Ta=85℃

0

0123456

SUPPLY VOLTAGE : V cc(V)

Fig.17 Data clock High Period t

SPEC

Ta=-40℃
Ta=25℃
Ta=85℃

0123456

SUPPLY VOLTAGE : Vcc( V)

SPEC

0

Ta=-40℃
Ta=25℃
Ta=85℃

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.23　Input Data Setup Time

Technical Note

Ta=-40℃
Ta=25℃
Ta=85℃

SB

HIGH

SU : STA

(HIGH)

ｔ

SU: DAT

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5/21

2011.03 - Rev.A

BR24T□□□□Series

●Characteristic data (The following values are Typ. ones.)

300

(ns)

200

SU : DAT

100

0

Ta=-40℃
Ta=25℃

-100

Ta=85℃

-200

INPUT DATA SET UP TIME : t

0123456

SPEC

SUPPLY VOLTAGE : Vcc(V)

Fig.24　Input Data setup time t

2.0

:STO(us)

su

Ta=-40℃
Ta=25℃

1.5

Ta=85℃

1.0

0.5

0.0

-0.5

STOP CONDITION SETUP TIME : t

0123456

SUPPLY VOLTAGE : Vcc( V)

Fig.27 Stop condition setup time

0.6

0.5

0.4

(SCL H) (us)

l

0.3

0.2

NOISE REDUCTION

0.1

EFECTIVE TIME : t

0

0123456

:STO

　ｔ

SU

Ta=-40℃
Ta=25℃
Ta=85℃

SPEC

SUPPLY VOLTAGE : Vcc(V)

Fig.30 Noise reduction efection time

SU : DAT

SPEC

(LOW)

t

（SCL H）

l

2.0

(us)

PD

OUTPUT DATA DELAY TIME : t

BUS OPEN T IME

Ta=-40℃
Ta=25℃

1.5

Ta=85℃

1.0

0.5

SPEC

0.0
0123456

SUPPLY VOLTAGE : Vcc(V)

' Data output delay time

Fig.25　'L

2

(us)

BUF

1.5

1

Ta=-40℃
Ta=25℃
Ta=85℃

0.5

0

BEFORE TRANSMISSION : t

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.28 BUS open time before transmission

0.6

Ta=-40℃

0.5

Ta=25℃

0.4

(SCL L)(us)

l

NOISE REDUCTION

EFECTIVE TIME : t

Ta=85℃

0.3

0.2

0.1

0

0123456

Fig.31　Noise reduction efective time

SUPPLY VOLTAGE : Vcc(V)

2.0

(us)

PD

SPEC SPEC

OUTPUT DATA DELAY TIME : t

0

t

PD

(ms)

WR

INTERNAL WRITING

CYCLE TIME : t

(SDA H)(us)

l

NOISE REDUCTION

EFECTIVE TIME : t

Fig.32　Noise resuction efecctive time

SPEC

SPEC

　t

l

　ｔ

（SCL L）

BUF

Ta=-40℃

1.5

Ta=25℃
Ta=85℃

1.0

0.5

SPEC

0.0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.26 'H' Data output delay time

6

5

4

3

2

Ta=-40℃
Ta=25℃

1

Ta=85℃

0

0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.29 Internal writing cycle time

0.6

Ta=-40℃

0.5

Ta=25℃
Ta=85℃

0.4

0.3

0.2

0.1

0

0123456

SUPPLY VOLATGE : Vcc(V)

Technical Note

ｔ

1

PD

SPEC

　ｔ

WR

SPEC

　ｔ

（SDA H）

ｌ

0.6

Ta=-40℃

0.5

Ta=25℃
Ta=85℃

0.4

(SAD L)(us)

l

0.3

0.2

NOISE REDUCT ION

0.1

EFFECTIVE TIME : t

0

0123456

Fig.33 Noise reduction efective time t

1.2

(us)

1.0

HIGH : WP

0.8

0.6

0.4

0.2

WP EFFECTIVE TIME : t

0.0

SUPPLY VOLTAGE : Vcc(V)

Ta=-40℃
Ta=25℃
Ta=85℃

0123456

Fig.36 WP efective time

SPEC

SUPPLYVOLTAGE : Vcc( V)

SPEC

t

HIGH : WP

SDA L

（

l

1.2

Ta=-40℃
Ta=25℃
Ta=85℃

SPEC

(us)

1.0

HD : WP

0.8

0.6

0.4

0.2

WP DATA HOLD TIME : t

0.0
0123456

SUPPLYVOLTAGE : Vcc(V)

）

Fig.34 WP data hold time tHD:WP

0.2

0.1

(us)

0.0

Ta=-40℃

SU : WP

WP SET UP TIME : t

Ta=25℃

-0.1

Ta=85℃

-0.2

-0.3

-0.4

-0.5

-0.6
0123456

SUPPLY VOLTAGE : Vcc(V)

Fig.35 WP setup time

SPEC

t

SU : WP

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6/21

2011.03 - Rev.A

BR24T□□□□Series

S

Technical Note

●I2C BUS communication
○I2C BUS data communication

2

C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long,

I
and acknowledge is always required after each byte. I

2

C BUS carries out data transmission with plural devices connected
by 2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.

SDA

1-7 1-7

SCL

S P
START R/W ACK
condition condition

89 89 89

1-7

Fig.37 Data transfer timing

ACK STOPACKDATA DATAADDRES

○Start condition (Start bit recognition)

・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL is

'HIGH' is necessary.

・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition is

satisfied, any command is executed.

○Stop condition (stop bit recongnition)

・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'

○Acknowledge (ACK) signal

・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In

master and slave, the device (µ-COM at slave address input of write command, read command, and this IC at data
output of read command) at the transmitter (sending) side releases the bus after output of 8bit data.

・The device (this IC at slave address input of write command, read command, and µ-COM at data output of read

command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.

・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・ Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'. When

acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (µ-COM) side, this IC
continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.

○Device addressing

・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type.

The device code of this IC is fixed to '1010'.

・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same

bus according to the number of device addresses.

・The most insignificant bit (R/W --- READ /

WRITE

) of slave address is used for designating write or read action,

and is as shown below.

Setting

Setting

W/R

to 0 ------- write (setting 0 to word address setting of random read)

W/R

to 1 ------- read

Slave address

Type

BR24T01-W,BR24T02-W 1 0 1 0 A2 A1 A0 R/W―― 8

Maximum number of

Connected buses

BR24T04-W 1 0 1 0 A2 A1 P0 R/W―― 4

BR24T08-W 1 0 1 0 A2 P1 P0 R/W―― 2

BR24T16-W 1 0 1 0 P2 P1 P0 R/W―― 1

BR24T32-W,BR24T64-W,BR24T128-W,
BR24T256-W,BR24T512-W

BR24T1M-W

P0～P2 are page select bits.

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© 2011 ROHM Co., Ltd. All rights reserved.

1 0 1 0 A2 A1 A0 R/

1 0 1 0 A2 A1 P0 R/

7/21

――

W

8

――

W

4

2011.03 - Rev.A

BR24T□□□□Series

A

A

A

A

A

A

A

A

A

A

A0 A1 A

A

A

Technical Note

●Write Command
○Write cycle

・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write

continuous data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write
bytes is specified per device of each capacity. Up to 256 arbitrary bytes can be written.(In the case of BR24T1M-W)

SDA
LINE

S
T
A
R
T

1 1 0 0

ADDRESS

Note)

SLAVE

W
R

I
T

E

A1 A2

A0

R

A

/

C

W

K

WA

7

WORD

ADDRESS

WA

DATA

D7

0

A
C
K

Fig.38 Byte write cycle (BR24T01/02/04/08/16-W)

D0

S

T
O
P

A
C
K

As for WA7, BR24T01-W becomes Don't care.

SDA
LINE

S
T
A

R

T

1 1 0 0

W

R

I

T

SLAVE

ADDRESS

A1 A2

A0 D0

Note)

1st WORD

E

ADDRESS

WA

WA

WA

WA

WA

14

13

12

11

15

R

A

/

C

W

K

*1

2nd WORD

ADDRESS

WA

0

A
C
K

A
C
K

D7

DATA

S
T
O
P

*1 As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.

A
C
K

SDA
LINE

Fig.39 Byte write cycle (BR24T32/64/128/256/512/1M-W)

0

注 )

W

W
R

T
E

R

/

I

WA

C
K

ADDRESS(n)

7

*1

WORD

WA

0

DATA(n)

D0 D7 D0

C
K

C
K

S
T
A
R
T

1

SLAVE

ADDRESS

0

1A0 A1 A2

Fig.40 Page write cycle (BR24T01/02/04/08/16-W)

*2

DATA(n+15)

S
T
O
P

*1 As for WA7, BR24T01-W becomes Don't ca re.
*2 As for BR24T01/02-W becomes (n+7)

A
C
K

SLAVE

1
0

W
R

I
T
E

2

0

R

/

C

)

注

W

K

WA

WA

14

15

1st WORD
DDRESS(n)

WA

WA

WA

13

12

11

*1

C
K

2nd WORD

DDRESS(n)

DATA(n)

WA

0

C
K

D0D7

C
K

DATA(n+31)

*2

D0

*1 As for WA12, BR24T32-W becomes Don't care.

S

As for WA13, BR24T32/64-W becomes Don't care.

T
O

As for WA14, BR24T32/64/128-W becomes Don't care.

P

As for WA15, BR24T32/64/128/256-W becomes Don't care.

*2 As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)

C
K

As for BR24T1M-W becomes (n+255)

SDA
LINE

S
T

R

DDRESS

T

1

0

0

Note)

Fig.42 Difference of slave address of each type

Page write cycle (BR24T32/64/128/256/512/1M-W)

Fig.41

1

*1 *2 *3

0

1A0

A2

0

A1

*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T04/08/16/1M-W A0 becomes P0.

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8/21

2011.03 - Rev.A

BR24T□□□□Series

・During internal write execution, all input commands are ignored, therefore ACK is not sent back.
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).

・By page write cycle, the following can be written in bulk : Up to 8Byte (BR24T01-W, BR24T02-W)

Up to 16Byte (BR24T04-W, BR24T08-W, BR24T16-W)
Up to 32Byte (BR24T32-W, BR24T64-W)
Up to 64Byte (BR24T128-W, BR24T256-W)
Up to 128Byte (BR24T512-W)
Up to 256Byte (BR24T1M-W)

And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P10.)

・As for page write cycle of BR24T01-W and BR24T02-W, after the significant 4 bits (in the case of BR24T01-W) of word

address, or the significant 5 bits (in the case of BR24T02-W) of word address are designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 3 bits is incremented internally, and data up to 8 bytes can be
written.

・As for page write command of BR24T04-W, BR24T08-W and BR24T16-W, after page select bit ’P0’(in the case of

BR24T04-W), after page select bit ’P0,P1’(in the case of BR24T08-W), after page select bit ’P0,P1,P2’(in the case of
BR24T16-W) of slave address are designated arbitrarily, by continuing data input of 2 bytes or more, the address of
insignificant 4 bits is incremented internally, and data up to 16 bytes can be written.

・As for page write cycle of BR24T32-W and BR24T64-W, after the significant 7 bits (in the case of BR24T32-W) of word

address, or the significant 8 bits (in the case of BR24T64-W) of word address are designated arbitrarily, by continuing
data input of 2 bytes or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can
be written.

・As for page write cycle of BR24T128-W and BR24T256-W, after the significant 8 bits (in the case of BR24T128-W) of

word address, or the significant 9 bits (in the case of BR24T256-W) of word address are designated arbitrarily, by
continuing data input of 2 bytes or more, the address of insignificant 6 bits is incremented internally, and data up to 64
bytes can be written.

・As for page write cycle of BR24T512-W after the significant 9 bits of word address is designated arbitrarily, by continuing

data input of 2 bytes or more, the address of insignificant 7 bits is incremented internally, and data up to 128 bytes can
be written.

・As for page write cycle of BR24T1M-W after page select bit ’P0’ and the significant 8 bit of word address are designated

arbitrarily, by continuing data input of 2 bytes or more, the address of insignificant 8 bits is incremented internally, and
data up to 256 bytes can be written.

Technical Note

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9/21

2011.03 - Rev.A

BR24T□□□□Series

○Notes on page write cycle

List of numbers of page write

Number of Pages 8Byte 16Byte 32Byte 64Byte 128Byte 256Byte

Product number

The above numbers are maximum bytes for respective types.
Any bytes below these can be written.

BR24T01-W
BR24T02-W

BR24T04-W
BR24T08-W
BR24T16-W

In the case BR24T256-W, 1 page=64bytes, but the page
write cycle time is 5ms at maximum for 64byte bulk write.
It does not stand 5ms at maximum × 64byte=320ms(Max.)

○Internal address increment

Page write mode (in the case of BR24T16-W)

WA7 WA4 WA3 WA2 WA1 WA0

0 00000
0 00001
0 00010

0Eh

0 01110
0 01111
0 00000

Significant bit is fi xed.
No digit up

○Write protect (WP) terminal

・Write protect (WP) function

When WP terminal is set Vcc (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data
rewrite of all address is enabled. Be sure to connect this terminal to Vcc or GND, or control it to H level or L level. Do
not use it open.
In the case of use it as an ROM, it is recommended to connect it to pull up or Vcc.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.

BR24T32-W
BR24T64-W

Increment

BR24T128-W
BR24T256-W

BR24T512-W BR24T1M-W

For example, when it is started from address 0Eh,
therefore, increment is made as below,
0Eh→0Fh→00h→01h･･･ which please note.

※0Eh･･･0E in hexadecimal, therefore,

00001110 becomes a binary number.

Technical Note

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10/21

2011.03 - Rev.A

BR24T□□□□Series

(n)

)

Technical Note

●Read Command
○Read cycle

Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle. Random read cycle is a
command to read data by designating address, and is used generally. Current read cycle is a command to read data of
internal address register without designating address, and is used when to verify just after write cycle. In both the read
cycles, sequential read cycle is available, and the next address data can be read in succession.

S

SDA
LINE

T
A
R

ADDRESS

T

10 0 1 A0 A1 A2

SLAVE

SDA
LINE

SDA
LINE

Note)

Fig.43 Random read cycle (BR24T01/02/04/08/16-W)

S
T
A

SLAVE

R

ADDRESS

T

A2

10 0

1

Note)

Fig.44 Random read cycle (BR24T32/64/128/256/512/1M-W)

S
T
A

SLAVE

R

ADDRESS

T

10 0 1 A0 A1 A2 D0 D7

Fig.45 Current read cycle

S
T
A

SLAVE

R

ADDRESS

T

SDA
LINE

1

10 0

Note）

Fig.46 Sequential read cycle (in the case of current read cycle)

W

R

I
T
E

R

/

W

W
R

I
T
E

WA

WA

A1

A0 D7 D0

15

14

A

R

C

/

K

W

Note)

R
E
A
D

A0

A2

A1

R

/

W

WORD

ADDRESS(n)

WA

7

*1

A
C
K

1st WORD
ADDRESS

WA

13 WA12WA11

A

*1

C
K

R

E
A

D

R

W

A

C

K

DATA(n)

A
C

/

K

DATA

D7 D0

S
T
A
R
T

WA

0

A
C
K

2nd WORD

ADDRESS(n)

A
C
K

D0

A
C
K

SLAVE

ADDRESS

10 0 1A1 A2

S
T
A
R

ADDRESS

T

WA

100

0

A
C
K

S

T
O
P

R
E
A
D

A0 D0

R

W

SLAVE

A1

A0

A2

1

A
C
K

/

W

D7

D7

A
C
K

R
E
A
D

A

R

C

/

K

DATA(n)

DATA(n)

DATA(n+x

A
C
K

S
T

O

P

A
C
K

S
T
O
P

A

C

K

S
T

O

P

*1 As for WA7,BR24T01-W be come Don’t care.

*1 As for WA12, BR24T32-W become Don’t care.
As for WA13, BR24T32/64-W become Don’t care.
As for WA14, BR24T32/64/128-W become Don’t care.
As for WA15, BR24T32/64/128/256-W become Don’t care.

*1 As for WA7, BR24T01-W becomes Don't care.
*2 As for BR24T01/02-W becomes (n+7)

*1 As for WA12, BR24T32-W becomes Don't care.
As for WA13, BR24T32/64-W becomes Don't care.
As for WA14, BR24T32/64/128-W becomes Don't care.
As for WA15, BR24T32/64/128/256-W becomes Don't care.

*2 As for BR24T128/256-W becomes (n+63)
As for BR24T512-W becomes (n+127)
As for BR24T1M-W becomes (n+255)

・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential

read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.

・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (µ-COM) side, the next

address data can be read in succession.

・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL

signal 'H' .

・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.

Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.

・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL

signal 'H'.

Note)

1

0

*1 *2 *3

0

A2

A1

1A0

*1 In BR24T16-W, A2 becomes P2.
*2 In BR24T08/16-W, A1 becomes P1.
*3 In BR24T08/16/1M-W, A0 becomes P0.

Fig.47 Difference of slave address of each type

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11/2 1

2011.03 - Rev.A

BR24T□□□□Series

A

A

A

A

A

A

Technical Note

●Software reset

Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.48-(a), Fig.48-(b), Fig.48-(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.

SCL

SDA

Dummy clock×14

1 2 13 14

Star t×2

Normal command

Normal command

Fig.48-(a) The case of dummy clock +START+START+ command input

SCL

SDA

Start

Dummy clock×9

2 1 8 9

Start

Normal command

Normal command

Fig.48-(b) The case of START +9 dummy clocks +START+ command input

SCL

SDA

1 2 3 8 9 7

Star t×9

Normal command

Normal command

Fig.48-(c) START×9+ command input

※Start command from START input.

●Acknowledge polling

During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.

When to write continuously,

W/R

= 0, when to carry out current read cycle after write, slave address

W/R

= 1 is sent,

and if ACK signal sends back 'L', then execute word address input and data output and so forth.

First write command

S
T
A

Write command
R
T

S

S

T

T
O
P

A
R
T

Slave

address

Second write command

During internal write,
ACK = HIGH is sent back.

S
T

tWR

A
R
T

Slave

address

C
K
H

C

…

K
H

…

S
T
A
R
T

Slave

address

tWR

C
K
H

S
T
A
R
T

Slave

address

Word

C
K

address

L

After completion of internal write,
ACK=LOW is sent back, so input
next word address and data in
succession.

C
K
L

Data

C
K
L

S
T
O
P

Fig.49 Case to continuously write by acknowledge polling

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2011.03 - Rev.A

BR24T□□□□Series

Technical Note

●WP valid timing (write cancel)

WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. The area from the rise of SCL to take in D0 to input the stop condition is cancel
valid area. And, after execution of forced end by WP, standby status gets in.

・Rise of D0 taken clock

・Rise of SDA

SCL

SDA

D0 ACK

D1

Enlarged view

SCL

SDA

ACK D0

Enlarged view

SDA

WP

S
T
A
R
T

A

Slave

address

Word

C
K

address

L

WP cancel invalid area

A
C
K

L

D7 D6

D5

D4

D3

D2

D0

D1

Data is not written.

A
C

Data

K
L

WP cancel valid area

A
C
K
L

O

S
T

P

tWR

WP cancel invalid area

Fig.50 WP valid timing

●Command cancel by start condition and stop condition

During command input, by continuously inputting start condition and stop condition, command can be cancelled. (Fig.51)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.

SCL

SDA

1 1 0 0

Start condition Stop condition

Fig.51 Case of cancel by start, stop condition during slave address input

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2011.03 - Rev.A

BR24T□□□□Series

●I/O peripheral circuit

○Pull up resistance of SDA terminal

SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R
this resistance value from microcontroller V
limited. The smaller the R

, the larger the consumption current at action.

PU

, IL, and VOL-I

IL

characteristics of this IC. If RPU is large, action frequency is

OL

○Maximum value of RPU

The maximum value of R

is determined by the following factors.

PU

①SDA rise time to be determined by the capacitance (CBUS) of bus line of R

And AC timing should be satisfied even when SDA rise time is late.

②The bus electric potential

SDA bus and R

should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including

PU

A to be determined by input leak total (IL) of device connected to bus at output of 'H' to

○

recommended noise margin 0.2Vcc.

CC－ILRPU－0.2 VCC ≧ VIH

V

IHCC

VV8.0

R

PU

I

L

Microcontroller

Ex.) VCC =3V IL=10µA VIH=0.7 VCC

from②

37.038.0



R



PU

1010



6



 300 [kΩ]

Technical Note

), select an appropriate value to

PU

and SDA should be tR or below.

PU

BR24TXX

RPU

A

L

I

Bus line
capacity

CBUS

SDA

IL

terminal

Fig.52 I/O circuit diagram

○ Minimum value of RPU

The minimum value of R
When IC outputs LOW, it should be satisfied that V



OLCC

VV

OL

I



PU

R

VVR



②V



PU

OLMAX= should secure the input 'L' level (V

OLCC

OL

I

is determined by the following factors.

PU

OLMAX

) of microcontroller and EEPROM

IL

=0.4V and I

OLMAX

=3mA.

including recommended noise margin 0.1Vcc.

OLMAX ≦ VIL－0.1 VCC

V

CC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM V

Ex.) V

4.03



from①

R

PU



 867[Ω]

And

VOL=0.4［V］

3



103



=0.3Vcc

IL

VIL=0.3×3

=0.9［V］

Therefore, the condition ② is satisfied.

○Pull up resistance of SCL terminal

When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.

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© 2011 ROHM Co., Ltd. All rights reserved.

14/21

2011.03 - Rev.A

BR24T□□□□Series





A

A

Technical Note

●Cautions on microcontroller connection
○RS

2

C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of

In I
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.

RPU

R

S

SCL

SDA

'H' output of microcontroller

CK

'L' output of EEPROM

Microcontroller

Fig.53 I/O circuit diagram Fig.54 Input / output collision timing

EEPROM

Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.

○Maximum value of Rs

The maximum value of Rs is determined by the following relations.
①SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.

And AC timing should be satisfied even when SDA rise time is late.

②The bus electric potential

sufficiently secure the input 'L' level (V

A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus

○

) of microcontroller including recommended noise margin 0.1Vcc.

IL



OLCC

VV

V

IL

Micro controller

V

CC

Bus line
capacity
CBUS

R

PU

S

R

I

OL

V

OL

EEPROM

Ex)VCC=3V VIL=0.3VCC VOL=0.4V RPU=20kΩ

Fig.55 I/O Circuit Diagram



SPU

RR





OLCC

VV

S R

R 





ILCC

VV1.1



31.04.033.0

S

R 





33.031.1



]k[67.1 Ω

PU

ILCCOL

VV1.0V



3

1020

○Minimum value of Rs

The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the
following relation must be satisfied. Determine the allowable current in consideration of impedance of power source line
in set and so forth. Set the over current to EEPROM 10mA or below.

CC

EX) V

R

V



R

S

V

S



R

=3V I=1mA

CC

S



CC

I

I

3

3



1010



][300

Ω

'H' output

Microcontroller

R

PU

R

S

Over current I

'L'output

EEPROM

Fig.56 I/O circuit diagram

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© 2011 ROHM Co., Ltd. All rights reserved.

15/21

2011.03 - Rev.A

BR24T□□□□Series

●I2C BUS input / output circuit
○Input (A0, A1, A2, SCL, WP)

○Input / output (SDA)

Technical Note

Fig.57 Input pin circuit diagram

Fig.58 Input / output pin circuit diagram

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© 2011 ROHM Co., Ltd. All rights reserved.

16/21

2011.03 - Rev.A

BR24T□□□□Series

A

A

Technical Note

●Notes on power ON

At power on, in IC internal circuit and set, Vcc rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.

1. Set SDA = 'H' and SCL ='L' or 'H’

, t

2. Start power source so as to satisfy the recommended conditions of t

CC

V

tR

Recommended conditions of tR, tOFF,Vbot

, and Vbot for operating POR circuit.

R

OFF

tR tOFF Vbot

tOFF

0

Fig.59 Rise waveform diagram

Vbot

10ms or below 10ms or larger 0.3V or below

100msor below 10msor larger 0.2V or below

3. Set SDA and SCL so as not to become 'Hi-Z'.

When the above conditions 1 and 2 cannot be observed, take the following countermeasures.

a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.

V

CC

SCL

tLOW

SDA

fter Vcc becomes stable

Fig.60 When SCL= 'H' and SDA= 'L'

tSU:DAT

tDH

fter Vcc becomes stable

Fig.61

When SCL='L' and SDA='L'

tSU:DAT

b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P12).
c) In the case when the above conditions 1 and 2 cannot be observed.

→Carry out a), and then carry out b).

●Low voltage malfunction prevention function

LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.

●Vcc noise countermeasures
○Bypass capacitor

When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a bypass capacitor (0.1µF) between IC Vcc and GND. At that moment, attach it as close to IC as
possible. And, it is also recommended to attach a bypass capacitor between board Vcc and GND.

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© 2011 ROHM Co., Ltd. All rights reserved.

17/21

2011.03 - Rev.A

BR24T□□□□Series

●Notes for use

(1) Described numeric values and data are design representative values, and the values are not guaranteed.

(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further

sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.

(3) Absolute maximum ratings

If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it
that conditions exceeding the absolute maximum ratings should not be impressed to LSI.

(4) GND electric potential

Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that
of GND terminal.

(5) Terminal design

In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.

(6) Terminal to terminal shortcircuit and wrong packaging

When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.

(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.

Technical Note

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© 2011 ROHM Co., Ltd. All rights reserved.

18/21

2011.03 - Rev.A

BR24T□□□□Series

●Order part number

B R 2 4 T 1 2 8 F V T - W G E 2

Part No. BUS type

DIP-T8

3.4±0.3

3.2±0.2

SOP8

6.2±0.3

SOP-J8

6.0±0.3

1.375±0.1

2

C

24：I

9.3±0.3

85

1

0.51Min.

2.54

5.0±0.2

(MAX 5.35 include BURR)

4.4±0.2

0.595

1.5±0.1

0.11

1.27

4.9±0.2

(MAX 5.25 include BURR)

3.9±0.2

234

0.545

1

1.27

0.175

4

7

0.5±0.1

6

438251

0.42±0.1

5678

6.5±0.3

0.42±0.1

0.1

Operating
temperature/
Power source
Voltage

-40℃~+85℃

1.7V~5.5V

7.62

0°−15°

4

°

0.17

S

0.1 S

4°

S

S

Capacity
01=1K 64=64K
02=2K 128=128K
04=4K 256=256K
08=8K 512=512K
16=16K 1M=1024K
32=32K

0.3±0.1

(Unit : mm)

+

6

°

−4°

0.3MIN

+0.1

-

0.05

(Unit : mm)

+

6°

−4°

0.45MIN

0.2±0.1

(Unit : mm)

0.9±0.15

Package
Blank :DIP-T8
F :SOP8
FJ :SOP-J8
FV : SSOP-B8
FVT : TSSOP-B8
FVJ : TSSOP-B8J
FVM : MSOP8
NUX :VSON008X2030

<Tape and Reel information>

TubeContainer
Quantity
Direction of feed

2000pcs

Direction of products is fixed in a container tube

<Tape and Reel information>

Embossed carrier tapeTape

Quantity

Direction
of feed

2500pcs
E2

The direction is the 1pin of product is at the upper left when you hold

()

reel on the left hand and you pull out the tape on the right hand

Reel

<Tape and Reel information>

Embossed carrier tapeTape

Quantity

Direction
of feed

2500pcs
E2

The direction is the 1pin of product is at the upper left when you hold

()

reel on the left hand and you pull out the tape on the right hand

Reel

Double
Cell

Order quantity needs to be multiple of the minimum quantity.

∗

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

Halogen
Free

Technical Note

Packaging and forming specification
E2: Embossed tape and reel
(SOP8, SOP8-J8, SSOP-B8,
TSSOP-B8, TSSOP-B8J)
TR: Embossed tape and reel
(MSOP8, VSON008X2030)
None: Tube
(DIP-T8)

Direction of feed

Direction of feed

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© 2011 ROHM Co., Ltd. All rights reserved.

19/21

2011.03 - Rev.A

BR24T□□□□Series

TSSOP-B8

3.0± 0.1

(MAX 3.35 include BURR)

8765

4.4± 0.1

6.4± 0.2

1.2MAX

1.0± 0.05

0.525

0.1± 0.05

1

0.65

234

1PIN MARK

0.245

+0.05

−0.04

TSSOP-B8J

3.0± 0.1

(MAX 3.35 include BURR)

578

6

3.0± 0.1

4.9± 0.2

1.1MAX

0.85±0.05

1234

0.525

0.1±0.05

0.65

1PIN MARK

0.32

MSOP8

4.0±0.2

0.9MAX

0.75±0.05

2.9±0.1

(MAX 3.25 include BURR)

6

57

8

2.8±0.1

1

4

2

3

0.475

0.08±0.05

1PIN MARK

0.22

0.08 S

0.65

0.08 S

+0.05

−0.04

+0.05

−0.04

S

S

4 ± 4

0.145

0.08

0.08 S

0.08

S

0.5± 0.15

4 ± 4

0.145

M

4°

M

0.45± 0.15

+

−4°

0.145

6°

1.0± 0.2

+0.05

−0.03

(Unit : mm)

0.95± 0.2

+0.05

−0.03

(Unit : mm)

0.29±0.15

+0.05

−0.03

(Unit : mm)

Technical Note

<Tape and Reel information>

Embossed carrier tapeTape

Quantity

Direction
of feed

<Tape and Reel information>

Quantity

Direction
of feed

<Tape and Reel information>

Quantity

0.6±0.2

Direction
of feed

3000pcs
E2

The direction is the 1pin of product is at the upper left when you hold

()

reel on the left hand and you pull out the tape on the right hand

Direction of feed

Reel

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

Embossed carrier tapeTape
2500pcs

E2

The direction is the 1pin of product is at the upper left when you hold

()

reel on the left hand and you pull out the tape on the right hand

Direction of feed

Reel

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

Embossed carrier tapeTape
3000pcs

TR

The direction is the 1pin of product is at the upper right when you hold

()

reel on the left hand and you pull out the tape on the right hand

1pin

Direction of feed

Reel

Order quantity needs to be multiple of the minimum quantity.

∗

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© 2011 ROHM Co., Ltd. All rights reserved.

20/21

2011.03 - Rev.A

BR24T□□□-W Series

VSON008X2030

2.0±0.1

1PIN MARK

0.6MAX

0.08 S

C0.25

0.3±0.1

0.25

1.5±0.1

0.5

+0.03

4

518

+0.05

0.25

−0.04

3.0±0.1

−0.02

0.02

Technical Note

<Tape and Reel information>

Embossed carrier tapeTape

Quantity

S

(0.12)

1.4±0.1

(Unit : mm)

Direction
of feed

4000pcs
TR

The direction is the 1pin of product is at the upper right when you hold

()

reel on the left hand and you pull out the tape on the right hand

Direction of feed

Reel

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

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© 2011 ROHM Co., Ltd. All rights reserved.

21/21

2011.03 - Rev.A

Notes

No copying or reproduction of this document, in par t or in whole, is permitted without the
consent of ROHM Co.,Ltd.

The content specied herein is subject to change for improvement without notice.

The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.

The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.

The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, commu­nication devices, electronic appliances and amusement devices).

The Products specied in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel­controller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology specied herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.

Notice

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Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.

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R1120

A