ROHM BR24A01A Technical data

Serial EEPROM Series

High Reliability Series EEPROMs I2C BUS

BR24A□□-WM series

●Description

BR24A□□-WM series is a serial EEPROM of I

●Features

1) Completely conforming to the world standard I

2) Other devices than EEPROM can be connected to the same port, saving microcontroller port

3) 2.5V~5.5V single power source action most suitable for battery use

4) Page write mode useful for initial value write at factory shipment

5) Highly reliable connection by Au pad and Au wire

6) Auto erase and auto end function at data rewrite

7) Low current consumption At write operation (5V) : 1.2mA (Typ.) At read operation (5V) : 0.2mA (Typ.) At standby operation (5V) : 0.1μA (Typ.)

8) Write mistake prevention function Write (write protect) function added Write mistake prevention function at low voltage

9) SOP8/SOP-J8/MSOP8 compact package

10) Data rewrite up to 100,000 times

11) Data kept for 40 years

12) Noise filter built in SCL / SDA terminal

13) Shipment data all address FFh

*1 BR24A32-WM,BR24A64-WM : 1.5mA *2 Refer to following list

●Page write

Number of Pages 8Byte 16Byte 32Byte

Product number

●BR24A series

Capacity Bit format Type Power source Voltage SOP8 SOP-J8 MSOP8

1Kbit 128×8 BR24A01A-WM 2.5～5.5V ● ● 2Kbit 256×8 BR24A02-WM 2.5～5.5V ● ● ● 4Kbit 512×8 BR24A04-WM 2.5～5.5V ● ●

8Kbit 1K×8 BR24A08-WM 2.5～5.5V ● ● 16Kbit 2K×8 BR24A16-WM 2.5～5.5V ● ● 32Kbit 4K×8 BR24A32-WM 2.5～5.5V ● 64Kbit 8K×8 BR24A64-WM 2.5～5.5V ●

BR24A01A-WM

BR24A02-WM

2

C BUS interface method.

2

C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA)

*1

*2

BR24A04-WM BR24A08-WM BR24A16-WM

No.09001ECT02

BR24A32-WM BR24A64-WM

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2009.08 - Rev.C

BR24A□□-WM series

Technical Note

●Absolute maximum ratings (Ta=25℃)

Parameter symbol Limits Unit

Impressed voltage VCC -0.3～+6.5 V

450 (SOP8)

Permissible dissipation Pd

450 (SOP-J8) *2

*1

mW

310 (MSOP8) *3

Storage temperature range Tstg -65～+125 ℃ Action temperature range Topr -40～+105 ℃ Terminal voltage - -0.3～VCC+1.0 V

When using at Ta=25℃ or higher, 4.5mW(*1,*2) , 3.1mW(*3) to be reduced per 1℃

●Memory cell characteristics (VCC=2.5～5.5V)

Parameter

Min.

Number of data rewrite times *1 100,000

Limits

Typ.

-

Max.

Unit Test Condition

- Times Ta=-40～105℃

Data hold years *1 40 - - Years Ta=25℃

○Shipment data all address FFh *1 Not 100% TESTED

●Recommended operating conditions

Parameter Symbol Limits Unit

Power source voltage VCC 2.5～5.5 Input voltage VIN 0～VCC

●Electrical characteristics (Unless otherwise specified, Ta=-40～+105℃, VCC=2.5～5.5V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Conditions

V

“HIGH” input voltage VIH 0.7VCC - - V “LOW” input voltage VIL - - 0.3 VCC V “LOW” output voltage 1 VOL - - 0.4 V IOL=3.0mA (SDA) Input leak current ILI -1 - 1 μA VIN=0V～VCC Output leak current ILO -1 - 1 μA VOUT=0V～VCC, (SDA)

Current consumption at action

ICC1 - -

ICC2 - - 0.5 mA

Standby current ISB - - 2.0 μA

◎Radiation resistance design is not made. *1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM

*1

2.0

3.0 *2

VCC=5.5V,f

mA

Byte write, Page write VCC=5.5V,f

SCL=400kHz, tWR=5ms,

SCL=400kHz

Random read, current read, sequential read VCC=5.5V, SDA・SCL=VCC A0, A1, A2=GND, WP=GND

●Action timing characteristics (Unless otherwise specified, Ta=

Parameter Symbol

-40～+105℃, VCC=2.5～5.5V)

FAST-MODE

2.5V≦VCC≦5.5V

STANDARD-MODE

2.5V≦VCC≦5.5V

Unit

Min. Typ. Max. Min. Typ. Max. SCL frequency fSCL - - 400 - - 100 kHz Data clock “HIGH“ time tHIGH 0.6 - - 4.0 - - μs Data clock “LOW“ time tLOW 1.2 - - 4.7 - - μs SDA, SCL rise time *1 tR - - 0.3 - - 1.0 μs SDA, SCL fall time *1 tF - - 0.3 - - 0.3 μs Start condition hold time tHD:STA 0.6 - - 4.0 - - μs Start condition setup time tSU:STA 0.6 - - 4.7 - - μs Input data hold time tHD:DAT 0 - - 0 - - ns Input data setup time tSU:DAT 100 - - 250 - - ns Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 μs Output data hold time tDH 0.1 - - 0.2 - - μs Stop condition setup time tSU:STO 0.6 - - 4.7 - - μs Bus release time before transfer start tBUF 1.2 - - 4.7 - - μs Internal write cycle time tWR - - 5 - - 5 ms Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs WP hold time tHD:WP 0 - - 0 - - ns WP setup time tSU:WP 0.1 - - 0.1 - - μs WP valid time tHIGH:WP 1.0 - - 1.0 - - μs

*1 Not 100% tested

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2009.08 - Rev.C

A

BR24A□□-WM series

Technical Note

●FAST-MODE and STANDARD-MODE

FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds. 100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the maximum action frequency, so 100kHz clock may be used in FAST-MODE. At VCC=2.5V～5.5V , 400kHz, namely, action is made in FASTMODE. (Action is made also in STANDARD-MODE.)

●Sync data input / output timing

SCL

tHD:STA tHD:DAT

SD

(入力)

(input)

SDA

(output)

(出力)

tBUF

○Input read at the rise edge of SCL ○Data output in sync with the fall of SCL

tSU:DAT

tHIGHtR tF

tLOW

tPD tDH

SCL

tSU:STA tSU:STOtHD:STA

SDA

START BIT

STOP BIT

Fig.1-(a) Sync data input / output timing Fig.1-(b) Start-stop bit timing

SCL

SDA

D0

Write data

(n-th address)

ACK

Stop condition

ｔWR

Start condition

SCL

SDA

WP

DATA(1)

D1 D0ACK

tSU：WP

DATA(n)

CK

WR

ｔ

Stop condition

ストップコンディション

ｔHD：

WP

Fig.1-(c) Write cycle timing Fig.1-(d) WP timing at write execution

SCL

DATA(1)

D1 D0 ACK ACK

SDA

WP

○At write execution, in the area from the D0 taken clock rise of the first

DATA(1), to tWR, set WP=“LOW”.

○By setting WP “HIGH” in the area, write can be cancelled.

When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of address under access is not guaranteed, therefore write it once again.

DATA(n)

tHIGH:WP

Fig.1-(e) WP timing at write cancel

tWR

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3/17

2009.08 - Rev.C

y

BR24A□□-WM series

●Block diagram

*2

1

A0

*2

A1

2

*2

3

A2

GND

4

1

＊

8bit : BR24A02-WM

High voltage

generating circuit

7bit : BR24A01A-WM

9bit : BR24A04-WM

●Pin assignment and description

Terminal

name

Input / output

BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM

*1

7bit

11bit

8bit

12bit 13b

9bit

t

10bi

Address decoder

it

7bit 8bit

*1

9bit 10bi

Control circuit

10bit : BR24A08-WM 11bit : BR24A16-WM 12bit : BR24A32-WM 13bit : BR24A64-WM

1Kbit~64Kbit EEPROM arra

11bit

Slave - word

12bit

it

13b

t

address register

START STOP

Power source

voltage detection

＊

2 A0=N.C. : BR24A04-WM

A0, A1=N.C. : BR24A08-WM

A0, A1= N.C. A2=Don’t Use : BR24A16-WM

Fig.2 Block diagram

A0

1

BR24A01A-WM

A1

2

BR24A02-WM BR24A04-WM BR24A08-WM

A2

3

BR24A16-WM BR24A32-WM BR24A64-WM

4

GND

ACK

8

Vcc

WP

7

6

SCL

5

SDA

Function

8bit

Data

register

Technical Note

8

Vcc

7

WP

6

SCL

5

SDA

A0 Input Slave address setting Not connected Slave address setting

A1 Input Slave address setting Not connected Slave address setting

A2 Input Slave address setting Not used Slave address setting

GND - Reference voltage of all input / output, 0V

SDA

Input / output

SCL Input Serial clock input

WP Input Write protect terminal

Vcc - Connect the power source.

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Slave and word address, Serial data input serial data output

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2009.08 - Rev.C

BR24A□□-WM series

●Characteristic data (The following values are Typ. ones.)

6

5

4

3

VIH1,2[V]

2

1

0

0123456

Fig.3 H input voltage VIH1,2　(SCL,SDA,WP) Fig.4 L input voltageVIL1,2　(SCL,SDA,WP)

1.2

1

0.8

0.6

ILI[μA]

0.4

0.2

0

0123456

Fig.6 Input leak current ILI　(SCL,WP) Fig.7 Output leak current　ILO(SDA)

3.5

3

fSCL=400kHz DATA=AAh

2.5

2

1.5

ICC1[mA]

1

0.5

0

0123456

Fig.9 Current consumption at WRITE action ICC1

3.5

3

fSCL=100kHz

2.5

DATA=AAh

2

1.5

ICC1[mA]

1

0.5

0

0123456

Fig.12 Current consumption at WRITE action ICC1

10000

SPEC

Vcc[V]

SPEC

Vcc[V]

SPEC

Vcc[V]

(fSCL=400kHz)

SPEC

Vcc[V]

(fSCL=100kHz)

Ta=105℃ Ta=-40℃ Ta=25℃

Ta=105℃ Ta=25℃ Ta=-40℃

[BR24A32/64 series]

Ta=25℃ Ta=105℃ Ta=-40℃

[BR24A32/64 series]

Ta=25℃ Ta=105℃ Ta=-40℃

1000

fSCL[kHz]

100

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC1

SPEC2

10

1

0123456

5

4

3

2

tHD:STA[μs]

1

0

0123456

Fig.18 Start condition hold time　tHD:STA

Vcc[V]

Fig.15 SCL frequency　fSCL

SPEC2

Ta=105℃

SPEC1

Ta=25℃

Ta=-40℃

Vcc[V]

6

5

4

3

VIL1,2[V]

2

1

0

0123456

1.2

1

0.8

0.6

ILO[μA]

0.4

0.2

0

0123456

0.6

0.5

0.4

0.3

ICC2[mA]

0.2

0.1

0

0123456

Fig.10 Current consumption at READ action ICC2

0.6

0.5

0.4

0.3

ICC2[mA]

0.2

0.1

0

0123456

Fig.13 Current consumption at READ action ICC2

5

4

3

2

tHIGH [μs]

1

0

0123456

6

5

4

3

2

tSU:STA[μs]

1

0

0123456

SPEC

fSCL=400kHz DATA=AAh

SPEC

fSCL=100kHz DATA=AAh

Ta=25℃

SPEC2

Fig.16 Data clock "H" time tHIGH

SPEC2

Ta=-40℃

Ta=25℃

Ta=105℃

Fig.19 Start condition setup time tSU:STA Fig.20 Input data hold time tHD:DAT(HIGH)

Vcc[V]

SPEC

Vcc[V]

(fSCL=400kHz)

Ta=105℃

Ta=-40℃

Vcc[V]

(fSCL=100kHz)

Ta=-40℃ Ta=25℃ Ta=105℃

Vcc[V]

SPEC1

Vcc[V]

Ta=105℃ Ta=-40℃ Ta=25℃

SPEC

Ta=105℃ Ta=25℃ Ta=-40℃

Ta=105℃

Ta=25℃

Ta=-40℃

SPEC1

Technical Note

1

0.8

0.6

0.4

VOL1[V]

0.2

0

0123456

Fig.5 L output voltage　VOL1-IOL1　(VCC=2.5V)

2.5

2

fSCL=400kHz DATA=AAh

1.5

1

ICC1[mA]

0.5

0

0123456

Fig.8 Current consumption at WRITE action ICC1

2.5

2

fSCL=100kHz DATA=AAh

1.5

1

ICC1[mA]

0.5

0

0123456

Fig.11 Current consumption at WRITE action ICC1

2.5

2

1.5

1

ISB[μA]

0.5

0

0123456

Fig.14 Standby current　ISB

5

4

3

2

tLOW[μs]

1

0

0123456

Fig.17 Data clock "L" time tLOW

50

0

-50

-100

tHD:DAT(HIGH)[ns]

-150

-200 0123456

IOL1[mA]

[BR24A01/02/04/08/16 series]

Vcc[V]

(fscl=400kHz)

[BR24A01/02/04/08/16 series]

SPEC

Vcc[V]

(fSCL=100kHz)

SPEC

Ta=105℃

Vcc[V]

SPEC2

SPEC1

Ta=105℃

Ta=25℃

Ta=-40℃

Vcc[V]

SPEC1,2

Vcc[V]

SPEC

Ta=-40℃

Ta=105℃

Ta=-40℃ Ta=25℃ Ta=105℃

Ta=25℃

Ta=-40℃

Ta=25℃ Ta=105℃ Ta=-40℃

Ta=25℃

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5/17

2009.08 - Rev.C

BR24A□□-WM series

●Characteristic data (The following values are Typ. ones.)

50

0

-50

-100

tHD:DAT(LOW)[ns]

-150

-200 0123456

4

3

SPEC1,2

Ta=105℃

Ta=25℃

Ta=-40℃

Fig.21 Input data hold time　tHD:DAT(LOW) Fig.22 Input data setup time　tSU:DAT(HIGH)

Vcc[V]

SPEC2

300

200

100

0

tSU:DAT(HIGH)[ns]

-100

-200 0123456

4

3

SPEC2

2

tPD0[μs]

tWR[ms]

0.6

0.5

0.4

0.3

0.2

tI(SDA H)[μs]

0.1

1.2

0.8

0.6

0.4

tHIGH:WP[μs]

0.2

Ta=105℃

Ta=25℃

Ta=-40℃

1

SPEC2

SPEC1

0

0123456

Fig.24 Output data delay time tPD0 Fig.25 Output data delay time　tPD1

6

5

4

3

2

1

0

0123456

Fig.27 Internal write cycle time　tWR

Ta=25℃

0

0123456

Fig.30 Noise removal valid time tI(SDA H) Fig.31 Noise removal valid time tI(SDA L) Fig.32 WP setup time　tSU:WP

1

0

0123456

Fig.33 WP valid time　tHIGH:WP

SPEC1,2

Vcc[V]

SPEC1

Ta=-40℃

Ta=105℃

Ta=25℃

Ta=-40℃

Ta=-40℃ Ta=25℃ Ta=105℃

2

Ta=-40℃

Ta=25℃

tPD1[μs]

Ta=105℃

1

SPEC2

SPEC1

0

0123456

0.6

0.5

0.4

Ta=25℃

SPEC1,2

0123456

Fig.28 Noise rem oval valid time tI(S CL H)

Ta=25℃

SPEC1

0123456

tI(SDA L)[μs]

0.3

0.2

tI(SCL H)[μs]

0.1

0.6

0.5

0.4

0.3

0.2

0.1

0

SPEC1

Vcc[V]

SPEC1

Vcc[V]

Ta=105℃

Vcc[V]

Ta=-40℃

Ta=105℃

Ta=105℃ Ta=25℃ Ta=-40℃

300

200

100

0

tSU:DAT(LOW)[ns]

-100

-200 0123456

5

4

3

2

tBUF[μs]

1

0

0123456

Fig.26 Bus release time before transfer start tBUF

0.6

0.5

0.4

0.3

0.2

tI(SCL L)[μs]

0.1

0

0123456

0.2

0

-0.2

tSU:WP[μs]

-0.4

-0.6 0123456

SPEC2

SPEC1

Ta=105℃

Ta=25℃

Ta=-40℃

Vcc[V]

Fig.23 Input data setup time tSU:DAT(LOW)

SPEC2

Ta=-40℃

SPEC1

Ta=25℃

Ta=105℃

Vcc[V]

Ta=-40℃

Ta=25℃

Ta=105℃

SPEC1

Vcc[V]

Fig.29 Noise removal valid time tI(SCL L)

SPEC1,2

Ta=25℃

Ta=105℃

Ta=-40℃

Vcc[V]

Technical Note

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2009.08 - Rev.C