Serial EEPROM Series
High Reliability Series
EEPROMs I2C BUS
BR24A□□-WM series
●Description
BR24A□□-WM series is a serial EEPROM of I
●Features
1) Completely conforming to the world standard I
2) Other devices than EEPROM can be connected to the same port, saving microcontroller port
3) 2.5V~5.5V single power source action most suitable for battery use
4) Page write mode useful for initial value write at factory shipment
5) Highly reliable connection by Au pad and Au wire
6) Auto erase and auto end function at data rewrite
7) Low current consumption
At write operation (5V) : 1.2mA (Typ.)
At read operation (5V) : 0.2mA (Typ.)
At standby operation (5V) : 0.1μA (Typ.)
8) Write mistake prevention function
Write (write protect) function added
Write mistake prevention function at low voltage
9) SOP8/SOP-J8/MSOP8 compact package
10) Data rewrite up to 100,000 times
11) Data kept for 40 years
12) Noise filter built in SCL / SDA terminal
13) Shipment data all address FFh
*1 BR24A32-WM,BR24A64-WM : 1.5mA
*2 Refer to following list
●Page write
Number of Pages 8Byte 16Byte 32Byte
Product
number
●BR24A series
Capacity Bit format Type Power source Voltage SOP8 SOP-J8 MSOP8
1Kbit 128×8 BR24A01A-WM 2.5～5.5V ● ●
2Kbit 256×8 BR24A02-WM 2.5～5.5V ● ● ●
4Kbit 512×8 BR24A04-WM 2.5～5.5V ● ●
8Kbit 1K×8 BR24A08-WM 2.5～5.5V ● ●
16Kbit 2K×8 BR24A16-WM 2.5～5.5V ● ●
32Kbit 4K×8 BR24A32-WM 2.5～5.5V ●
64Kbit 8K×8 BR24A64-WM 2.5～5.5V ●
BR24A01A-WM
BR24A02-WM
2
C BUS interface method.
2
C BUS. All controls available by 2 ports of serial clock(SCL) and serial data(SDA)
*1
*2
BR24A04-WM
BR24A08-WM
BR24A16-WM
No.09001ECT02
BR24A32-WM
BR24A64-WM
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1/17
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
●Absolute maximum ratings (Ta=25℃)
Parameter symbol Limits Unit
Impressed voltage VCC -0.3～+6.5 V
450 (SOP8)
Permissible dissipation Pd
450 (SOP-J8) *2
*1
mW
310 (MSOP8) *3
Storage temperature range Tstg -65～+125 ℃
Action temperature range Topr -40～+105 ℃
Terminal voltage - -0.3～VCC+1.0 V
When using at Ta=25℃ or higher, 4.5mW(*1,*2) , 3.1mW(*3) to be reduced per 1℃
●Memory cell characteristics (VCC=2.5～5.5V)
Parameter
Min.
Number of data rewrite times *1 100,000
Limits
Typ.
-
Max.
Unit Test Condition
- Times Ta=-40～105℃
Data hold years *1 40 - - Years Ta=25℃
○Shipment data all address FFh
*1 Not 100% TESTED
●Recommended operating conditions
Parameter Symbol Limits Unit
Power source voltage VCC 2.5～5.5
Input voltage VIN 0～VCC
●Electrical characteristics (Unless otherwise specified, Ta=-40～+105℃, VCC=2.5～5.5V)
Parameter Symbol
Min. Typ. Max.
Limits
Unit Conditions
V
“HIGH” input voltage VIH 0.7VCC - - V
“LOW” input voltage VIL - - 0.3 VCC V
“LOW” output voltage 1 VOL - - 0.4 V IOL=3.0mA (SDA)
Input leak current ILI -1 - 1 μA VIN=0V～VCC
Output leak current ILO -1 - 1 μA VOUT=0V～VCC, (SDA)
Current consumption
at action
ICC1 - -
ICC2 - - 0.5 mA
Standby current ISB - - 2.0 μA
◎Radiation resistance design is not made.
*1 BR24A01A/02/04/08/16-WM, *2 BR24A32/64-WM
*1
2.0
3.0 *2
VCC=5.5V,f
mA
Byte write, Page write
VCC=5.5V,f
SCL=400kHz, tWR=5ms,
SCL=400kHz
Random read, current read, sequential read
VCC=5.5V, SDA・SCL=VCC
A0, A1, A2=GND, WP=GND
●Action timing characteristics (Unless otherwise specified, Ta=
Parameter Symbol
-40～+105℃, VCC=2.5～5.5V)
FAST-MODE
2.5V≦VCC≦5.5V
STANDARD-MODE
2.5V≦VCC≦5.5V
Unit
Min. Typ. Max. Min. Typ. Max.
SCL frequency fSCL - - 400 - - 100 kHz
Data clock “HIGH“ time tHIGH 0.6 - - 4.0 - - μs
Data clock “LOW“ time tLOW 1.2 - - 4.7 - - μs
SDA, SCL rise time *1 tR - - 0.3 - - 1.0 μs
SDA, SCL fall time *1 tF - - 0.3 - - 0.3 μs
Start condition hold time tHD:STA 0.6 - - 4.0 - - μs
Start condition setup time tSU:STA 0.6 - - 4.7 - - μs
Input data hold time tHD:DAT 0 - - 0 - - ns
Input data setup time tSU:DAT 100 - - 250 - - ns
Output data delay time tPD 0.1 - 0.9 0.2 - 3.5 μs
Output data hold time tDH 0.1 - - 0.2 - - μs
Stop condition setup time tSU:STO 0.6 - - 4.7 - - μs
Bus release time before transfer start tBUF 1.2 - - 4.7 - - μs
Internal write cycle time tWR - - 5 - - 5 ms
Noise removal valid period (SDA, SCL terminal) tI - - 0.1 - - 0.1 μs
WP hold time tHD:WP 0 - - 0 - - ns
WP setup time tSU:WP 0.1 - - 0.1 - - μs
WP valid time tHIGH:WP 1.0 - - 1.0 - - μs
*1 Not 100% tested
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2/17
2009.08 - Rev.C
A
A
BR24A□□-WM series
Technical Note
●FAST-MODE and STANDARD-MODE
FAST-MODE and STANDARD-MODE are of same actions, and mode is changed. They are distinguished by action speeds.
100kHz action is called STANDARD-MODE, and 400kHz action is called FAST-MODE. This action frequency is the
maximum action frequency, so 100kHz clock may be used in FAST-MODE. At VCC=2.5V～5.5V , 400kHz, namely, action is
made in FASTMODE. (Action is made also in STANDARD-MODE.)
●Sync data input / output timing
SCL
tHD:STA tHD:DAT
SD
(入力)
(input)
SDA
(output)
(出力)
tBUF
○Input read at the rise edge of SCL
○Data output in sync with the fall of SCL
tSU:DAT
tHIGHtR tF
tLOW
tPD tDH
SCL
tSU:STA tSU:STOtHD:STA
SDA
START BIT
STOP BIT
Fig.1-(a) Sync data input / output timing Fig.1-(b) Start-stop bit timing
SCL
SDA
D0
Write data
(n-th address)
ACK
Stop condition
ｔWR
Start condition
SCL
SDA
WP
DATA(1)
D1 D0ACK
tSU：WP
DATA(n)
CK
WR
ｔ
Stop condition
ストップコンディション
ｔHD：
WP
Fig.1-(c) Write cycle timing Fig.1-(d) WP timing at write execution
SCL
DATA(1)
D1 D0 ACK ACK
SDA
WP
○At write execution, in the area from the D0 taken clock rise of the first
DATA(1), to tWR, set WP=“LOW”.
○By setting WP “HIGH” in the area, write can be cancelled.
When it is set WP=“HIGH” during tWR, write is forcibly ended, and data of
address under access is not guaranteed, therefore write it once again.
DATA(n)
tHIGH:WP
Fig.1-(e) WP timing at write cancel
tWR
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© 2009 ROHM Co., Ltd. All rights reserved.
3/17
2009.08 - Rev.C
y
BR24A□□-WM series
●Block diagram
*2
1
A0
*2
A1
2
*2
3
A2
GND
4
1
＊
8bit : BR24A02-WM
High voltage
generating circuit
7bit : BR24A01A-WM
9bit : BR24A04-WM
●Pin assignment and description
Terminal
name
Input /
output
BR24A01A-WM BR24A02-WM BR24A04-WM BR24A08-WM BR24A16-WM BR24A32-WM BR24A64-WM
*1
7bit
11bit
8bit
12bit
13b
9bit
t
10bi
Address
decoder
it
7bit
8bit
*1
9bit
10bi
Control circuit
10bit : BR24A08-WM
11bit : BR24A16-WM
12bit : BR24A32-WM
13bit : BR24A64-WM
1Kbit~64Kbit EEPROM arra
11bit
Slave - word
12bit
it
13b
t
address register
START STOP
Power source
voltage detection
＊
2 A0=N.C. : BR24A04-WM
A0, A1=N.C. : BR24A08-WM
A0, A1= N.C. A2=Don’t Use : BR24A16-WM
Fig.2 Block diagram
A0
1
BR24A01A-WM
A1
2
BR24A02-WM
BR24A04-WM
BR24A08-WM
A2
3
BR24A16-WM
BR24A32-WM
BR24A64-WM
4
GND
ACK
8
Vcc
WP
7
6
SCL
5
SDA
Function
8bit
Data
register
Technical Note
8
Vcc
7
WP
6
SCL
5
SDA
A0 Input Slave address setting Not connected Slave address setting
A1 Input Slave address setting Not connected Slave address setting
A2 Input Slave address setting Not used Slave address setting
GND - Reference voltage of all input / output, 0V
SDA
Input /
output
SCL Input Serial clock input
WP Input Write protect terminal
Vcc - Connect the power source.
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Slave and word address, Serial data input serial data output
4/17
2009.08 - Rev.C
BR24A□□-WM series
●Characteristic data (The following values are Typ. ones.)
6
5
4
3
VIH1,2[V]
2
1
0
0123456
Fig.3 H input voltage VIH1,2 (SCL,SDA,WP) Fig.4 L input voltageVIL1,2 (SCL,SDA,WP)
1.2
1
0.8
0.6
ILI[μA]
0.4
0.2
0
0123456
Fig.6 Input leak current ILI (SCL,WP) Fig.7 Output leak current ILO(SDA)
3.5
3
fSCL=400kHz
DATA=AAh
2.5
2
1.5
ICC1[mA]
1
0.5
0
0123456
Fig.9 Current consumption at WRITE action ICC1
3.5
3
fSCL=100kHz
2.5
DATA=AAh
2
1.5
ICC1[mA]
1
0.5
0
0123456
Fig.12 Current consumption at WRITE action ICC1
10000
SPEC
Vcc[V]
SPEC
Vcc[V]
SPEC
Vcc[V]
(fSCL=400kHz)
SPEC
Vcc[V]
(fSCL=100kHz)
Ta=105℃
Ta=-40℃
Ta=25℃
Ta=105℃
Ta=25℃
Ta=-40℃
[BR24A32/64 series]
Ta=25℃
Ta=105℃
Ta=-40℃
[BR24A32/64 series]
Ta=25℃
Ta=105℃
Ta=-40℃
1000
fSCL[kHz]
100
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
SPEC2
10
1
0123456
5
4
3
2
tHD:STA[μs]
1
0
0123456
Fig.18 Start condition hold time tHD:STA
Vcc[V]
Fig.15 SCL frequency fSCL
SPEC2
Ta=105℃
SPEC1
Ta=25℃
Ta=-40℃
Vcc[V]
6
5
4
3
VIL1,2[V]
2
1
0
0123456
1.2
1
0.8
0.6
ILO[μA]
0.4
0.2
0
0123456
0.6
0.5
0.4
0.3
ICC2[mA]
0.2
0.1
0
0123456
Fig.10 Current consumption at READ action ICC2
0.6
0.5
0.4
0.3
ICC2[mA]
0.2
0.1
0
0123456
Fig.13 Current consumption at READ action ICC2
5
4
3
2
tHIGH [μs]
1
0
0123456
6
5
4
3
2
tSU:STA[μs]
1
0
0123456
SPEC
fSCL=400kHz
DATA=AAh
SPEC
fSCL=100kHz
DATA=AAh
Ta=25℃
SPEC2
Fig.16 Data clock "H" time tHIGH
SPEC2
Ta=-40℃
Ta=25℃
Ta=105℃
Fig.19 Start condition setup time tSU:STA Fig.20 Input data hold time tHD:DAT(HIGH)
Vcc[V]
Vcc[V]
SPEC
Vcc[V]
(fSCL=400kHz)
Ta=105℃
Ta=-40℃
Vcc[V]
(fSCL=100kHz)
Ta=-40℃
Ta=25℃
Ta=105℃
Vcc[V]
SPEC1
Vcc[V]
Ta=105℃
Ta=-40℃
Ta=25℃
SPEC
Ta=105℃
Ta=25℃
Ta=-40℃
Ta=105℃
Ta=25℃
Ta=-40℃
SPEC1
Technical Note
1
0.8
0.6
0.4
VOL1[V]
0.2
0
0123456
Fig.5 L output voltage VOL1-IOL1 (VCC=2.5V)
2.5
2
fSCL=400kHz
DATA=AAh
1.5
1
ICC1[mA]
0.5
0
0123456
Fig.8 Current consumption at WRITE action ICC1
2.5
2
fSCL=100kHz
DATA=AAh
1.5
1
ICC1[mA]
0.5
0
0123456
Fig.11 Current consumption at WRITE action ICC1
2.5
2
1.5
1
ISB[μA]
0.5
0
0123456
Fig.14 Standby current ISB
5
4
3
2
tLOW[μs]
1
0
0123456
Fig.17 Data clock "L" time tLOW
50
0
-50
-100
tHD:DAT(HIGH)[ns]
-150
-200
0123456
IOL1[mA]
[BR24A01/02/04/08/16 series]
Vcc[V]
(fscl=400kHz)
[BR24A01/02/04/08/16 series]
SPEC
Vcc[V]
(fSCL=100kHz)
SPEC
Ta=105℃
Vcc[V]
SPEC2
SPEC1
Ta=105℃
Ta=25℃
Ta=-40℃
Vcc[V]
SPEC1,2
Vcc[V]
SPEC
SPEC
Ta=-40℃
Ta=105℃
Ta=-40℃
Ta=25℃
Ta=105℃
Ta=25℃
Ta=-40℃
Ta=25℃
Ta=105℃
Ta=-40℃
Ta=25℃
Ta=105℃
Ta=-40℃
Ta=25℃
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5/17
2009.08 - Rev.C
BR24A□□-WM series
●Characteristic data (The following values are Typ. ones.)
50
0
-50
-100
tHD:DAT(LOW)[ns]
-150
-200
0123456
4
3
SPEC1,2
Ta=105℃
Ta=25℃
Ta=-40℃
Fig.21 Input data hold time tHD:DAT(LOW) Fig.22 Input data setup time tSU:DAT(HIGH)
Vcc[V]
SPEC2
300
200
100
0
tSU:DAT(HIGH)[ns]
-100
-200
0123456
4
3
SPEC2
SPEC2
2
tPD0[μs]
tWR[ms]
0.6
0.5
0.4
0.3
0.2
tI(SDA H)[μs]
0.1
1.2
0.8
0.6
0.4
tHIGH:WP[μs]
0.2
Ta=105℃
Ta=25℃
Ta=-40℃
1
SPEC2
SPEC1
0
0123456
Fig.24 Output data delay time tPD0 Fig.25 Output data delay time tPD1
6
5
4
3
2
1
0
0123456
Fig.27 Internal write cycle time tWR
Ta=25℃
0
0123456
Fig.30 Noise removal valid time tI(SDA H) Fig.31 Noise removal valid time tI(SDA L) Fig.32 WP setup time tSU:WP
1
0
0123456
Fig.33 WP valid time tHIGH:WP
SPEC1,2
SPEC1,2
SPEC1,2
Vcc[V]
Vcc[V]
Vcc[V]
Vcc[V]
SPEC1
Ta=-40℃
Ta=105℃
Ta=105℃
Ta=25℃
Ta=-40℃
Ta=-40℃
Ta=25℃
Ta=105℃
2
Ta=-40℃
Ta=25℃
tPD1[μs]
Ta=105℃
1
SPEC2
SPEC1
0
0123456
0.6
0.5
0.4
Ta=25℃
SPEC1,2
0123456
Fig.28 Noise rem oval valid time tI(S CL H)
Ta=25℃
SPEC1
0123456
tI(SDA L)[μs]
0.3
0.2
tI(SCL H)[μs]
0.1
0.6
0.5
0.4
0.3
0.2
0.1
0
0
SPEC1
Vcc[V]
SPEC1
Vcc[V]
Ta=105℃
Vcc[V]
Vcc[V]
Ta=-40℃
Ta=-40℃
Ta=105℃
Ta=105℃
Ta=25℃
Ta=-40℃
300
200
100
0
tSU:DAT(LOW)[ns]
-100
-200
0123456
5
4
3
2
tBUF[μs]
1
0
0123456
Fig.26 Bus release time before transfer start tBUF
0.6
0.5
0.4
0.3
0.2
tI(SCL L)[μs]
0.1
0
0123456
0.2
0
-0.2
tSU:WP[μs]
-0.4
-0.6
0123456
SPEC2
SPEC1
Ta=105℃
Ta=25℃
Ta=-40℃
Vcc[V]
Fig.23 Input data setup time tSU:DAT(LOW)
SPEC2
Ta=-40℃
SPEC1
Ta=25℃
Ta=105℃
Vcc[V]
Ta=-40℃
Ta=25℃
Ta=105℃
SPEC1
Vcc[V]
Fig.29 Noise removal valid time tI(SCL L)
SPEC1,2
Ta=25℃
Ta=105℃
Ta=-40℃
Vcc[V]
Technical Note
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6/17
2009.08 - Rev.C
S
BR24A□□-WM series
Technical Note
●I2C BUS communication
○I2C BUS data communication
2
C BUS data communication starts by start condition input, and ends by stop condition input. Data is always 8bit long, and
I
acknowledge is always required after each byte. I2C BUS carries out data transmission with plural devices connected by
2 communication lines of serial data (SDA) and serial clock (SCL).
Among devices, there are “master” that generates clock and control communication start and end, and “slave” that is
controlled by address peculiar to devices. EEPROM becomes “slave”. And the device that outputs data to bus during
data communication is called “transmitter”, and the device that receives data is called “receiver”.
SDA
1-7 1-7
SCL
S P
START R/W ACK
condition condition
89 89 89
1-7
Fig.34 Data transfer timing
ACK STOPACKDATA DATAADDRES
○Start condition (Start bit recognition)
・Before executing each command, start condition (start bit) where SDA goes from 'HIGH' down to 'LOW' when SCL
is 'HIGH' is necessary.
・This IC always detects whether SDA and SCL are in start condition (start bit) or not, therefore, unless this confdition
is satisfied, any command is executed.
○Stop condition (stop bit recongnition)
・Each command can be ended by SDA rising from 'LOW' to 'HIGH' when stop condition (stop bit), namely, SCL is 'HIGH'
○Acknowledge (ACK) signal
・This acknowledge (ACK) signal is a software rule to show whether data transfer has been made normally or not. In
master and slave, the device (μ-COM at slave address input of write command, read command, and this IC at data
output of readcommand) at the transmitter (sending) side releases the bus after output of 8bit data.
・The device (this IC at slave address input of write command, read command, and μ-COM at data output of read
command) at the receiver (receiving) side sets SDA 'LOW' during 9 clock cycles, and outputs acknowledge signal (ACK
signal) showing that it has received the 8bit data.
・This IC, after recognizing start condition and slave address (8bit), outputs acknowledge signal (ACK signal) 'LOW'.
・Each write action outputs acknowledge signal (ACK signal) 'LOW', at receiving 8bit data (word address and write data).
・Each read action outputs 8bit data (read data), and detects acknowledge signal (ACK signal) 'LOW'.
・When acknowledge signal (ACK signal) is detected, and stop condition is not sent from the master (μ-COM) side, this
IC continues data output. When acknowledge signal (ACK signal) is not detected, this IC stops data transfer, and
recognizes stop cindition (stop bit), and ends read action. And this IC gets in status.
○Device addressing
・Output slave address after start condition from master.
・The significant 4 bits of slave address are used for recognizing a device type. The device code of this IC is fixed to '1010'.
・Next slave addresses (A2 A1 A0 --- device address) are for selecting devices, and plural ones can be used on a same
bus according to the number of device addresses.
・The most insignificant bit (R/W --- READ / WRITE) of slave address is used for designating write or read action, and is as
shown below.
Setting R / W to 0 ------- write (setting 0 to word address setting of random read)
Setting R / W to 1 ------- read
Type Slave address
BR24A01A-WM 1 0 1 0 A2 A1 A0 R/W
BR24A02-WM 1 0 1 0 A2 A1 A0 R/W
BR24A04-WM 1 0 1 0 A2 A1 PS R/W
BR24A08-WM 1 0 1 0 A2 P1 P0 R/W
BR24A16-WM 1 0 1 0 P2 P1 P0 R/W
BR24A32-WM 1 0 1 0 A2 A1 A0 R/W
BR24A64-WM 1 0 1 0 A2 A1 A0 R/W
PS, P0～P2 are page select bits.
Note) Up to 4 units BR24A04-WM, up to 2 units of BR24A08-WM, and one unit of BR24A16-WM can be connected.
Device address is set by 'H' and 'L' of each pin of A0, A1, and A2.
Maximum number of
connected buses
―
8
―
8
―
4
―
2
―
1
―
8
―
8
A0
A1
A2
GND
1
BR24A01A-WM
BR24A02-WM
2
BR24A04-WM
BR24A08-WM
3
BR24A16-WM
BR24A32-WM
BR24A64-WM
4
8
7
6
5
Vcc
WP
SCL
SDA
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7/17
2009.08 - Rev.C
A
A
A
A
BR24A□□-WM series
Technical Note
●Write Command
○Write cycle
・Arbitrary data is written to EEPROM. When to write only 1 byte, byte write is normally used, and when to write continuous
data of 2 bytes or more, simultaneous write is possible by page write cycle. The maximum number of write bytes is
specified per device of each capacity. Up to 32 arbitrary bytes can be written. (In the case of BR24A32 / A64-WM)
SDA
LINE
S
T
A
R
T
1 1 0 0
ADDRESS
SLAVE
Note)
W
R
I
T
E
A1 A2
A0
R
A
/
C
W
K
WA
*1
7
WORD
ADDRESS
WA
DATA
D7
0
A
C
K
Fig.35 Byte write cycle (BR24A01A/02/04/08/16-WM)
S
T
O
P
D0
A
C
K
*1 As for WA7, BR24A01A-WM becomes Don’t care.
SDA
LINE
S
T
A
R
T
ADDRESS
W
R
I
T
SLAVE
A1 A2 1 1 0 0
A0 D0
Note)
1st WORD
E
ADDRESS
WA
WA
*
*
*
12
11
R
A
/
C
W
K
*1
A
C
K
Fig.36 Byte write cycle (BR24A32/64-WM)
S
T
A
R
ADDRESS
T
SDA
LINE
0
1
Fig.37 Page write cycle (BR24A01A/02/04/08/16-WM)
S
T
A
R
T
SDA
LINE
1
W
R
I
SLAVE
1A0 A1 A2 D0
0
Note)
SLAVE
ADDRESS
0
1A0 A1 A2
0
Note)
T
E
R
/
W
ADDRESS(n)
* * *
A
C
K
W
R
T
E
R
/
W
1st WORD
WA
WA
12
11
*1
I
WA
7
*1
C
K
ADDRESS(n)
A
C
K
WORD
2nd WORD
ADDRESS(n)
WA
0
C
K
2nd WORD
ADDRESS
WA
0
A
C
K
DAT
WA
D7
0
A
C
K
DATA(n)
D0D7
A
C
K
(n)
DATA(n+15)
D0D7 D0
C
K
DATA
DATA(n+31)
*2
S
T
O
P
A
*1 As for WA12, BR24A32-WM becomes Don’t care.
C
K
S
T
O
P
*1 As for WA7, BR24A01A-WM becomes Don’t care.
A
C
*2 As for BR24A01A/02-WM becomes (n+7).
K
S
T
O
P
*1 As for WA12, BR24A32-WM becomes Don’t care.
A
C
K
Fig.38 Page write cycle (BR24A32/64-WM)
・Data is written to the address designated by word address (n-th address)
・By issuing stop bit after 8bit data input, write to memory cell inside starts.
・When internal write is started, command is not accepted for tWR (5ms at maximum).
・By page write cycle, the following can be written in bulk : Up to 8 bytes ( BR24A01A-WM, BR24A02-WM）
: Up to 16bytes (BR24A04-WM, BR24A08-WM,BR24A16-WM）
: Up to 32bytes (BR24A32-WM, BR24A64-WM
And when data of the maximum bytes or higher is sent, data from the first byte is overwritten.
(Refer to "Internal address increment" of "Notes on page write cycle" in P8/16.)
・As for page write cycle of BR24A01A-WM and BR24A02-WM, after the significant 5 bits (4 significant bits in
BR24A01A-WM) of word address are designated arbitrarily, and as for page write command of BR24A04-WM,
BR24A08-WM, and BR24A16-WM, after page select bit (PS) of slave address is designated arbitrarily, by continuing data
input of 2 bytes or more, the address of insignificant 4 bits (insignificant 3 bit in BR24A01A-WM, and BR24A02-WM) is
incremented internally, and data up to 16 bytes (up to 8 bytes in BR24A01A-WM and BR24A02-WM) can be written.
・As for page write cycle of BR24A32-WM and BR24A64-WM, after the significant 7 bits (in the case of BR24A32-WM) of
word address, or
input of 2 byte or more, the address of insignificant 5 bits is incremented internally, and data up to 32 bytes can be written.
the significant 8 bits (in the case of BR24A64-WM) of word address are designated arbitrarily, by continuing data
Note)
0
1
*1 *2 *3
0
A2
A1
1A0
Fig.39 Difference of slave address of each type
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM and
BR24A16-WM, A0 becomes P0.
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8/17
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
○Notes on write cycle continuous input
S
T
O
P
A
C
K
At STOP (stop bit),
write starts.
S
T
A
R
T
1 100
Next command
tWR(maximum : 5ms)
Command is not accepted for this perio d.
SDA
LINE
S
T
A
R
ADDRESS
T
10 0 1A0 A1 A2
Note)
SLAVE
W
R
I
T
E
WA
R
A
/
C
W
K
WORD
ADDRESS（ｎ）
*1
7
WA
0
A
C
K
Note)
1
0 0
*1 *2 *3
A2
A1
1A0
Fig.42 Difference of each type of slave address
DATA(n)
*2
DATA(n+7)
*3
D0D7 D0
A
C
K
*1 BR24A01A-WM becomes Don’t care.
*2 BR24A04-WM, BR24A08-W, and BR24A16-WM become (n+15).
*3 BR24A32-WM and BR24A64-WM become (n+31).
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and in BR24A16-WM, A0 becomes P0.
○Notes on page write cycle
List of numbers of page write
Number of Pages 8Byte 16Byte 32Byte
Product
number
BR24A01A-WM
BR24A02-WM
BR24A04-WM
BR24A08-WM
BR24A16-WM
BR24A32-WM
BR24A64-WM
The above numbers are maximum bytes for respective types.
Any bytes below these can be written.
In the case BR24A02-WM, 1 page=8bytes, but the page write cycle write time is 5ms at maximum for 8byte bulk write.
It does not stand 5ms at maximum × 8byte=40ms(Max.).
○Internal address increment
Page write mode (in the case of BR24A02-WM)
WA7 ----- WA4 WA3 WA2 WA1 WA0
0 ----- 0 0 0 0 0
0 ----- 0 0 0 0 1
0 ----- 0 0 0 1 0
---------
---------
0 ----- 0 0 1 1 0
06h
0 ----- 0 0 1 1 1
0 ----- 0 0 0 0 0
Increment
---------
Significant bit is fixed.
No digit up
For example, when it is started from address 06h,therefore, increment is made as below,
06h → 07h → 00h → 01h ---, which please note.
*06h･･･06 in hexadecimal, therefore, 00000110 becomes a binary number.
○Write protect (WP) terminal
・Write protect (WP) function
When WP terminal is set VCC (H level), data rewrite of all addresses is prohibited. When it is set GND (L level), data rewrite of
all address is enabled. Be sure to connect this terminal to VCC or GND, or control it to H level or L level. Do not use it open.
At extremely low voltage at power ON / OFF, by setting the WP terminal 'H', mistake write can be prevented.
During tWR, set the WP terminal always to 'L'. If it is set 'H', write is forcibly terminated.
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9/17
2009.08 - Rev.C
A
A
A
N
BR24A□□-WM series
Technical Note
●Read Command
○Read cycle
Data of EEPROM is read. In read cycle, there are random read cycle and current read cycle.
Random read cycle is a command to read data by designating address, and is used generally.
Current read cycle is a command to read data of internal address register without designating address, and is used when
to verify just after write cycle. In both the read cycles, sequential read cycle is available, and the next address data can be
read in succession.
S
T
A
SLAVE
R
SDA
LINE
ADDRESS
T
10 0 1 A0 A1 A2
ote)
Fig.42 Random read cycle (BR24A01A/02/04/08/16-WM)
SDA
LINE
S
T
A
SLAVE
R
ADDRESS
T
10 0 1A0 A1
Note)
Fig.43 Random read cycle (BR24A32/64 -WM)
S
T
A
SLAVE
R
SDA
LINE
ADDRESS
T
10 0 1 A0 A1 A2 D0 D7
Fig.44 Current read cycle
S
T
A
SLAVE
R
SDA
LINE
ADDRESS
T
10 0
Note）
Fig.45 Sequential read cycle (in the case of current read cycle)
A2
Note)
A2
1
A1
W
R
I
T
E
R
/
W
A0
W
R
I
T
E
A
R
C
/
K
W
ADDRESS（ｎ）
*
A
C
K
R
D
R
W
R
E
A
D
A
R
C
/
K
W
ADD RE SS (n)
WA
7
*1
1st WORD
WA
WA
**
12
11
*1
E
A
A
C
/
K
WORD
WA
0
C
K
2nd WORD
ADDRESS（ｎ）
A
C
K
DA TA(n )
DATA(n)
D0 D7 D0D7
A
C
K
S
T
A
SLAVE
R
ADDRESS
T
10 0 1A1A2
WA
S
T
O
P
A
C
K
R
E
A
D
A0 D0
R
C
/
K
W
S
T
A
SLAVE
R
ADDRESS
T
100
1
0
A
C
K
A2
A
C
K
D7
A1
A0
DATA(n+x)
R
E
A
D
R
/
W
DATA(n)
DATA(n)
D7 D0
A
C
K
S
T
O
P
C
K
It is necessary to input 'H' to
the last ACK.
*1 As for WA7, BR24A01A-WM become Don’t care.
S
T
O
P
A
C
K
*1 As for WA12, BR24A32-WM become Don’t care.
It is necessary to input 'H' to
the last ACK.
S
T
O
P
A
C
K
・In random read cycle, data of designated word address can be read.
・When the command just before current read cycle is random read cycle, current read cycle (each including sequential
read cycle), data of incremented last read address (n)-th address, i.e., data of the (n+1)-th address is output.
・When ACK signal 'LOW' after D0 is detected, and stop condition is not sent from master (μ-COM) side, the next address
data can be read in succession.
・Read cycle is ended by stop condition where 'H' is input to ACK signal after D0 and SDA signal is started at SCL signal 'H' .
・When 'H' is not input to ACK signal after D0, sequential read gets in, and the next data is output.
Therefore, read command cycle cannot be ended. When to end read command cycle, be sure input stop condition to
input 'H' to ACK signal after D0, and to start SDA at SCL signal 'H'.
・Sequential read is ended by stop condition where 'H' is input to ACK signal after arbitrary D0 and SDA is started at SCL
signal 'H'.
Note)
1
*1 *2 *3
0 0
1A0
A2
A1
Fig.46 Difference of slave address of each type
*1 In BR24A16-WM, A2 becomes P2.
*2 In BR24A08-WM, BR24A16-WM, A1 becomes P1.
*3 In BR24A04-WM, A0 becomes PS, and in BR24A08-WM
and BR24A16-WM, A0 becomes P0.
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10/17
2009.08 - Rev.C
A
A
A
A
A
A
A
A
BR24A□□-WM series
Technical Note
●Software reset
Software reset is executed when to avoid malfunction after power on, and to reset during command input. Software reset
has several kinds, and 3 kinds of them are shown in the figure below. (Refer to Fig.47(a), Fig.47(b), and Fig.47(c).) In
dummy clock input area, release the SDA bus ('H' by pull up). In dummy clock area, ACK output and read data '0' (both 'L'
level) may be output from EEPROM, therefore, if 'H' is input forcibly, output may conflict and over current may flow, leading
to instantaneous power failure of system power source or influence upon devices.
SCL
SDA
Dummy clock×14
2 13
1
14
Star t×2
Normal command
Normal command
Fig.47-(a) The case of dummy clock +START+START+ command input
SCL
SDA
Fig.47-(b) The case of START +9 dummy clocks +START+ command input
SCL
SDA
Star t
1
Dummy clock×9
1
2
2
3
8
Star t×9
7
Fig.47-(c) START×9+ command input
Star t
9
8
9
※
Start command from START input.
Normal command
Normal command
Normal command
Normal command
●Acknowledge polling
During internal write execution, all input commands are ignored, therefore ACK is not sent back. During internal automatic
write execution after write cycle input, next command (slave address) is sent, and if the first ACK signal sends back 'L', then
it means end of write action, while if it sends back 'H', it means now in writing. By use of acknowledge polling, next
command can be executed without waiting for tWR = 5ms.
When to write continuously, R/W = 0, when to carry out current read cycle after write, slave address R/W = 1 is sent, and if
ACK signal sends back 'L', then execute word address input and data output and so forth.
First write command
…
S
T
A
R
T
Write command
S
T
Slave
A
address
R
T
tWR
S
S
T
A
R
T
Slave
address
T
O
P
Second write command
C
C
K
K
H
H
S
T
A
R
T
Slave
address
During internal write,
ACK = HIGH is sent back.
S
T
A
R
T
Slave
address
C
K
H
C
K
H
tWR
S
Word
C
K
address
L
After completion of internal write,
ACK=LOW is sent back, so input next
word address and data in succession.
C
C
Data
K
K
L
L
S
C
T
T
K
O
O
L
P
P
Fig.48 Case to continuously write by acknowledge polling
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11/1 7
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
●WP valid timing (write cancel)
WP is usually fixed to 'H' or 'L', but when WP is used to cancel write cycle and so forth, pay attention to the following WP
valid timing. During write cycle execution, in cancel valid area, by setting WP='H', write cycle can be cancelled. In both byte
write cycle and page write cycle, the area from the first start condition of command to the rise of clock to taken in D0 of
data(in page write cycle, the first byte data) is cancel invalid area.
WP input in this area becomes Don't care. Set the setup time to rise of D0 taken SCL 100ns or more. The area from the rise
of SCL to take in D0 to the end of internal automatic write (tWR) is cancel valid area. And, when it is set WP='H' during tWR,
write is ended forcibly, data of address under access is not guaranteed, therefore, write it once again. (Refer to Fig.49.) After
execution of forced end by WP, standby status gets in, so there is no need to wait for tWR (5ms at maximum).
・Rise of D0 taken clock
SCL
SCL
・Rise of SDA
SDA
D0
D1
Enlarged view
ACK
SDA
ACK
D0
Enlarged view
SDA
WP
S
T
A
R
T
Slave
address
A
C
K
L
A
Word
C
address
WP cancel invalid area
K
L
D7 D6
D5
D4
D3
D2
A
C
D1 D0
K
L
WP cancel valid area
Data is not written.
Data
A
S
C
T
K
O
L
P
Data not guaranteed
tWR
Write forced end
Fig.49 WP valid timing
●Command cancel by start condition and stop condition
During command input, by continuously inputting start condition and stop condition, command can be cancelled.
(Refer to Fig. 50.)
However, in ACK output area and during data read, SDA bus may output 'L', and in this case, start condition and stop
condition cannot be input, so reset is not available. Therefore, execute software reset. And when command is cancelled by
start, stop condition, during random read cycle, sequential read cycle, or current read cycle, internal setting address is not
determined, therefore, it is not possible to carry out current read cycle in succession. When to carry out read cycle in
succession, carry out random read cycle.
SCL
SDA
1
0 0
1
Start condition Stop condition
Fig.50 Case of cancel by start, stop condition during slave address input
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12/17
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
●I/O peripheral circuit
○Pull up resistance of SDA terminal
SDA is NMOS open drain, so requires pull up resistance. As for this resistance value (R
this resistance value from microcontroller VIL, IL, and VOL-I
characteristics of this IC. If RPU is large, action frequency is
OL
), select an appropriate value to
PU
limited. The smaller the RPU, the larger the consumption current at action.
○Maximum value of R
PU
The maximum value of RPU is determined by the following factors.
(1)SDA rise time to be determined by the capacitance (CBUS) of bus line of RPU and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential
A to be determined by input leak total (IL) of device connected to bus at output of 'H' to SDA
○
bus and RPU should sufficiently secure the input 'H' level (VIH) of microcontroller and EEPROM including recommended
noise margin 0.2VCC.
○Minimum value of R
The minimum value of RPU is determined by the following factors.
(1)When IC outputs LOW, it should be satisfied that V
(2)V
Vcc - ILR
Ex. ) When VCC =3V, IL=10μA, VIH=0.7 VCC,
from (2)
=0.4V should secure the input 'L' level (VIL) of microcontroller and EEPROM including recommended noise
OLMAX
- 0.2Vcc ≧ V
PU
∴ R
PU
R
PU
≦ 300 [kΩ]
PU
V
CC-VOL
R
PU
IH
0.8Vcc - V
＝
0.8×3- 0.7×3
≦
10×10
≦ I
OL
マイコン
OL
IOL
Microcontroller
=3mA.
OLMAX
RPU
A
IL
Bus line
バスライン容量
capacity
CBUS
CBUS
Fig.51 I/O circuit diagram
IL
IH
I
L
-6
=0.4V and I
OLMAX
VC-V
∴ R
≦
PU
BR24AXX
SDA terminal
margin 0.1VCC.
OLMAX ≦ VIL-0.1 VCC
V
Ex. ) When VCC =3V, VOL=0.4V, IOL=3mA, microcontroller, EEPROM VIL=0.3VCC
from (1)
R
PU
And
VOL = 0.4 [V]
V
IL
3－0.4
≧
3×10
≧ 867 [Ω]
= 0.3×3
= 0.9 [V]
-3
Therefore, the condition (2) is satisfied.
○Pull up resistance of SCL terminal
When SCL control is made at CMOS output port, there is no need, but in the case there is timing where SCL becomes
'Hi-Z', add a pull up resistance. As for the pull up resistance, one of several kΩ ~ several ten kΩ is recommended in
consideration of drive performance of output port of microcontroller.
●A0, A1, A2, WP process
○Process of device address terminals (A0,A1,A2)
Check whether the set device address coincides with device address input sent from the master side or not, and select
one among plural devices connected to a same bus. Connect this terminal to pull up or pull down, or VCC or GND. And,
pins (N, C, PIN) not used as device address may be set to any of 'H' , 'L', and 'Hi-Z'.
Types with N.C.PIN BR24A16/F/FJ -WM A0, A1, A2
BR24A08/F/FJ-WM A0, A1
BR24A04/F/FJ -WM A0
○Process of WP terminal
WP terminal is the terminal that prohibits and permits write in hardware manner. In 'H' status, only READ is available and
WRITE of all address is prohibited. In the case of 'L', both are available. In the case of use it as an ROM, it is
recommended to connect it to pull up or VCC. In the case to use both READ and WRITE, control WP terminal or connect it
to pull down or GND.
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13/17
2009.08 - Rev.C
S
A
BR24A□□-WM series
Technical Note
●Cautions on microcontroller connection
○Rs
2
C BUS, it is recommended that SDA port is of open drain input/output. However, when to use CMOS input / output of
In I
tri state to SDA port, insert a series resistance Rs between the pull up resistance Rpu and the SDA terminal of EEPROM.
This is controls over current that occurs when PMOS of the microcontroller and NMOS of EEPROM are turned ON
simultaneously. Rs also plays the role of protection of SDA terminal against surge. Therefore, even when SDA port is
open drain input/output, Rs can be used.
EEPROM
RPU
R
S
SCL
SDA
'H' output of microcontroller
'L' output of EEPROM
Microcontroller
Fig.52 I/O circuit diagram
Over current flows to SDA line by 'H'
output of microcontroller and 'L'
output of EEPROM.
Fig.53 Input / output collision timing
○Maximum value of Rs
The maximum value of Rs is determined by the following relations.
(1)SDA rise time to be determined by the capacity (CBUS) of bus line of Rpu and SDA should be tR or below.
And AC timing should be satisfied even when SDA rise time is late.
(2)The bus electric potential
should sufficiently secure the input 'L' level (V
A to be determined by Rpu and Rs the moment when EEPROM outputs 'L' to SDA bus
○
) of microcontroller including recommended noise margin 0.1VCC.
IL
VIL
Microcontroller
VCC
RPU
Bus line
capacity CBUS
R
IOL
(V
S
VOL
CC
∴
When VCC=3V, VIL=0.3V
Example
EEPROM
）
from(2),
－
R
PU+RS
R
S
R
S
)×R
V
OL
V
－
IL
≦
1.1V
0.3×3－0.4－0.1×3
≦
1.1×3－0.3×3
+VOL+0.1V
V
0.1V
－
OL
CC
－
V
CC,
CC
IL
V
≦
V
CC
IL
×
R
PU
=0.4V, RPU=20kΩ,
OL
×
20×10
Fig.54 I/O circuit diagram
≦
1.67［kΩ
］
○Minimum value of Rs
The minimum value of Rs is determined by over current at bus collision. When over current flows, noises in power source
line, and instantaneous power failure of power source may occur. When allowable over current is defined as I, the following
relation must be satisfied. Determine the allowable current in consideration of impedance of power source line in set and so
forth. Set the over current to EEPROM 10mA or below.
R
PU
R
'L' output
S
'H' output
Over currentⅠ
Microcontroller
EEPROM
Fig.55 I/O circuit diagram
V
CC
≦
R
S
R
S
∴
≧
Exam ple）When V
I
V
CC
I
=3V, I=10mA
CC
R
S
≧
≧
3
10×10
300［Ω
-3
］
3
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14/17
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
●I2C BUS input / output circuit
○Input (A0,A2,SCL)
Fig.56 Input pin circuit diagram
○Input / output (SDA)
Fig.57 Input / output pin circuit diagram
○Input (A1, WP)
Fig.58 Input pin circuit diagram
●Notes on power ON
At power on, in IC internal circuit and set, VCC rises through unstable low voltage area, and IC inside is not completely reset,
and malfunction may occur. To prevent this, functions of POR circuit and LVCC circuit are equipped. To assure the action,
observe the following conditions at power on.
1. Set SDA = 'H' and SCL ='L' or 'H'
, t
2. Start power source so as to satisfy the recommended conditions of t
, and Vbot for operating POR circuit.
R
OFF
t
VCC
t
OFF
0
Fig.59 Rise waveform diagram
R
Vbot
Recommended conditions of tR, t
t
R
t
OFF
10ms or below 10ms or longer 0.3V or below
OFF
,Vbot
Vbot
100ms or below 10ms or longer 0.2V or below
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15/17
2009.08 - Rev.C
A
BR24A□□-WM series
Technical Note
3. Set SDA and SCL so as not to become 'Hi-Z'.
When the above conditions 1 and 2 cannot be observed, take the following countermeasures.
a) In the case when the above condition 1 cannot be observed. When SDA becomes 'L' at power on .
→Control SCL and SDA as shown below, to make SCL and SDA, 'H' and 'H'.
V
CC
SCL
t
LOW
SDA
fter Vcc becomes stable
t
t
SU:DAT
DH
After Vcc becomes stable
t
SU:DAT
Fig.60 When SCL= 'H' and SDA= 'L'
Fig.61 When SCL='L' and SDA='L'
b) In the case when the above condition 2 cannot be observed.
→After power source becomes stable, execute software reset(P11).
c) In the case when the above conditions 1 and 2 cannot be observed.
→Carry out a), and then carry out b).
●Low voltage malfunction prevention function
LVCC circuit prevents data rewrite action at low power, and prevents wrong write. At LVCC voltage (Typ. =1.2V) or below, it
prevent data rewrite.
●VCC noise countermeasures
○Bypass capacitor
When noise or surge gets in the power source line, malfunction may occur, therefore, for removing these, it is
recommended to attach a by pass capacitor (0.1μF) between IC VCC and GND. At that moment, attach it as close to IC as possible.
And, it is also recommended to attach a bypass capacitor between board VCC and GND.
●Note of use
(1) Described numeric values and data are design representative values, and the values are not guaranteed.
(2) We believe that application circuit examples are recommendable, however, in actual use, confirm characteristics further
sufficiently. In the case of use by changing the fixed number of external parts, make your decision with sufficient margin
in consideration of static characteristics and transition characteristics and fluctuations of external parts and our LSI.
(3) Absolute maximum ratings
If the absolute maximum ratings such as impressed voltage and action temperature range and so forth are exceeded,
LSI may be destructed. Do not impress voltage and temperature exceeding the absolute maximum ratings. In the case
of fear exceeding the absolute maximum ratings, take physical safety countermeasures such as fuses, and see to it that
conditions exceeding the absolute maximum ratings should not be impressed to LSI.
(4)GND electric potential
Set the voltage of GND terminal lowest at any action condition. Make sure that each terminal voltage is lower than that of
GND terminal.
(5)Terminal design
In consideration of permissible loss in actual use condition, carry out heat design with sufficient margin.
(6)Terminal to terminal shortcircuit and wrong packaging
When to package LSI onto a board, pay sufficient attention to LSI direction and displacement. Wrong packaging may
destruct LSI. And in the case of shortcircuit between LSI terminals and terminals and power source, terminal and GND
owing to foreign matter, LSI may be destructed.
(7) Use in a strong electromagnetic field may cause malfunction, therefore, evaluate design sufficiently.
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© 2009 ROHM Co., Ltd. All rights reserved.
16/17
2009.08 - Rev.C
BR24A□□-WM series
Technical Note
●Ordering part number
B R 2 4 A 0 1 F - W M E 2
Part No. BUS type Operating Capacity Package Double cell Packaging and forming specification
24 :I2C temperature 01= 1K 02= 2K F : SOP8 E2: Embossed tape and reel
A:-40℃～ 04= 4K 08= 8K FJ : SOP-J8 TR: Embossed tape and reel
+105℃ 16=16K 32=32K FVM : MSOP8
64=64K
●Package specifications
SOP8
6.2±0.3
SOP-J8
MSOP8
0.9MAX
(MAX 5.35 include BURR)
4.4±0.2
0.595
1.5±0.1
0.11
1.27
4.9±0.2
(MAX 5.25 include BURR)
6.0±0.3
3.9±0.2
0.545
1.375±0.1
4.0±0.2
0.75±0.05
1
0.175
2.9±0.1
(MAX 3.25 include BURR)
8
2.8±0.1
1
2
0.475
0.65
0.08±0.05
5.0±0.2
7
234
1.27
6
57
3
4
6
438251
0.42±0.1
5678
0.1
1PIN MARK
+0.05
0.22
–0.04
0.08 S
S
0.42±0.1
S
+
6
°
4
°
−4°
0.3MIN
+0.1
0.17
-
0.05
S
(Unit : mm)
+
6°
4°
−4°
0.45MIN
0.2±0.1
(Unit : mm)
+
6°
4°
−4°
0.6±0.2
0.29±0.15
+0.05
0.145
–0.03
S
(Unit : mm)
<Tape and Reel information>
Quantity
Direction
0.9±0.15
of feed
<Tape and Reel information>
Quantity
Direction
of feed
<Tape and Reel information>
Quantity
Direction
of feed
Embossed carrier tapeTape
2500pcs
E2
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
Embossed carrier tapeTape
2500pcs
E2
The direction is the 1pin of product is at the upper left when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
Embossed carrier tapeTape
3000pcs
TR
The direction is the 1pin of product is at the upper right when you hold
()
reel on the left hand and you pull out the tape on the right hand
Reel
1pin
Order quantity needs to be multiple of the minimum quantity.
∗
1pin
Order quantity needs to be multiple of the minimum quantity.
∗
1pin
Order quantity needs to be multiple of the minimum quantity.
∗
Direction of feed
Direction of feed
Direction of feed
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© 2009 ROHM Co., Ltd. All rights reserved.
17/17
2009.08 - Rev.C
Notes
No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.
The content specied herein is subject to change for improvement without notice.
The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.
The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other par ties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.
Notice
The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, communication devices, electronic appliances and amusement devices).
The Products specied in this document are not designed to be radiation tolerant.
While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.
Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.
The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.
If you intend to export or ship overseas any Product or technology specied herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.
Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.
ROHM Customer Support System
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R0039
A
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