ROHM BH3866AS Datasheet

1
Video ICs
Dual-line serial control sound processor IC
BH3866AS
The BH3866AS is a signal processing IC developed for the control of volume and tone quality in TV equipment. Since dual-line serial control (I
2
using signals such as those from a microcomputer or similar device.
Applications
DVDs, personal computers, high-vision TVs, karaoke sets, digital broadcasts, CATVs, and other TV equipment
Features
1) 3-channel volume and sound quality control (for stereo and center speakers).
2) Absorption of volume deviation between input sources and improved S / N ratio, for better sound quality, using an AGC circuit.
3) Control through I
2
C BUS serial control.
4) Internal pseudo-stereo circuit provides phase-shift matrix surround effect.
Recommended operating conditions (Ta = 25°C)
Absolute maximum ratings (Ta = 25°C)
Parameter
Symbol
Min. Typ. Max. Unit
Power supply voltage
V
CC
7.0 9.5 V
Parameter Symbol Limits Unit
Power supply voltage V
CC 10.0 V
Power dissipation 1250
mW Operating temperature Topr °C Storage temperature Tstg °C
Pd
– 25 ~ + 75
– 55 ~ + 125
Reduced by 12.5mW for each increase in Ta of 1°C over 25°C.
2
Video ICs BH3866AS
Pin descriptions
Pin No. Pin name Function
1
R
IN
Rch input
Pin No. Pin name Function
17
DAC
Expansion DAC (L / H)
2
GND
Ground
18
SCV
Vol Cch shock sound integration
3
AGCADJ
AGC 0dB adjustment
19
C
OUT
Cch output
4
LS1
AGC level sensor 1
20
L
OUT
Lch output
5
LS2
AGC level sensor 2
21
CB
Cch Bass fc setting
6
S
OUT
Sch output pin and LPF
22
CT
Cch Treble fc setting
7
PS
Phase shift pin (internal resistance: 18k)
23
LB
Lch Bass fc setting
8
Vref
1 / 2 V
CC
24
LT
Lch Treble fc setting
9
STB
Bass shock sound integration
25
STT
Treble shock sound integration
10
RT
Rch Treble fc setting
26
BGAIN
Bass Mix Gain adjustment
11
RB
Rch Bass fc setting
27
MS
IN
Mono Sur input
12
R
OUT
Rch output
28
B
IN
Bass detection LPF operating amplifier input
13
SRV
Vol Rch shock sound integration
29
ADD
L + R added output after AGC
14
SLV
Vol Lch shock sound integration
30
C
IN
Cch input
15
SCL
I
2
C communications clock
31
V
CC
Power supply, 9V
16
SDA
I
2
C communications data
32
L
IN
Lch input
Block diagram
32
1
17
16
LINRIN31VCCGND30CINAGCADJ29ADDLS128BINLS227MSINSOUT26BGAINPS25STTVref24LTSTB23LBRT22CTRB21CBROUT20LOUTSRV19COUTSLV
18
23456789101112131415
SCVSCL
DACSDA
+
+
+
+
+
+
+
+
+
+
VCA
CIN
AGC
MIX OFF
MIX ON
BASS
OFF
Surr effect
ON
OFF
ON
OFF
ON
OFF
ON
SON
OFF
ON
SSTE
LOOP
L + R
CSEL
SMON
A G C
L + R
PHASE
SHIFT
L + S
10k
10k
10k
10k
50k
50k
10k
50k
50k
50k
50k
50k
10k
10k
10k
VCA
R - S
L - R
LFP
AMP
+
VCC
VCC
1 2
V
CC
I2C BUS
SCL SDA
interface
IncrementIncrement
Volume VolumeVolume
Volume Volume Volume
Tone
(bass / treble)
Tone
(bass / treble)
Tone
(bass / treble)
3
Video ICs BH3866AS
Input / output circuits
Pin No.
Input pins.
30 4.5V 50k
IC
IN
32 LIN
1RIN
Pin name I / OZin
Pin voltage
Equivalent circuit Function
AGC 0dB adjustment pin. This pin is connected to the base of PNP. The current output from this pin is 1µA (Typ.) Max.
3—IAGCADJ
Output pins.
19 4.5V OC
OUT
20 LOUT
12 ROUT
Time constant pin on the side that suppresses the AGC signal level.
4—LS1
VCC
GND
50k
1 2
V
CC
VCC
GND
200
200
10k
VCC
GND
VCC
GND
200
430
2k
4
Video ICs BH3866AS
Pin No.
5—LS2
Pin name I / OZin
Pin voltage
Equivalent circuit Function
7PS
Serves as both the output pin for the surround and pseudo­stereo effects, and the LPF pin.
For the phase-shifter filter for the surround and pseudo­stereo effects.
6 4.5V 10k OS
OUT
1 / 2 VCC. This voltage serves as the power supply for the signal system.
Time constant pin on the side that amplifies the AGC signal level.
8 4.5V Vref
——
VCC
GND
200
20k
2k
VCC
GND
200
200
10k
VCC
GND
10k 18k
10k
18k
50k
50k
VCC
GND
5
Video ICs BH3866AS
Pin No.
Pin name I / OZin
Pin voltage
Equivalent circuit Function
Treble filter pins for the left, right, and center channels.
Integration pins that prevent shock sound when switching the bass and treble levels.
25
——
30k
STT
9 STB
22 4.5V 30kCT
24 LT
10 RT
Bass filter pins for the left, right, and center channels.
21 4.5V 30kCB
23 LB
11 RB
Integration pins that prevent shock sound when switching the volume levels on the left, right, and center channels.
14 30kSLV
18 SCV
13 SRV
VCC
GND
30k
DAC
VCC
GND
30k
1 2
V
CC
VCC
GND
30k
1 2
V
CC
VCC
GND
30k
DAC
6
Video ICs BH3866AS
VCC
GND
Pin No.
SCL pin for the I
2
C BUS.
This is the clock pin.
15 ISCL
Pin name I / OZin
Pin voltage
Equivalent circuit Function
50k
1 2
V
CC
17 0 / 5 ODAC
VCC
GND
200
100k
25.6k
74.6k
16
——
ISDA
Gain adjustment pin used to mix the bass on the left and right channels.
26 4.5VBGAIN
VCC
GND
control logic
SDA pin for the I2C BUS. The Acknowledge signal is output from this pin. This is the data pin.
0V and 5V output pin that enables control with the I
2
C BUS.
VCC
GND
B
IN
10k
7
Video ICs BH3866AS
Pin No.
Surround input section for monaural signals in the surround section.
Bass signal input to the left and right channels.
27 4.5V 50k IMS
IN
Pin name I / OZin
Pin voltage
Equivalent circuit Function
50k
1 2
V
CC
29 4.5V OADD
28 4.5V 50k IB
IN
Power supply pin.
Ground pin.
31 9VV
CC
20VGND
Incremented output from the left and right channels following AGC.
VCC
GND
BGAIN
50k
1 2
V
CC
10k
1 2
V
CC
VCC
GND
VCC
GND
200
200
10k
——
——
8
Video ICs BH3866AS
Electrical characteristics (unless otherwise noted, Ta = 25°C, VCC = 9V, f = 1kHz, Rg = 600, RL = 10kΩ)
Parameter
Symbol Conditions
IQQuiescent circuit current VIN = 0Vrms
VOMRMax. output voltage, Rch Max. output voltage, Lch Max. output voltage, Cch
VOML
Min.
2.1
2.1
Typ.
35
2.5
2.5
Max.
65 — —
Unit
mA Vrms Vrms
f
INR = 1kHz, VIN = 1Vrms, RINR =
THD = 1%( )
( / V
IN)
( / V
IN)
( / V
IN)
GVRVoltage gain, Rch Voltage gain, Lch Voltage gain, Cch
– 1.5 0 1.5 dB V
IN = 1Vrms, GVR = 20log
GVL – 1.5 0 1.5 dB VIN = 1Vrms, GVL = 20log
GVC – 1.5 0 1.5 dB VIN = 1Vrms, GVC = 20log
VOMC 2.1 2.5 Vrms THD = 1%( )
THDR
Total harmonic distortion, Rch Total harmonic distortion, Lch Total harmonic distortion, Cch
THDL
——0.01
0.01
0.1
0.1%%
VIN = 1Vrms V
IN = 1Vrms
THDC 0.1 0.3 % VIN = 1Vrms
VNOROutput noise voltage, Rch Output noise voltage, Lch Output noise voltage, Cch
VNOL
— —35357070
µVrms µVrms
Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO
VNOC —3570µVrms Rg = 0Ω, DIN AUDIO
VMNORResidual noise voltage, Rch Residual noise voltage, Lch Residual noise voltage, Cch
VMNOL
— —
331010µVrms
µVrms
Rg = 0, DIN AUDIO Rg = 0, DIN AUDIO
VMNOC —310µVrms Rg = 0Ω, DIN AUDIO
(
R / L)
50k ×
(1 – )
CTR-LCrosstalk, RchLch Crosstalk, RchCch Crosstalk, LchRch Crosstalk, LchCch Crosstalk, CchRch Crosstalk, CchLch
Input impedance, Rch
Input impedance, Lch
Input impedance, Cch
70 78 dB V
IN = 1Vrms, CTR-L = 20log
CTR-C 70 78 dB VIN = 1Vrms, CTR-C = 20log
CTL-R 70 78 dB VIN = 1Vrms, CTL-R = 20log
CTL-C 66 71 dB VIN = 1Vrms, CTL-C = 20log
CTC-R 70 78 dB VIN = 1Vrms, CTC-R = 20log
CTC-L 70 78 dB
R
INR 35 50 65 k
f
INL = 1kHz, VIN = 1Vrms, RINR =
RINL 35 50 65 k
f
INC = 1kHz, VIN = 1Vrms, RINR =
fOUTR = 1kHz, ROUTR =
1k ×
1 –
1 –
1 –
Output impedance, Rch
Output impedance, Lch
Output impedance, Cch
ROUTR —50
f
RR = 100Hz,
V
RR = 100mVrms,
VRR
Ripple rejection, Rch
Ripple rejection, Lch
Ripple rejection, Cch
RRR 40 53 dB
f
OUTL = 1kHz, ROUTL =
1k ×
ROUTL —50
f
OUTC = 1kHz, ROUTC =
1k ×
ROUTC
—50
RINC 35 50 65 k
V
IN = 1Vrms, CTC-L = 20log
RR
R = 20log
VIN
Muting level, Rch
Muting level, Lch
Muting level, Cch
VMUTER 80 90 dB
V
IN = 1Vrms, VMUTER = 20log
VIN
VMUTEL 80 90 dB
V
IN = 1Vrms, VMUTEL = 20log
f
RR = 100Hz,
V
RR = 100mVrms,
VRR
RRL 40 53 dB
RR
R = 20log
VIN
VMUTEC 80 90 dB
V
IN = 1Vrms, VMUTEC = 20log
f
RR = 100Hz,
V
RR = 100mVrms,
VRR
RRC 40 53 dB
RR
R = 20log
THD = 1%( )
(
R / C)
(
L / R)
( L / C) (
C / R)
(
C / L)
50k ×
(1 – )
50k ×
(1 – )
C
C
C
B
B
B
BB
BB
BB
BB
BB
BB
A
A
A
A
A
A
D D D D
D D
B
B
B
B
B
B
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