The BHŜŜFB1W, BHŜŜLB1W and BHŜŜMA3W series are low dropout CMOS regulators with 150 mA and 300 mA
output that have
The BHŜŜFB1W series combines 40µA low current consumption and a 70 dB high ripple rejection ratio by utilizing output
level CMOS technology. The components can be easily mounted into the small standard SSOP5 and the ultra-small
HVSOF5/HVSOF6 packages.
Features
1) High accuracy output voltage: ±1%
2) High ripple rejection ratio: 70 dB (BHŜŜFB1WHFV/WG, BHŜŜLB1WHFV/WG)
3) Low dropout voltage: 60 mV (when current is 100 mA) (BHŜŜMA3WHFV)
4) Stable with ceramic output capacitors
5) Low Bias current : 40µA (I
6) Output voltage ON/OFF control
7) Built-in over-current protection and thermal shutdown circuits
8) Ultra-small power package: HVSOF5 (BHŜŜFB1WHFV, BHŜŜLB1WHFV)
9) Ultra-small power package: HVSOF6 (BHŜŜMA3WHFV)
Applications
Battery-driven portable devices and etc.
Line up
150mA BHŜŜFB1W and BHŜŜLB1W Series
Part Number
BHŜŜFB1WG
BHŜŜFB1WHFV
BHŜŜLB1WG
BHŜŜLB1WHFV
Operating temperature range
Storage temperature range
Topr
Tstg
40
-
55
Recommended operating range
ParameterMin.Max.UnitTyp.Symbol
Power supply voltage
VIN
BHMA3W
Output current
BHFB1W
IOUT
BHLB1W
Recommended operating conditions
ParameterMin.Max.UnitTyp.Symbol
Input capacitor
Output capacitor
Noise decrease capacitor
CIN0.1
Co
Cn
1.0
-
0.010.22
BHĄĄMA3WHFV series
Unit
+
6.5
+
~
85
+
~
125
2.55.5
-
--
--
--
-
-
-
-
V
mW
C
C
300
150mA
150mA
μF
μF
μF
Technical Note
V
mA
Conditions
Ceramic capacitor recommended
Ceramic capacitor recommended
Ceramic capacitor recommended
BHFB1WHFV/WG , BHLB1WHFV/WG
ParameterSymbolMin.Typ.Max.UnitConditions
Output voltage
Circuit current
Circuit current(STBY)
Ripple rejection ratio
Load response 1
Load response 2
Dropout voltage
Line regulation
Load regulation
Load regulation
Output voltage ON/OFF control
(High: ON, Low: OFF)
NO CONNECT
Voltage output
Output voltage ON/OFF control
(High: ON, Low: OFF)
Ground
Power supply input
Voltage output
NO CONNECT
Terminal No. Terminal Name
Function
Power supply input
Voltage output
Voltage output
Noise reducing capacitor
ground terminal
Ground
Output voltage ON/OFF control
(High: ON, Low: OFF)
Power dissipation Pd
1.
Power dissipation
Power dissipation calculation include estimates of power dissipation characteristics and internal IC power consumption
and should be treated as guidelines. In the event that the IC is used in an environment where this power dissipation is
exceeded, the attendant rise in the junction temperature will trigger the thermal shutdown circuit, reducing the current
capacity and otherwise degrading the IC's design performance. Allow for sufficient margins so that this power dissipation
is not exceeded during IC operation.
Calculating the maximum internal IC power consumption (P
MAX)
2. Power dissipation characteristics (Pd)
Board: 70 mm X 70 mm X 1.6 mm
Material: Glass epoxy PCB
Board: 70 mm X 70 mm X 1.6 mm
Material: Glass epoxy PCB
°
Fig. 28: SSOP5
Power Dissipation Reduction (Example)
Power Dissipation/
2010.07 -
Rev. C
BH
□□
BH □□LB1WG series, BH□□LB1WHFV series,
FB1WG series, BH□□FB1WHFV series,
BH □□MA3WHFV series
Technical Note
Input capacitor
It is recommended to insert bypass capacitors between input and GND pins, positioning them as close to the pins as
possible. These capacitors will be used when the power supply impedance increases or when long wiring routes are used, so
they should be checked once the IC has been mounted.
Ceramic capacitors generally have temperature and DC bias characteristics. When selecting ceramic capacitors, use X5R or
X7R or better models that offer good temperature and DC bias characteristics and high torelant voltages.
To prevent oscillation at the output, it is recommended that the IC be operated at the stable region show in below Fig. It
operates at the capacitance of more than 1.0μF. As capacitance is larger, stability becomes more stable and characteristic of
output load fluctuation is also improved.
BHŜŜLB1WHFV/WG
Cout=1.0μF
100
10
1
ESR(Ω)
0.1
0.01
050100150
Fig. 32 BHŜŜLB1WHFV/WG
Stable operating region characteristics (Example)
Ta=+25°C
Stable regionStable region
Output current IOUT(mA)
BHŜŜFB1WHFV/WG
Cout=2.2μF
100
10
1
ESR(Ω)
0.1
0.01
050100150
Fig. 33 BHŜŜFB1WHFV/WG
Stable operating region characteristics (Example)
Ta=+25°C
Output current IOUT(mA)
BHŜŜMA3WHFV
Cout=1.0μFCin=1.0μF
100
10
1
ESR(Ω)
0.1
0.01
0100200300
Fig. 34 BHŜŜMA3WHFV
Stable operating region characteristics (Example)
Stable region
Output current IOUT(mA)
Ta=+25°C
Other precautions
• Over current protection circuit
The IC incorporates a built-in over current protection circuit that operates according to the output current capacity. This circuit
serves to protect the IC from damage when the load is shorted. The protection circuits use fold-back type current limiting and
are designed to limit current flow by not latching up in the event of a large and instantaneous current flow originating from a
large capacitor or other component. These protection circuits are effective in preventing damage due to sudden and
unexpected accidents. Howeve r, the IC should not be used in applications characterized by the continuous operation or
transitioning of the protection circuits.
• Thermal shutdown circuit
This system has a built-in thermal shutdown circuit for the purpose of protecting the IC from thermal damage. As shown
above, this must be used within the range of power dissipation, but if the power dissipation happens to be continuously
exceeded, the chip temperature increases, causing the thermal shutdown circuit to operate. When the thermal shutdown
circuit operates, the operation of the circuit is suspended. The circuit resumes operation immediately after the chip
temperature decreases, so the output repeats the ON and OFF states. There are cases in which the IC is destroyed due to
thermal runaway when it is left in the overloaded state. Be sure to avoid leaving the IC in the overloaded state.
• Actions in strong magnetic fields
Use caution when using the IC in the presence of a strong magnetic field as such environments may occasionally cause the chip
to malfunction.
• Back current
In applications where the IC may be exposed to back current flow, it is recommended to create a route t dissipate this current
by inserting a bypass diode between the V
IN and VOUT pins.
• GND potential
Ensure a minimum GND pin potential in all operating conditions.
In addition, ensure that no pins other than the GND pin carry a voltage less than or equal to the GND pin, including during
actual transient phenomena.
Noise terminal (BHŜŜMA3WHFV)
The terminal is directly connected to inward normal voltage source. Because this has low current ability, load exceeding
100nA will cause some instability at the output. For such reasons, we urge you to use ceramic capacitors which have less
leak current. When choosing noise the current reduction capacitor, there is a trade-off between boot-up time and stability. A
bigger capacitor value will result in lesser oscillation but longer boot-up time for VOUT.
100
10
1
0.1
VOUT startup time t (msec)
0.01
100P1000P0.01μ0.1μ
noise-filtering capacitor capacitance Cn (F)
Fig. 35: VOUT startup time vs. noise-filtering capacitor capacitance characteristics (Example)
Regarding input pin of the IC
This monolithic IC contains P
+ isolation and P substrate layers between adjacent
elements in order to keep them isolated. P/N junctions are formed at the intersection of
these P layers with the N layers of other elements to create a variety of parasitic elements.
For example , when a resistor and transistor are connected to pins as sho wn in Fig.37
The P/N junction functions as a parasitic diode when GND > (Pin A) for the resistor or
GND > (Pin B) for the transistor (NPN).
Similarly, when GND > (Pin B) for the transistor (NPN), the parasitic diode described
above combines with the N lay er of other adjacent elements to oper ate as a par asitic
NPN transistor.
The formation of parasitic elements as a result of the relationships of the potentials of
different pins is an inevitable result of the IC's architecture. The operation of parasitic
elements can cause interference with circuit operation as well as IC malfunction and
damage. For these reasons, it is necessary to use caution so that the IC is not used in a
way that will trigger the operation of parasitic elements, such as by the application of
voltage lower than the GND (P substrate) voltage to input pins.
(When the reel is held with the left hand and the tape is drawn out with the right hand,
the No. 1 pin of the product faces the upper right direction.)
Reel
No. 1 pin
* Please make orders in multiples of the package quantity.
Pulling side
(Package Specification) HVSOF6
Package Form
Package Quantity
Package
Orientation
Embossed taping
3000pcs
TR
(When the reel is held with the left hand and the tape is drawn out with the right hand,
the No. 1 pin of the product faces the upper right direction.)
* Please make orders in multiples of the package quantity.
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The Products specied in this document are intended to be used with general-use electronic
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