ROHM BH1721FVC Technical data

Ambient Light Sensor IC Series

Digital 16bit Serial Output Type Ambient Light Sensor IC

BH1721FVC

●Descriptions

BH1721FVC is an digital Ambient Light Sensor IC for I light data for adjusting LCD and Keypad backlight power of Mobile phone. It is possible to detect wide range at High resolution. ( 1 - 65528 lx ).

●Features

●Applications

●Absolute Maximum Ratings

2

1) I

2) Spectral responsibility is approximately human eye response

3) Illuminance to Digital Converter

4) Wide range and High resolution. (1 – 65528 lx )

5) Low Current by power down function

6) 50Hz / 60Hz Light noise reject-function

7) 1.8V Logic input interface

8) No need any external parts

9) Light source dependency is little. (ex. Incandescent Lamp. Fluorescent Lamp. Halogen Lamp. White LED. Sun Light)

10) Small measurement variation (+/- 15%)

11) Compact surface mount package 1.6 x 1.6 x 0.55 mm

Mobile phone, LCD TV, NOTE PC, Portable game machine, Digital camera, Digital video camera, PDA, LCD display

C bus Interface ( f / s Mode Support, Slave Address : "0100011" )

2

C bus interface. This IC is the most suitable to obtain the ambient

No.11046EBT10

Parameter Symbol Ratings Units

Supply Voltage Vmax 4.5 V

Operating Temperature Topr -40～85 ℃

Storage Temperature Tstg -40～100 ℃

SDA Sink Current Imax 7 mA

Power Dissipation Pd 165※ mW

※70mm × 70mm × 1.6mm glass epoxy board. Derating in done at 2.2mW/℃ for operating above Ta=25℃.

●Operating Conditions

Parameter Symbol

VCC Voltage Vcc 2.4 3.0 3.6 V

I2C Reference Voltage VDVI 1.65 - VCC V

Min. Typ. Max.

Ratings

Units

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1/15

2011.11 - Rev.B

BH1721FVC

●Electrical Characteristics ( VCC = 3.0V, DVI = 3.0V, Ta = 25℃, unless otherwise noted )

Parameter

Supply Current

Symbol

Min. Typ. Max.

Icc1 － 140 199 µA Ev = 100 lx

Limits

Technical Note

Units Conditions

1

※

Powerdown Current

Peak Wave Length

Measurement Accuracy

Dark ( 0 lx ) Sensor out

H-Resolution Mode Resolution

L-Resolution Mode Resolution

H-Resolution Mode Measurement Time

L-Resolution Mode Measurement Time

Incandescent / Fluorescent Sensor out ratio

DVI Input ‘L’ Voltage

SCL, SDA Input ‘H’ Voltage 1

SCL, SDA Input ‘H’ Voltage 2

SCL, SDA Input ‘L’ Voltage 1

Icc2 － 0.01 1.0 µA No input Light

λp － 560 － nm

S/A 1.02 1.2 1.38 times

S0 0 0 2 count H-Resolution Mode

Sensor out / Actual lx EV = 1000 lx

※

1, ※2

3

※

rHR － 1 － lx

rLR － 8 － lx

tHR － 120 180 ms

tLR － 16 24 ms

rIF － 1 － times EV = 1000 lx

VDVL －－ 0.4 V

VIH1 0.7 * DVI －－ V DVI ≧ 1.8V

VIH2 1.26 －－ V 1.65V ≦ DVI ＜ 1.8V

VIL1 －－ 0.3 * DVI V DVI ≧ 1.8V

SCL, SDA Input ‘L’ Voltage 2

SCL, SDA, Input ‘H’ Current

SCL, SDA, Input ‘L’ Current

I2C SCL Clock Frequency

I2C Bus Free Time

I2C Hold Time ( repeated ) START Condition

I2C Set up time for a Repeated START Condition

I2C Set up time for a Repeated STOP Condition

I2C Data Hold Time

I2C Data Valid Time

I2C Data Valid Acknowledge Time

I2C Data Setup Time

I2C ‘L’ Period of the SCL Clock

VIL2 －－ DVI – 1.26 V 1.65V ≦ DVI ＜ 1.8V

IIH －－ 10 µA

IIL －－ 10 µA

fSCL －－ 400 kHz

tBUF 1.3 －－ µs

tHDSTA 0.6 －－ µs

tSUSTA 0.6 －－ µs

tSUSTO 0.6 －－ µs

tHDDAT 0 －－ µs

tVDDAT －－ 0.9 µs

tVDACK －－ 0.9 µs

tSUDAT 100 －－ ns

tLOW 1.3 －－ µs

I2C ‘H’ Period of the SCL Clock

I2C SDA Output ‘L’ Voltage

※1 White LED is used as optical source. ※2 Measurement Accuracy typical value is possible to change '1' by "Measurement result adjustment function". ※3 Use H-Resolution Mode if dark data ( less than 20 lx ) is need.

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tHIGH 0.6 －－ µs

VOL 0 － 0.4 V IOL = 3 mA

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BH1721FVC

●Reference Data

1.2

1.0

0.8

0.6

Ratio

0.4

0.2

0.0

400 500 600 700 800 900 1000 1100

1.2

Wave length [ nm ]

Fig.1 Spectral Response

1

0.8

0.6

Ratio

0.4

0.2

0

-90 -60 -30 0 30 60 90

Fig.4 Directional Characteristics 1

1.2

1

0.8

0.6

Ratio

0.4

0.2

0

-40-20 0 20406080100

1pin

-

Angle [ deg ]

Ta [ ℃ ]

+

Fig.7 Measurement Result

Temperature Dependency

10

1

0.1

ICC @ POWER DOWN [ uA ]

0.01

-40-20 0 20406080100

Fig.10 VCC – ICC@0 lx

(POWER DOWN)

Ta [ ℃ ]

64

56

48

40

32

H-Res.

24

Measurement Result

16

8

0

0 8 16 24 32 40 48 56 64

L-Res.

Illuminance [ lx ]

Fig.2 Illuminance -

Measurement Result 1

1.2

1

0.8

0.6

Ratio

0.4

0.2

0

-90 -60 -30 0 30 60 90

-

+

Angle [ deg ]

-

1pin

+

Fig.5 Directional Characteristics 2

Fluor escent Light

Incandescent

Light

Halogen Light

Kripton Light

Artifical Sun

Light

White LED

0 0.5 1 1.5 2

Ratio

Fig.8 Light Source Dependency

(Fluorescent Light is set to ‘1’)

1.2

1

0.8

0.6

Ratio

0.4

0.2

0

2 2.5 3 3.5 4

DVI=1.8V

VCC [ V ]

Fig.11 Measurement Result

VCC Dependency

Technical Note

100000

10000

1000

100

Measurement Result

10

1

1 10 100 1000 10000 100000

Illuminance [ lx ]

Fig.3 Illuminance -

Measuremnet Result 2

10

8

6

4

Measurement Result

2

H-Res.

0

-40 -20 0 20 40 60 80 100

Fig.6 Dark Response

200

150

100

50

ICC @ Measurement

0

2 2.5 3 3.5 4

(During measurement)

1.2

1

0.8

0.6

Ratio

0.4

0.2

0

1.5 2 2.5 3 3.5

Fig.12 Measurement Result

DVI Dependency

Ta [ ℃ ]

VCC [ V ]

Fig.9 VCC – ICC

VCC=3V

DVI [ V ]

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2011.11 - Rev.B

BH1721FVC

●Block Diagram

●Block Diagram Descriptions ・PD

Photo diode with approximately human eye response.

・AMP

Integration-OPAMP for converting from PD current to Voltage.

・ADC

AD converter for obtainment Digital 16bit data.

2

・Logic + I

・OSC

●Measurement Procedure

Measurement command

Continuous measurement

C Interface

Ambient Light Calculation and I2C BUS Interface. It is including below register. Data Register → This is for registration of Ambient Light Data. Initial Value is "0000_0000_0000_0000". Measurement Time Register → This is for registration of measurement time. Initial Value is "01_0010_1100".

Internal Oscillator. It is CLK for internal logic.

Power supply

Power Down

Power On

VCC

AMP

PD

Initial state is Power Down mode after VCC and DVI supply.

ADC

OSC

GND

DVI

Logic

+

I2C Interface

State Transition by I2C write-command.

Automatically State Transition

Technical Note

SCL

SDA

* "Power On" Command is possible to omit.

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2011.11 - Rev.B

BH1721FVC

●Instruction Set Architecture

Instruction Opecode Comments

Power Down 0000_0000 No active state.

Power On 0000_0001 Waiting for measurement command.

Technical Note

Continuously Auto-Resolution Mode

Continuously H-Resolution Mode

Continuously L-Resolution Mode

Change Measurement time ( High bit )

Change Masurement time ( Low bit )

※ Don't input the other opecode.

●Measurement mode explanation

Measurement Mode Measurement Time. Measurement Range. Resolution

H-Resolution Mode Typ. 120ms

L-Resolution Mode Typ. 16ms

We recommend to use H-Resolution Mode.

Measurement time (integration time) of H-Resolution Mode is so long that some kind of noise (including in 50Hz / 60Hz noise) is rejected. And H-Resolution Mode is 1 lx resolution so that it is suitable for darkness (less than 20 lx)

Auto-Resolution mode selects measurement mode automatically. It is determined after 16ms (typ.) passes from measurement start. If BH1721FVC judges that current illuminance is more than 4000 lx, then Data is output at L-resolution mode, else Data is output after 120ms(typ.) from measurement start at H-resolution mode. Please refer below flow chart.

Data output at H-resolution mode after 120ms passes from measurement start.

Lux <= 4000

Start

Select mode

0001_0000 0010_0000

0001_0010 0010_0010

0001_0011 0001_0110 0010_0011 0010_0110

010_MT[9,8,7,6,5]

011_MT[4]_XXXX

0 - 65528 lx 8 lx

after 16ms.(typ.)

Lux > 4000

DATA output at L-resolution mode

Auto-Resolution mode measurement

Switch measurement mode automatically by illuminance.

Start measurement at 1lx resolution. Measurement Time is typically 120ms.

Start measurement at 8lx resolution. Measurement Time is typically 16ms.

Change measurement time.

※ Please refer "adjust measurement result for influence of optical window."

Change measurement time.

※ Please refer "adjust measurement result for influence of optical window."

0 - 8191 lx 1 lx

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5/15

2011.11 - Rev.B

BH1721FVC

●Timing chart for VCC and DVI power supply sequence DVI is I2C bus reference voltage terminal. And it is also asynchronous reset terminal. It is necessary to set to ‘L’ after VCC is supplied. In DVI 'L' term, internal state is set to Power Down mode.

1) Recommended Timing chart1 for VCC and DVI supply.

VCC

DVI

Reset Term (more than 1µs)

2) Timing chart2 for VCC and DVI supply.

(If DVI rises within 1µs after VCC supply)

VCC

DVI

Reset Term (more than 1µs)

Don't care state

Technical Note

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6/15

2011.11 - Rev.B

BH1721FVC

●Measurement sequence example from "Write instruction" to "Read measurement result"

ex1) Continuously Auto-resolution mode

from Master to Slave

① Send "Continuously Auto-resolution mode " instruction

ST 0100011 0 Ack 00010000 Ack SP

② Wait to complete 1st Auto-resolution mode measurement.( max. 180ms )

③ Read measurement result.

ST 0100011 1 Ack High Byte [ 15:8 ] Ack

from Slave to Master

Technical Note

Low Byte [ 7:0 ]

How to calculate when the data High Byte is "10000011" and Low Byte is "10010000"

15

+ 29 + 28 + 27 + 24 ) / 1.2 ≒ 28067 [ lx ]

( 2

The result of continuously measurement mode is updated.

ex2) Continuously L-resolution mode

① Send " Continuously L-resolution mode " instruction

ST 0100011 0 Ack 00010011 Ack SP

② Wait to complete L-resolution mode measurement.( max. 24ms )

③ Read measurement result

ST 0100011 1 Ack High Byte [ 15:8 ] Ack

Low Byte [ 7:0 ]

How to calculate when the data High Byte is "00000001" and Low Byte is "00010000"

8

+ 24 ) / 1.2 ≒ 227 [ lx ]

( 2

Ack

SP

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7/15

2011.11 - Rev.B

BH1721FVC

µ

Technical Note

●Application circuit example of DVI terminal The DVI terminal is an asynchronous reset terminal. Please note that there is a possibility that IC doesn't operate normally if the reset section is not installed after the start-up of VCC. (Please refer to the paragraph of "Timing chart for VCC and DVI power supply sequence”) The description concerning SDA and the terminal SCL is omitted in this application circuit example. Please design the application the standard of the I

2

C bus as it finishes being satisfactory.

ex 1) The control signal line such as CPU is connected.

0.1µF

BH1721FVC

SCL

VCC

GND

0.1µF

SDA DVI

Micro Controller

0.1µF

ex 2) Reset IC is used.

1, For Reset IC of the Push-Pull type

0.1

F

BH1721FVC

SCL

VCC

GND

RESET

0.1µF

SDA DVI

0.1µF

Reset IC( Push-Pull type )

2, For Reset IC of the Open drain output

0.1µF

BH1721FVC

SCL

VCC

GND

1kΩ

RESET

0.1µF

SDA DVI

0.1µF

Reset IC( Open drain type )

ex 3) A different power supply is used.

0.1µF

V1

BH1721FVC

SCL

VCC

GND

0.1µF

SDA DVI

V2

0.1µF

※ Power supply of DVI must stand up later than power supply of VCC stand up, because it is necessary to secure reset section ( 1µs or more ).

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2011.11 - Rev.B

BH1721FVC

ex 4) LPF using CR is inserted between VCC and DVI.

This method has the possibility that the Reset section of turning on the power supply can not satisfied. Cannot be satisfied. Please design the set considering the characteristic of the power supply enough.

0.1µF

BH1721FVC

SCL

VCC

GND

R1 : 1kΩ

0.1µF

SDA DVI

C1 : 1µF

◆ Notes when CR is inserted between VCC and DVI

※Please note that there is a possibility that reset section ( 1µs ) can not be satisfied because the power supply is turned on when the rise time of VCC is slow ※When VCC is turned off, the DVI voltage becomes higher than VCC voltage but IC destruction is not occred if recommended constant ( R1 = 1kΩ, C1 = 1µF ) is used. ※Please note that there is a possibility that Reset section (1µsec) cannot be satisfied if wait time is not enough long after turning off VCC.

(It is necessary to consider DVI voltage level after turning off VCC.)

t1

t2

2.4V

0.4V

0V

Reset Section: 1µs or more

* Please do the application design to secure Reset section 1µs or more after the reclosing of the power supply.

◆ Example of designing set when CR ( C = 1µF, R = 1kΩ ) is inserted between VCC and DVI with VCC=2.8V

①The rise time to 0→2.4V of VCC must use the power supply of 100µs or less. ②Please wait 25ms or more after VCC turn off ( VCC <= 0.05V ), because it is necessary to secure reset section

(1µs or more).

Rise time of power supply: 100µs or less

2.8V

0V

* Please do the application design to secure Reset section 1µs or more after the reclosing of the power supply.

0V

Time to power supply reclosing: 25ms or more

2.4V

0.4V

0.05V

Reset Section: 1µs or more

Technical Note

VCC

DVI

VCC

DVI

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9/15

2011.11 - Rev.B

BH1721FVC

●I2C Bus Access 1 ) I2C Bus Interface Timing chart

Write measurement command and Read measurement result are done by I

2

C Bus interface. Please refer the formally

specification of I2C Bus interface, and follow the formally timing chart.

SDA

tf

SCL

S

t

LOW

t

HD ; STA

t

tr

SU ; DAT

t

f

t

HD ; STA

t

HD ; DAT

t

HIGH

SU ; STA

Sr

t

SU;STO

2 ) Write Format

BH1721FVC is not able to accept plural command without stop condition. Please insert SP every 1 Opecode.

ST

Slave Address

"0100011"

R/W

0

Ack

Opecode Ack SP

3 ) Read Format

ST

Slave Address

"0100011"

R/W

1

Ack

High Byte [15:8]

15 214 213 212 211 210 29 28

2

7 26 25 24 23 22 21 20

2

Low Byte [7:0]

SP

Ack

from Master to Slave

from Slave to Master

ex )

High Byte = "1000_0011" Low Byte = "1001_0000"

15

+ 29 + 28 + 27 + 24 ) / 1.2 ≒ 28067 [ lx ]

( 2

* Please refer formality I2C bus specification of NXP semiconductors.

Technical Note

tr

t

BUF

P

S

Ack

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2011.11 - Rev.B

BH1721FVC

Technical Note

●Adjust measurement result for influence of optical window. (sensor sensitivity adjusting ) BH1721FVC is possible to change sensor sensitivity. And it is possible to cancel the optical window influence (difference with / without optical window) by using this function. Adjust is done by changing measurement time. For example, when transmission rate of optical window is 50% (measurement result becomes 0.5 times if optical window is set), influence of optical window is ignored by changing sensor sensitivity from default to 2 times

Sensor sensitivity is shift by changing the value of MTreg (measurement time register). MTreg value has to set 2 times if target of sensor sensitivity is 2 times. Measurement time is also set 2 times when MTreg value is changed from default to 2 times. Low 4bit value is fixed”1100”. Please change high 6bit value of this register via to I

2

C Bus interface.

ex) Procedure for changing target sensor sensitivity to 2 times.

Please change Mtreg from”01_0010_1100” (default) to”10_0101_1100” (default * 2).

1) Changing High bit of Mtreg

ST

Slave Address

R/W

0

Ack

010_10010 Ack SP

2) Changing Low bit of Mtreg

ST

Slave Address

R/W

0

Ack

011_1XXXX Ack SP

* X value is ignore.

3) Input Measurement Command.

ST

Slave Address

R/W

0

Ack

* This example is High Resolution mode, but it accepts the other measurement.

0001_0000 Ack SP

4) After about 240ms, measurement result is registered to Data Register. (High Resolution mode is typically 120ms, but

measurement time is set twice. )

The below table is seeing the changeable range of MTreg.

changeable range of MTreg

binary

decimal

( sensitivity : default * 0.47 )

Min. Typ. Max.

00_1000_1100

140

01_0010_1100

default

300

default

11_1111_1100

( sensitivity : default * 3.40 )

1020

( sensitivity : default * 3.40 )

It is possible to detect 0.25lx by using this function at H-resolution mode. The below formula is to calculate illuminance per 1 count.

Illuminance per 1 count (lx / count) = 1 / 1.2 *(300 / X)

: Measurement accuracy

1.2 300 : Default value of MTreg ( dec )

: MTreg value

X

The below table is seeing the detail of resolution.

MTreg value lx / count

00_1000_1100 1.79

01_0010_1100 0.83

11_1111_1100 0.25

Please input the opecode at PowerDown state to change Mtreg.There is a possibility of malfunctioning when the opecode to change Mtreg is input while the illuminance measurement is going .

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2011.11 - Rev.B

BH1721FVC

●Terminal Description

No.

Terminal Name Equivalent Circuit Function

1 VCC

2 GND

3 SDA

4 DVI

5 SCL

※These values are design-value, not guaranteed.

150kΩ

Technical Note

Power Supply Terminal

GND Terminal

2

C bus Interface SDA Terminal

I

SDA, SCL Reference Voltage Terminal And DVI Terminal is also asynchronous Reset for internal registers.So that please set to 'L' ( at least 1µs, DVI <= 0.4V ) after VCC is supplied. BH1721FVC is pulled down by 150k Ω while DVI = 'L'.

2

C bus Interface SCL Terminal

I

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2011.11 - Rev.B

BH1721FVC

●Package Outlines

A E

Production code

●Optical design for the device

0.8 mm

Min.0.4 mm

Lot No.

0.6 mm

Technical Note

WSOF5 (Unit: mm)

PD area (0.25 mm x 0.3 mm)

Min.0.4 mm

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Min.0.4 mm

Please design an optical window to have the focused light within this area.

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BH1721FVC

●Notes for use

1) Absolute Maximum Ratings An excess in the absolute maximum ratings, such as supply voltage ( Vmax ), temperature range of operating conditions (Topr), etc., can break down devices, thus making impossible to identify breaking mode such as a short circuit or an open circuit. If any special mode exceeding the absolute maximum ratings is assumed, consideration should be given to take physical safety measures including the use of fuses, etc.

2) GND voltage Make setting of the potential of the GND terminal so that it will be maintained at the minimum in any operating state. Furthermore, check to be sure no terminals are at a potential lower than the GND voltage including an actual electric transient.

3) Short circuit between terminals and erroneous mounting In order to mount ICs on a set PCB, pay thorough attention to the direction and offset of the ICs. Erroneous mounting can break down the ICs. Furthermore, if a short circuit occurs due to foreign matters entering between terminals or between the terminal and the power supply or the GND terminal, the ICs can break down.

4) Operation in strong electromagnetic field Be noted that using ICs in the strong electromagnetic field can malfunction them.

5) Inspection with set PCB On the inspection with the set PCB, if a capacitor is connected to a low-impedance IC terminal, the IC can suffer stress. Therefore, be sure to discharge from the set PCB by each process. Furthermore, in order to mount or dismount the set PCB to/from the jig for the inspection process, be sure to turn OFF the power supply and then mount the set PCB to the jig. After the completion of the inspection, be sure to turn OFF the power supply and then dismount it from the jig. In addition, for protection against static electricity, establish a ground for the assembly process and pay thorough attention to the transportation and the storage of the set PCB.

6) Input terminals In terms of the construction of IC, parasitic elements are inevitably formed in relation to potential. The operation of the parasitic element can cause interference with circuit operation, thus resulting in a malfunction and then breakdown of the input terminal. Therefore, pay thorough attention not to handle the input terminals; such as to apply to the input terminals a voltage lower than the GND respectively, so that any parasitic element will operate. Furthermore, do not apply a voltage to the input terminals when no power supply voltage is applied to the IC. In addition, even if the power supply voltage is applied, apply to the input terminals a voltage lower than the power supply voltage or within the guaranteed value of electrical characteristics.

7) Thermal design Perform thermal design in which there are adequate margins by taking into account the power dissipation ( Pd ) in actual states of use.

8) Treatment of package Dusts or scratch on the photo detector may affect the optical characteristics. Please handle it with care.

9) Rush current When power is first supplied to the CMOS IC, it is possible that the internal logic may be unstable and rush current may flow instantaneously. Therefore, give special consideration to power coupling capacitance, power wiring, width of GND wiring, and routing of connections.

10) The exposed central pad on the back side of the package There is an exposed central pad on the back side of the package. Please mount by Footprint dimensions described in the Jisso Information for WSOF5. This pad is GND level, therefore there is a possibility that LSI malfunctions and heavy-current is generated.

Technical Note

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BH1721FVC

●Ordering part number

B H 1 7 2 1 F V C - T R

Technical Note

Part No. Part No.

Package

WSOF5

1.6±0.05

0.6MAX

1.2±0.05

+0.03

0.02

(MAX 1.28 include BURR)

−0.02

1.6±0.05

1.0±0.05

(0.05)

0.5

4

5

321

0.22±0.05

(0.91)

S

(0.41)

0.1 S

(0.8)

(0.3)

45

1

32

0.08

0.2MAX

0.13±0.05

M

(Unit : mm)

Quantity

Direction of feed

Packaging and forming specification

FVC: WSOF5

Embossed carrier tapeTape 3000pcs

TR

The direction is the 1pin of product is at the upper right when you hold

()

reel on the left hand and you pull out the tape on the right hand

Reel

Order quantity needs to be multiple of the minimum quantity.

∗

TR: Embossed tape and reel

1pin

Direction of feed

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2011.11 - Rev.B

Notes

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Examples of application circuits, circuit constants and any other information contained herein illustrate the standard usage and operations of the Products. The peripheral conditions must be taken into account when designing circuits for mass production.

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ROHM BH1721FVC Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual