ROHM BD9740KN Technical data

Regulators ICs for Digital Cameras and Camcorders

System Switching Regulator ICs with Built-in FET (10V)

BD9739KN, BD9740KN

●Description The 7-channel switching regulators include built-in FETs, and are designed for use in digital still cameras. They feature built-in power FETs and soft start functionality, reducing the number of external components.

●Features

1) Wide supply voltage range: 1.5 V to 10 V

2) High-precision reference voltage: ± 1%

3) Built-in shutdown circuit for overload (timer-latch type)

4) Oscillator frequency is user-adjustable

5) Built-in thermal shutdown circuit

6) Standby mode current: 0 μA

7) Built-in load switch circuit

8) Selectable step-up/step-down mode

9) Supports inverting circuit for negative output voltage

10) Support a constant-current LED drive for backlight applications

11) Includes multiple synchronous rectification channels

●Applications Digital still cameras, portable DVD players, and digital video cameras.

●Product lineup

No.10036EAT07

Parameter BD9739KN BD9740KN Input voltage 1.5 V to 10 V 1.5 V to 10 V Reference voltage precision 1 V ± 1% 1 V ± 1% Operating frequency range 100 k to 1.2 MHz 100 k to 1.2 MHz Step-up 3CH 2CH Step-down 2CH 1CH Step-up/step-down switch regulator 1CH 3CH Inverting 1CH 1CH Built-in FET 3CH 1CH Synchronous rectification 3CH 2CH Load switching 3CH — Operating temperature range -20℃ to +85℃ -20℃ to +85℃ Package UQFN64 UQFN48

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BD9739KN,BD9740KN

●Absolute maximum ratings

Technical Note

Parameter Symbol

BD9739KN BD9740KN

Ratings

VBAT,VCC,PVCC -0.3 to +12 -0.3 to +12 V

PVCCH,PVCCL -0.3 to +15 -0.3 to +15 V

DRAIN*H, DRAIN*L -0.3 to +12 -0.3 to +12 V

Maximum supply voltage

OUT1B -0.3 to +20 -0.3 to +20 V OUT2B -0.3 to +17 ― V

SWOUT1,4,PGIN1,PG2,3 -0.3 to +12 ― V

SWIN* -0.3 to +20 ― V

UQFN64 UQFN48

Power dissipation Pd

550

1000

*1-2

*2-2

500

760 Operating temperature range Topr -25～+85 ℃ Storage temperature range Tstg -55～+125 ℃ Junction temperature T

*1: IC without heat sink operation. Reduce by 5.5 mW/℃ (1-2), or 5.0 mW/℃ (1-3) when Ta ≥ 25℃. *2: When mounted on a PCB (70 mm 70 mm 1.6 mm (thickness), glass epoxy). Reduced by 10.0 mW/℃ (2-2), or 7.6 mW/℃ (2-3), when Ta ≥ 25℃.

+125 ℃

jmax

●Recommended operating ranges

Parameter Symbol

BD9739KN BD9740KN

Ratings

VBAT 1.5 to 10 1.5 to 10 V

Supply voltage

VCC, PVCC 1.5 to 10 2.8 to 10 V

PVCCL, PVCCH 4.0 to 14 4.0 to 14 V

Parameter Symbol

Min. Typ. Max.

Ratings

Unit Conditions

[Oscillator] Oscillating frequency f

0.1 — 1.2 MHz

OSC

[Driver block] DRAIN pin input voltage V

N-channel FET output current (step-down) N-channel FET output current (step-up)

LED channel output current I Driver output current I Driver peak current I Startup NPN TR sink current I

— — 10 V

DRAIN

— — 700 mA

OFET1

— — 300 mA

OFET2

— — 40 mA

OLED

— — 30 mA External FET drive circuit

OUT

— — 200 mA External FET drive circuit

PEAK

— — 500 mA

NPNSINK

[Positive/negative regulators] SWOUT1 pin sink current I PGOUT1 pin source current I PG23 pin sink current I SWOUT4 pin source current I SWOUT6 pin source current I SWOUT7 pin source current I

— — 10 mA

SWOUT1

— — 100 mA

PGOUT1

— — 1 mA

PG23

— — 50 mA (BD9739KN)

SWOUT4

— — 50 mA

SWOUT6

— — 50 mA

SWOUT7

*1-3 *2-3

Unit

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●Electrical characteristics (Unless otherwise specified, Ta = 25℃, VBAT = 3 V, VCC = 5 V, RT = 11 k, CT = 180 pF, STB1 to STB7 = 3 V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Conditions

[Reference voltage, reference voltage for inverting] Output voltage V

0.99 1.0 1.01 V

REF2

Line regulation DVLI － 4.0 12.5 mV VCC = 3.0 V to 9.5 V Load regulation DVLO － 1.0 7.5 mV IREF = 10 μA to 100 μA Output current when shorted IOS 0.2 1 － mA VREF = 0 V [Internal regulator] Output voltage REGA V

2.4 2.5 2.6 V IREG = 1 mA

REGA

[Under voltage lockout circuit] Detection threshold voltage 1 V Hysteresis width 1 ΔV Detection threshold voltage 2 V Hysteresis width 2 ΔV Detection threshold voltage 3 V Hysteresis width 3 ΔV

3.45 3.6 3.75 V PVCCL monitor

STD1

－ 300 － mV

ST1

2.3 2.4 2.5 V VCC monitor

STD2

－ 200 － mV

ST2

－ 2.0 － V VREGA monitor

STD3

－ 50 － mV

ST3

[Startup circuit block] Oscillating frequency f Operation start VBAT voltage V Soft start charge current I

50 120 220 kHz

START

1.5 －－ V VBAT pin monitor

ST1

1.1 2.2 3.3 µA VSS1 = 0 V

SS1

[Short protection circuit ] Timer threshold voltage VTC 2.1 2.2 2.3 V FB pin monitor

SCP pin source current I

SCP pin detection voltage V SCP pin standby voltage V

SCP

TSC

SSC

0.5 1.0 1.5 µAVSCP = 0.1 V 2 4 6 (BD9740KN)

0.45 0.50 0.55 V

0.9 1.0 1.1 (BD9740KN)

－ 22 170 mV [Triangular waveform oscillator] Oscillating frequency f

450 500 550 kHz RT = 11 k, CT = 180 pF

OSC1

Frequency stability Df － 0.3 2 % VCC = 3.0 V to 9.5 V RT pin voltage VRT 0.78 1.00 1.22 V [Soft start 23 block] (BD9738KN, BD9739KN) Soft start charge current I

5 10 15 µA VSS23 = 0 V

SS23

[Error amp] Low-level output voltage VOL － 1.3 － V INV = 2 V High-level output voltage VOH V

- 0.3 －－ V INV = 0 V

REGA

Output sink current IOI 36 72 － µA FB = 1.7 V, VINV = 1.1 V Output source current IOO 36 72 － µA FB = 1.7 V, VINV = 0.9 V DTC pin upper resistance R DTC pin lower resistance R NON pin input range I Non-inverted pin reference volt age V

20 30 40 kΩ (BD9740KN)

DTCU

65 95 125 kΩ (BD9740KN)

DTCD

-0.3 - 1.5 V

RES

－ 0.2 － V

NON7

[PWM comparator]

－ 1.49 － V 0% duty

Input threshold voltage MAX DUTY D

MAX DUTY (step-up operation) D

－ 1.95 － V 100% duty

T100

77 85 93 % VINV = 0.9 V, VSCP = 0 V

MAX1

77 85 93 %

MAX2

VINV = 0.9 V,

VSCP, UDSEL = 0 V [Output circuit] High-level output voltage V Low-level output voltage V

High-side N-channel FET on resistance

Low-side N-channel FET on resistance

CH7 N-channel FET on resistance

VCC-1.6 VCC-0.8 － V IO = 30 mA

SATH

－ 0.8 1.6 V IO = -30 mA

SATL

ONH

ONL

ONL7

－ 270 500 mΩPVCCH = 5 V(IO = 200 mA) － 300 500 (BD9740KN) － 270 500 mΩPVCCL = 5 V(IO = 200 mA) － 300 500 (BD9740KN)

－ 0.7 1.4 Ω PVCCL = 5 V(IO = 50 mA)

[Step-up/step-down selector ] UDSEL pin

control voltage

Note: This IC is not designed to be radiation-resistant.

Step-down V Step-up V

VCC×0.7 － V

UDDO

0 － VCC×0.3 V

UDUP

Technical Note

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(Unless otherwise specified, Ta = 25℃, VBAT = 3 V, VCC = 5 V, RT = 11 kΩ, CT = 180 pF, STB1 to STB7 = 3 V)

Parameter Symbol

Min. Typ. Max.

Limits

Unit Conditions [Power on switching block] (BD9739KN) SWOUT1

SWOUT4

SWOUT4,6

SWOUT7

Output voltage V Leak current I Output voltage V Leak current I

－ 0.1 0.3 V IO = 1 mA

SAT

－ 0 5 µA STB = 0 V

LEAK

－ 0.1 0.3 V IO = 100 μA

SAT

－ 0 5 µA STB = 0 V

LEAK

SAT

－ 0 5 µA STB = 0 V

LEAK

SAT

－ 0 5 µA STB = 0 V

LEAK

SWIN6

SWIN7

- 0.3 V

- 0.1 － V

SWIN6

- 0.1 － V

SWIN7

IO = 20 mA VSWIN = 5 V

IO = 10 mA VSWIN = 10 V

[Soft start block] (BD9740KN)

VCC = PVCC = 5V,

mse

Soft start time of CH4 T

Soft start time of CH2, 3 T

CH2, CH3 soft start INV4 threshold voltage at start

1.8 3.6 6.0

SS1

1.8 3.6 6.0

SS2

0.72 0.80 0.88 V

PG4

PVCCH = 5.0V

STB 0→3 V VCC = PVCC = 5V,

mse

STB = 3 V

INV4 = 0→1.2 V VCC = PVCC = 5 V

PVCCH = 5.0 V

[STB1 to STB7] STB pin control voltage

ON V OFF V

STB pin pull-down resistance R

2.0 － 11 V STB

STBH

-0.3 － 0.3 V

STBL

250 400 700 kΩ STB

STB

[Circuit current] Standby current 1

(VBAT pin sink current) Standby current 2

(VCC, PVCC pin sink current) Circuit current at startup

(VBAT pin sink current) Circuit current 1

(VBAT pin sink current) Circuit current 2

(VCC, PVCC pin sink current)

Note: This IC is not designed to be radiation-resistant.

－－ 5 µA STB1 to STB7 = 0 V

STB1

－－ 5 µA STB1 to STB7 = 0 V

STB2

－ 30 100 mA

－ 100 300 µA CT = 1.7 V

CC1

－ 5 15 mA

CC2

CT = 1.7 V VCC = 0 V

CT = 1.7 V INV = 2.5 V

●PVCCH and PVCCL input voltages

PVCCH

 Synchronous rectification channels with built-in FETs include, N-channel FETs

for both the high-side and low-side configuration. The driver block's power source is supplied to the PVCCL pin for the low-side and the PVCCH pin for

PVCCL

the high-side. (For the BD9740KN, both sides are supplied to the PVCCH pin.) In order to turn the FET on, a potential of at least 4 V must be supplied to the

DRAINH

PVCCL pin, and a potential of at least, DRAINH pin voltage + 4 V, must be supplied to the PVCCH pin.

Note:

DRAINL

 The breakdown voltage for the PVCCL and PVCCH pins is 15 V.

For applications that with voltages exceeding 15 V, add a zener diode, or other

components, to provide overvoltage protection.

 Shorting the DRAINH pin with the ground, while a charge remains in the output

capacitor, may cause unexpected current flow, resulting in damage to the IC.

PGND

Add an external protective diode for applications where this possibility exists.

Fig. 1 Synchronous Rectification

Channel with Built-In FET

Technical Note

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●Block diagram and application circuit (BD9739KN)

Connect a capacitor to prevent oscillation to the VREF pin. (See page 7.)

For more information about setting the SCP pin, (See page 7.)

Connect a capacitor for setting the soft star t time . (See pages 8& 9.)

Connect a capacitor for soft start at DTC pin. (See page 8.)

Connect a resistor for setting the output voltage. (See page 8.)

The soft start times for CH4, 6, 7 are fixed internally. (See page 9.)

Set the operating frequency with the RT and CT pins. (See page 8.)

Connect a capacitor to prevent oscillation to the VREGA pin. (See page 7.)

Set whether CH1 and CH5 will be used as step-up, step-down or inversion. (See page 7.)

This pin is used as the on/off control pin. (See page 7.)

Fig. 2 BD9739KN Application Circuit

Technical Note

Apply the PVCCH pin voltage with an external charge pump. (See page 4.)

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ROHM BD9740KN Technical data

Specifications and Main Features

Frequently Asked Questions

User Manual