ROHM BD9673EFJ Technical data

Single-chip Type with Built-in FET Switching Regulators

Flexible Step-down
Switching Regulator
with Built-in Power MOSFET

BD9673EFJ

●Description

Output 1.5A and below High Efficiency Rate Step-down Switching Regulator Power MOSFET Internal Type BD9673EFJ
mainly used as secondary side Power supply, for example from fixed Power supply of 12V, 24V etc, Step-down Output of

1.2V/1.8V/3.3V/5V, etc, can be produced. This IC has external Coil/Capacitor down-sizing through 300 kHz Frequency
operation, inside Nch-FET SW for 45V “withstand-pressure” commutation and also, high speed load response through
Current Mode Control is a simple external setting phase compensation system, through a wide range external constant, a
compact Power supply can be produced easily.

●Features

1) Internal 200 mΩ Nch MOSFET

2) Output Current 1.5A

3) Oscillation Frequency 300kHz

4) Synchronizes to External Clock ( 200kHz～500kHz )

5) Feedback Voltage 1.0V±1.0%

6) Internal Soft Start Function

7) Internal Over Current Protect Circuit, Low Input Error Prevention Circuit, Heat Protect Circuit

8) ON/OFF Control through EN Pin (Standby Current 0 A Typ.)

9) Package: HTSOP-J8 Package

●Applications

For Household machines in general that have 12V/24V Lines, etc.

●Absolute Maximum Rating

Parameter Symbol Ratings Unit

No.12027ECT57

VCC-GND Supply Voltage
BST-GND Voltage
BST-Lx Voltage
EN-GND Voltage
Lx-GND Voltage
FB-GND Voltage
VC-GND Voltage
SYNC-GND Voltage
High-side FET Drain Current
Power Dissipation
Operating Temperature
Storage Temperature
Junction Temperature

(*1)During mounting of 70×70×1.6t mm 4layer board (Copper area:70mm×70mm).Reduce by 30.08mW for every 1℃ increase. (Above 25℃)

●Operating Conditions (Ta=25℃)
Parameter Symbol

Power Supply Voltage VCC 7 － 42 V
Output Voltage VOUT 1.0

(*2)Restricted by minimum on pulse typ. 200ns

VCC 45 V

VBST 50 V

⊿VBST 7 V

VEN 45 V

VLX 45 V
VFB 7 V

VC 7 V

SYNC 7 V

IDH 2.0 A

Pd 3.76
Topr -40～+105 ℃
Tstg -55～+150 ℃

Tjmax +150 ℃

Min. Typ. Max.

(*2)

－ VCC×0.7 V

(*1)

W

Ratings

Unit

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1/18

2012.02 - Rev.C

BD9673EFJ

●Electrical Characteristics (Unless otherwise specified, Ta=25℃,VCC=24V, Vo=5V, EN=3V)
Parameter Symbol

Min. Typ. Max.

Limits

【Circuit Current】

Technical Note

Unit Conditions

Stand-by current of VCC

Circuit current of VCC

【Under Voltage Lock Out (UVLO)】

Detect Voltage

Hysteresis width

【Oscillator】

Oscillating frequency

Max Duty Cycle

【Error Amp】

FB threshold voltage

Input bias current

Error amplifier DC gain

Trans Conductance

Soft Start Time

Ist － 0 10 µA

Icc

－

1 2 mA

Vuv 6.1 6.4 6.7 V

Vuvhy

－

200 300 mV

fosc 270 300 330 kHz

Dmax 85 91 97 %

VFB 0.990 1.000 1.010 V

IFB -1.0 0 1.0 µA

A

700 7000 70000 V/V

VEA

110 220 440 µA/V

G

EA

Tsoft 7 10 13 ms

VEN=0V

FB=1.2V

VFB=0V

IVC=±10µA,
VC=1.5V

【Current Sense Amp】

VC to switch current transconductance

【Output】

Lx NMOS ON resistance

Lx pre-charge NMOS ON resistance

Over Current Detect Current

【CTL】

EN Pin Control voltage

ON
OFF

EN Pin input current

【SYNC】

SYNC Pin Control voltage

High
Low

SYNC Pin input current

SYNC falling edge to LX rising edge delay

◎ Not designed to withstand radiation.

5 10 20 A/V

G

CS

RonH － 200 340 mΩ

RonL

－

10 17 Ω

Iocp 2.0 3.3 － A

VENON 2 － VCC V

VENOFF -0.3 － 0.8 V

REN 2.7 5.5 11 µA

VSYNCH 2.0 － 5.5 V
VSYNCL -0.3 － 0.8 V

REN 6 12 24 µA

tdelay 200 400 600 ns

VEN=3V

VSYNC=3V

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2/18

2012.02 - Rev.C

V

A

A

BD9673EFJ

●Pin Description

8765

Thermal Pad

Technical Note

Pin

No.

Pin

Name

Function

1 Lx Terminal for inductor

2 GND Ground pin

3 VC Error amplifier output

4 FB Inverting node of the trans conductance error amplifier

1 234

Fig.1 Pin Layout Diagram

●Block Diagram

ON/OFF

EN

FB

1.0

Soft

Start

­+
+

TSD

shutdown

Error

MP

VC

ReferenceUVLO

VREF

Comparator

-

Σ

+

Oscillator

300kHz

5 SYNC

Input pin of an external signal for the device
synchronized by external signal

6 EN Stand-by ON/OFF pin

7 BST Voltage Supply pin for High Side FET Driver

8 VCC Voltage input pin

VCC

REG

Sense

Current

Current

RQ
S

MP

BST

200mΩ

LX

10Ω

GND

SYNC

Fig.2 Block Diagram

VOUT

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3/18

2012.02 - Rev.C

BD9673EFJ

●Block Description

1. Reference
This block generates Error Amp standard voltage.
Standard voltage is 1.0V.

2. REG
This is a Gate Drive Voltage Generator and 5V Low saturation regulator for internal circuit power supply.

3. OSC
This is a precise wave oscillation circuit with operation frequency fixed to 300 kHz fixed (self-running mode).
To implement the synchronization feature connect a square wave (Hi Level: higher than 2V, Low Level: lower than

0.8V )to the SYNC pin. The synchronization frequency range is 200 kHz to 500 kHz. After connecting the rising edge of
LX will be synchronized to the falling edge of SYNC pin signal after 3 counts. At the synchronization remove the
external clock, the device transitions self-running mode after 7 microseconds.

4. Soft Start
A circuit that does soft start to the output voltage of DC/DC comparator, and prevents rush current during start-up.
Soft start time is set at IC internal, after 10 ms from starting-up EN pin, standard voltage comes to 1.0V, and output
voltage becomes set voltage.

5. ERROR AMP
This is an Error amplifier what detects output signal, and outputs PWM control signal.
Internal Standard Voltage is set to 1.0V.
Also, C and R are connected between the output (VC) pin GND of Error Amp as Phase compensation elements.
(See p.11)

6. ICOMP
This is a Voltage-Pulse Width Converter that controls output voltage in response to input voltage.
This compares the Voltage added to the internal SLOPE waveform in response to the FET WS current with Error
amplifier output voltage, controls the width of output Pulse and outputs to driver.

7. Nch FET SW
This is an internal commutation SW that converts Coil Current of DC/DC Comparator.
It contains 45V” with stand pressure” 200mΩ SW.
Because the Current Rating of this FET is 2.0A included ripple current, please use at within 2.0A.
The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13msec restart.

8. UVLO
This is a Low Voltage Error Prevention Circuit.
This prevents internal circuit error during increase of power supply voltage and during decline of power suppl y voltage.
It monitors VCC pin voltage and internal REG voltage, and when VCC voltage becomes 6.4V and below, it turns off all
output FET and turns off DC/DC comparator output and soft start circuit resets.
Now this threshold has hysteresis of 200mV.

9. TSD
This is a Heat Protect (Temperature Protect) Circuit.
When it detects an abnormal temperature exceeding Maximum Junction Temperature (Tj=150℃), it turns off all output
FET, and turns off DC/DC comparator output. When Temperature falls, it has/with hysteresis and automatically returns.

10. EN
With the Voltage applied to EN Pin (6pin), IC ON/OFF can be controlled.
When a Voltage of 2.0V or more is applied, it turns on, at open or 0V application, it turns off.
About 550 kΩ pull-down resistance is contained within the pin.

Technical Note

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4/18

2012.02 - Rev.C

BD9673EFJ

Technical Note

●Detailed Description

◇Synchronizes to External Clock

The SYNC pin can be used to synchronize the regulator to an exter nal system clock. To implement the synchronization
feature connect a square wave to SYNC pin. The square wave am plitude must transition lo wer than 0.8V and higher than

2.0V on the SYNC pin and have an on time greater than 100 ns and an off time greater than 100 ns. The synchronization
frequency range is 200 kHz to 500 kHz. The rising edge of the LX will be synchronized to the falling edge of SYNC pin
signal after SYNC input pulse 3 count. At the synchronization, the external clock is removed, the device transitions
self-running mode after 7 microseconds. If the function of the synchronization is not used, please connect SYNC pin to
ground.

SYNC

SYNC_LATCH

Set the latch for
synchronization

400nsec

Lx

about
7µsec

Fig.3 Timing chart at Synchronization

◇SOFT START

The soft start time of BD9763EFJ is determined by the DCDC operating frequency (self-run mode 300 kHz ⇒10ms).
If synchronization is used at the time of EN=ON, The soft start time is restricted by SYNC pin input pulse frequency.
SYNC pin input pulse frequency is fosc_ex kHz, the soft start time is expressed by below equation.

Tss = × 10 [ms]

300

fosc_ex

◇The case of not using the function of synchronization

Although the SYNC pin is pulled down by resistor in this

device, if the function of the synchronization is not used
, it is recommended to connect SYNC pin to ground.

Fig.4 the method to disposal the SYNC pin without synchronization

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5/18

2012.02 - Rev.C

BD9673EFJ

◇OCP operation

The device has the circuit of over current protection for protecting the FET from over current.
To detect OCP 2 times sequentially, the device will stop and after 13msec restart.

VC

VC voltage rising by

output connect to GND

OCP threshold

Lx

VC voltage discharged

by OCP latch

force the High side FET OFF

by detecting OCP current

(pulse by pulse protection)

output connect to GND

VOUT

OCP

set the OCP latch by detectin g

the OCP current 2 times sequencially

OCP_LATCH

Fig.5 Timing chart at OCP operation

Technical Note

OCP latch reset after 13 msec

(300ｋHz 4000 counts)

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6/18

2012.02 - Rev.C

BD9673EFJ

●Reference Data (Unless otherwise specified, Ta=25℃,VCC=24V, Vo=5V,EN=3V)

1

0.9

0.8

0.7

0.6

0.5

ICC[uA]

0.4

0.3

0.2

0.1

0

-60 -40 -20 0 20 40 60 80 10 0 120

VCC=12V

Tem p[℃ ]

VCC= 42V

VCC= 36V

VCC= 24V

2

1.5

1

ICC[mA]

0.5

0

0 5 10 15 20 25 30 35 40 45

Tem p=1 05℃

Tem p= 25℃

Tem p=‐40℃

VCC[V]

Fig.6. Standby Current

Temperature Characteristics

Power supply Voltage Characteristics

Fig.7. Circuit Current

8

7

6

5

4

3

2

UVLOthreshold[V]

1

0

detectvoltage

-60 -40 -20 0 20 40 60 80 100 120

Tem p[℃ ]

Fig.9. UVLO Threshold

Temperature Characteristics

resetvoltage

350

340

330

320

310

300

290

280

FREQUENCY[kHz]

270

260

250

-60 -40 -20 0 20 40 60 80 100 120

Tem p[℃]

Fig.10. Oscillation Frequency

Temperature Characteristics

1.010

1.008

1.006

1.004

1.002

1.000

0.998

0.996

VFBthreshold[V]

0.994

0.992

0.990

VCC= 12V

-60 -40 -20 0 20 40 60 80 100 120

Tem p[℃ ]

VCC= 36V

VCC= 24V

VCC= 42V

1.010

1.008

1.006

1.004

1.002

1.000

0.998

0.996

VFBthreshold[V]

0.994

0.992

0.990

0 5 10 15 20 25 30 35 40 45

Tem p=1 05℃

Tem p= 25℃

VCC[V]

Tem p=‐40℃

Fig.12. FB Threshold Voltage

Temperature Characteristics

Fig.13. FB Threshold Power

supply Characteristics

Technical Note

2

1.5

1

ICC[mA]

0.5

0

-60 -40 -20 0 20 40 60 80 100 120

Temperature Characteristics

100

90

80

70

60

50

MAXDU TY[% ]

40

30

20

10

0

-60 -40 -20 0 20 40 60 80 100 120

Fig.11. Max Duty Temperature

60

50

40

30

20

10

0

‐10

‐20

‐30

‐40

VCterminalcurrent[uA]

‐50

‐60

00.511.52

Fig.14. FB Voltage －VC

Current Characteristics

VCC= 12V

VCC= 24V

VCC=36V

Tem p[℃ ]

Fig.8. Circuit Current

Tem p[℃ ]

Characteristics

Tem p=1 05℃

Tem p=2 5℃

Tem p=‐40℃

VFB[V]

VCC=42V

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7/18

2012.02 - Rev.C

BD9673EFJ

16

14

12

10

8

VCC= 12V

6

4

SoftStartTime [ms]

2

0

-60 -40 -20 0 20 40 60 80 100 120

VCC= 24V

VCC= 36V

VCC= 42V

Tem p[℃]

300

250

200

150

100

50

HIGHSIDEFETRON [mΩ]

0

-60 -40 -20 0 20 40 60 80 100 1 20

Tem p[℃ ]

20

15

10

5

PRECHARGEFETRO N [Ω]

0

-60 -40 -20 0 20 40 60 80 100 120

Fig.15. Soft Start Time

Temperature Characteristics

Fig.16. Nch FET ON Resistance

Temperature Characteristics

Fig.17. Pre-charge FET ON Resistance

Temperature Characteristics

6

5

4

3

2

1

OCP_peak_curre nt[A]

0

-60 -40 -20 0 20 40 60 80 100 120

VCC=12V

Tem p[℃ ]

VCC= 24V

VCC= 36V

VCC= 42V

14
13
12
11
10

9
8
7
6
5
4

VCtoSWCurrent

3
2

transconductance[A/V]

1
0

-60 -40 -20 0 20 40 60 80 100 120

Tem p[℃ ]

2

1.5

1

0.5

ENThre shold[V]

0

Fig.18. OCP Detect Current

Temperature Characteristics

Fig.19. VC to SW current transconductance

Temperature characteristics

Fig.20. EN Threshold Temperature

Technical Note

Tem p[℃ ]

-60 -40 -20 0 20 40 60 80 100 120

Tem p[℃ ]

Characteristics

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8/18

2012.02 - Rev.C

V

x

V

(

)

k

A

BD9673EFJ

●Example of Reference Application Circuit (Input 24V, Output 5.0V/ 1A)

5V/1

VOUT

47µF/15
GRM32EB31C476KE15 (murata)

15µH

CDRH105R

(SUMIDA)

RB056L-40(ROHM)

L

GND

R1 120k Ω

R2 30k

Ω

C1 6800pF

R3 10

Ω

VC

FB

Fig.21 Reference Application Circuit

●Reference Application Data (Example of Reference Application Circuit)

100

90

80

70

60

50

40

30

20

10

Transformation Efficie ncyη[%]

0

0 500 1000 1500

Fig.22 Electric Power Conversion Rate

VCC=42V

LOADCURRENT[mA]

VCC= 12V

VCC= 24V

VCC= 36V

Fig.23 Frequency Response

Characteristics(Io=0.5A）

Phase

Gain

VOUT：200mV/div (AC)

IL：500mA/div (DC)

Fig.25 Load Response Characteristics

(Io=0A→1.5A)

Fig.26 Load Response Characteristics

EN：5V/div (DC)
LX：10V/div (DC

IL：0.5A/div (DC)
VOUT：2V./div (DC)

0.01µF

VCC

BST

EN

SYNC

(Io=1.5A→0A)

Technical Note

10uF/35
GRM31EB3YA106KA12L

murata

Phase

Gain

Fig.24 Frequency Response

Characteristics (Io=1.0A）

VOUT：200mV/div (AC)

IL：500mA/div (DC)

VCC 24

ON/OFF

EN

control

SYNC

EN：5V/div (DC)
LX：10V/div (DC

IL：0.5A/div (DC)
VOUT：2V./div (DC)

Fig.27 startup Waveform

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9/18

Fig.28 Stop Waveform

2012.02 - Rev.C

r

A

r

A

BD9673EFJ

●Evaluation Board Layout

Layout is a critical portion of good power supply design. There are several signals paths that conduct fast changing currents
or voltages that can interact with stray inductance or parasitic capacitance to generate noise or degrade the power supplies
performance. To help eliminate these problems, the VCC pin should be bypassed to ground with a low ESR ceramic bypass
capacitor with B dielectric. Care should be taken to minimize the loop area formed by the bypass capacitor connections, the
VCC pin, and the anode of the catch diode. See Fig.28 for a PCB layout example. The GND pin should be tied directly to
the thermal pad under the IC and the thermal pad.
The thermal pad should be connected to any internal PCB ground planes using multiple VIAs directl y under the IC. The LX
pin should be routed to the cathode of the catch diode and to the output inductor. Since the LX connection is the switching
node, the catch diode and output inductor should be located close to the LX pins, and the area of the PCB conductor
minimized to prevent excessive capacitive coupling. For operation at full rated load, the top side ground area must provide
adequate heat dissipating area. The additional external components can be placed approximately as shown. It may be
possible to obtain acceptable performance with alternate PCB layouts; however this layout has be en shown to produce
good results and is meant as a guideline.

Compensation

Network

VOUT

Output

Inductor

Resistor

Divider

Output

Capacitor

Catch
Diode

LX

GND

VC

FB

Fig.29 Evaluation Board Pattern

VCC

BST

EN

SYNC

Topside
Ground

rea

Input Bypass
Capacito

CBST

Signal VI
Thermal VIA

Technical Note

VCC

Route BST Capacito
Trace on another layer to

provide with wide path for
topside ground

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10/18

2012.02 - Rev.C

BD9673EFJ

● Power Dissipation

It is shown below reducing characteristics of power dissipation to mount 70mm×70mm×1.6mmt PCB

Junction temperature must be designed not to exceed 150℃.

●Power Dissipation Estimate

4000

④3760mW

3500

3000

HTSOP-J8 Package ­On 70mm×70mm×1.6mm
①1-layer board （Backside copper foil area0mm×0mm）
②2-layer board ( Backside copper foilarea 15mm×15mm)
③2-layer board （Backside copper foil area70mm×70mm）
④4-layer board （Backside copper foil area 70mm×70mm）

t

glass epoxy PCB

2500

③2210mW

2000

1500

1000

POWER DISSIP A TION - mW

②1100mW

①820mW

500

0

0 25 50 75 100 125 150

Ambient Temperature -℃

t

Fig.30 Power Dissipation ( 70mm×70mm×1.6mm

The following formulas show how to estimate the device power dissipation under continuous mode operations. They should
not be used if the device is working in the discontinuous conduction mode.
The device power dissipation includes:

1) Conduction loss： Pcon = IOUT

2) Switching loss: Psw = 1.25 × 10

3) Gate charge loss： Pgc = 22.8 × 10

4) Quiescent current loss： Pq = 1.0 × 10–3 × VCC

Where:
IOUT is the output current (A）, RonH is the on-resistance of the high-side MOSFET（Ω）, VOUT is the output voltage (V).
VCC is the input voltage (V), fsw is the switching frequency (Hz).
Therefore
Power dissipation of IC is the sum of above dissipation.
Pd = Pcon + Psw + Pgc + Pq
For given Tj, Tj =Ta + θja × Pd
Where:
Pd is the total device power dissipation (W), Ta is the ambient temperature (℃)
Tj is the junction temperature (℃), θja is the thermal resistance of the package (℃)

2

× RonH × VOUT/VCC

–9

× VCC2 × IOUT × fsw

–9

× fsw

1layer PCB)

Technical Note

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11/18

2012.02 - Rev.C

∆

R

+

BD9673EFJ

●Application Components Selection Method

(1) Inductor

Something of the shield Type that Fulfills the Current Rating (Current value Ipeak below), with low DCR (Direct Current
Resistance element) is recommended.
Value of Inductor influences Inductor Ripple Current and becomes the cause of Output Ripple.
In the same way as the formula below, this Ripple Current can be made small for as big as the L value of Coil or as
high as the Switching Frequency.

I

IL

(IL: Output Ripple Current, f: Switching Frequency)

For design value of Inductor Ripple Current, please carry out design tentatively with about 20%～50% of Maximum
Input Current.

※When current that exceeds Coil rating flows to the coil, the Coil causes a Magnetic Sat uration, and there are cases

wherein a decline in efficiency, oscillation of output happens. Please have sufficient margin and select so that Peak
Current does not exceed Rating Current of Coil.

(2) Output Capacitor

In order for capacitor to be used in output to reduce output ripple, Low ceramic capacitor of ESR is recommended.
Also, for capacitor rating, on top of putting into consideration DC Bias characteristics, please use something whose
maximum rating has sufficient margin with respect to the Output Voltage. Output ripple voltage is looked for using the
following formula. The actual value of the output capacitor is not critical, but some pr actical limits do exist. Consider th e
relationship between the crossover frequency of the design and LC corner frequency of the output filter. In gener al, it is
desirable to keep the crossover frequency at less than 1/5 of the switching frequency. With high switching frequenci es
such as the 600kHz frequency of this design, internal circuit limitations of the BD9675FJ limit the practical maximum
crossover frequency to about 30kHz. In general, the crossover freq uency should be higher than the corner frequency
determined by the load impedance and the output capacitor. This limits the minimum capacitor value for the output filter
to:

C

Where: Rl is the output load resistance and fc_max is the maximum crossover frequency. The output ripple voltage can
be estimated by:
.

Please design in a way that it is held within Capacity Ripple Voltage.

(3) Output Voltage Setting

ERROR AMP internal Standard Voltage is 1.0V. Output Voltage is determined as seen in (4) formula.

(4) Bootstrap Capacitor

Please connect from 4700pF to 22000pF (Laminate Ceramic Capacitor) between BST Pin and Lx Pin.

=∆

OUT

pp

IOUTIpeak

−

min_

ILV

VOUT

R1

R2

L

×∆=

IL

+=

・・・ (1)

2

VOUTVCC

=

π

1

××

π

2

FB

Fig. 33Voltage Return Resistance Setting Method

VOUT

××

1

fcRl

××

COUTf

ERROR AMP

VREF

1.0V

1

・・・ (2)

fVCC

・・・ (3)

max_2

・・・ (4)

RIL

×∆+

ESR

VOUT

Technical Note

ΔIL

Fig.32 Inductor Current

RR

21

=

・・・ (5)

2

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12/18

2012.02 - Rev.C

×

×

×

×

×

×

BD9673EFJ

(5) Catch Diode

The BD9673EFJ is designed to operate using an externa l catch diode between Lx and GND. T he selected diode must
meet the absolute maximum ratings for the application: Reverse voltage must be higher t han the maximum voltage at
the Lx pin, which is VCCMAX + 0.5 V. Peak current must be greater than IOUTMAX plus on half the peak to peak
inductor current.

(6) Input Capacitor

The BD9673EFJ requires an input capacitor and depending on the application. Use low ESR capacitors for the best
performance. Ceramic capacitors are preferred, but low-ESR electrolytic capacitors may also suffice. The typical
recommended value for the decoupling capacitor is 10uF. Please place this capacitor as possible as close to the VCC
pin. When using ceramic capacitors, make sure that they have enough capacitance to provide sufficient charge to
prevent excessive voltage ripple at input. The input voltage ripple caused by capacitance can be estimated by:

Since the input capacitor (CVCC) absorbs the input switching current it requires an adequate ripple current rating. The
RMS current in the input capacitor can be estimated by:

The worst case condition occurs at VCC = 2VOUT, where

(7) About Adjustment of DC/DC Comparator Frequency Characteristics

Role of Phase compensation element C1,C2,R3 (See P.7. Example of Reference Application Circuit)
Stability and Responsiveness of Loop are controlled through VC Pin which is the output of Error Amp.

The combination of zero and pole that determines Stability and Responsiveness is adjusted by the combination of
resistor and capacitor that are connected in series to the VC Pin.

DC Gain of Voltage Return Loop can be calculated for using the following formula.

Here, VFB is Feedback Voltage (1.0V).AEA is Voltage Gain of Error amplifier (typ: 77dB),
Gcs is the Trans-conductance of Current Detect (typ: 10A/V), and Rl is the Output Load Resistance value.

There are 2 important poles in the Control Loop of this DC/DC.
The first occurs with/ through the output resistance of Phase compensation Capacitor (C1) and Error amplifier.
The other one occurs with/through the Output Capacitor and Load Resistor.
These poles appear in the frequency written below.

Here, G
Here, in this Control Loop, one zero becomes important. With the zero which occurs because of Phase compensation

Capacitor C1 and Phase compensation Resistor R3, the Frequency below appears.

Also, if Output Capacitor is big, and that ESR (RESR) is big, in this Control Loop, there are cases when it has an
important, separate zero (ESR zero).
This ESR zero occurs due to ESR of Output Capacitor and Capacitance, and exists in the Frequency below.

(ESR zero)

VCC

CVCC

I

CVCC_max

is the trans-conductance of Error amplifier (typ: 220 µA/V).

EA

=∆

IOUTI

×

IOUT

=

fp2

fz

ESR

IOUT

CVCCf

2

=

1fp

=

1fz

=

=

VOUT

VCC

VOUT

VCC

・・・ (8)

×

=

G

×

π

×

π

×

π

×

π

1

EA

1

(1

1

−××=

⎡

××

-1

⎢
⎣

VOUT

VCC

AGCSRlAdc

EA

AC12

EA

RlCOUT2

R3C12

RESRCOUT2

VOUT

VCC

)

V

VOUT

・・・ (10)

・・・ (11)

・・・ (12)

・・・ (13)

⎤

・・・ (6)

⎥
⎦

・・・ (7)

FB

・・・ (9)

Technical Note

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13/18

2012.02 - Rev.C

×

×××

BD9673EFJ

In this case, the 3rd pole determined with the 2nd Phase compensation Capacitor (C2) and Phase Correction Resistor
(R3) is used in order to correct the ESR zero results in Loop Gain.
This pole exists in the frequency shown below.

(Pole that corrects ESR zero)
The target of Phase compensation design is to create a communication function in order to acquire necessary band

and Phase margin.
Cross-over Frequency (band) at which Loop gain of Return Loop becomes “0” is important.

When Cross-over Frequency becomes low, Power supply Fluctuation Response, Load Response, etc worsens.
On the other hand, when Cross-over Frequency is too high, instability of the Loop can occur.
Tentatively, Cross-over Frequency is targeted to be made 1/20 or below of Switching Frequency.

Selection method of Phase Compensation constant is shown below.

1. Phase Compensation Resistor (R3) is selected in order to set to the desired Cross-over Frequency.

Calculation of RC is done using the formula below.

Here, fc is the desired Cross-over Frequency. It is made about 1/20 and below of the Normal Sw itching Frequency (fs).

2. Phase compensation Capacitor (C1) is selected in order to achieve the desired phase margin.

In an application that has a representative Inductance value (about several µH～20µH), by matching zero of
compensation to 1/4 and below of the Cross-over Frequency, sufficient Phase margin can be acquired. C1 can be

calculated using the following formula.

RC is Phase compensation Resistor.

3. Examination whether the second Phase compensation Capacitor C2 is necessary or not is done.

If the ESR zero of Output Capacitor exists in a place that is smaller than half of the Switching Frequency, a second
Phase compensation Capacitor is necessary. In other words, it is the case wherein the formula below happens.

In this case, add the second Phase compensation Capacitor C2, and match the frequency of the third pole to the
Frequency fp3 of ESR zero.

3fp

=

R3

×

π

×

π

=

R3C22

GCSGEA

4

1

C1

＞

π

××

fcR32

・・・ (16)

1

＜

××

π

C2 is looked for using the following formula.

C2

=

RESRCOUT2

×

RESRCOUT

R3

・・・ (14)

fcCOUT2

VOUT

fs

・・・ (17)

2

・・・ (18)

Technical Note

・・・ (15)

VFB

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14/18

2012.02 - Rev.C

BD9673EFJ

●I/O Equivalent Schematic

Pin.

No

Pin.

Name

1
2
7
8

Lx

GND

BST

VCC

BST

VCC

GND

Pin Equivalent Schematic

Lx

Pin.

No

5 SYNC

Pin.

Name

Technical Note

Pin Equivalent Schematic

SYNC

GND

3 VC

4 FB

VCC

VC

GND

GND

FB

EN

6 EN

GND

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15/18

2012.02 - Rev.C

BD9673EFJ

●Notes for use

(1) About Absolute Maximum Rating

When the absolute maximum ratings of application voltage, operating temperature range, etc. was exceeded, there is
possibility of deterioration and destruction. Also, the short Mode or open mode, etc. destruction condition cannot be
assumed. When the special mode where absolute maximum rating is exceeded is assumed, pleas e give consideration
to the physical safety countermeasure for the fuse, etc.

(2) About GND Electric Potential

In every state, please make the electr ic pot en tia l of GND Pi n into the minimum electrical potenti al. Also, i nclud e t he act u a l
excessive effect, and please do it such that the pins, excluding the GND Pin do not become the voltage below GND.

(3) About Heat Design

Consider the Power Dissipation (Pd) in actual state of use, and please make Heat Design with sufficient margin.

(4) About short circuit between pins and erroneous mounting

When installing to set board, please be mindful of the direction of the IC, phase difference, etc. If it is not installed
correctly, there is a chance that the IC will be destroyed. Also, if a foreign object enters the middle of output, the middle
of output and power supply GND, etc., even for the case where it is shorted, there is a change of destruction.

(5) About the operation inside a strong electro-magnetic field

When using inside a strong electro-magnetic field, there is a possibility of error, so please be careful.

(6) Temperature Protect Circuit (TSD Circuit)

Temperature Protect Circuit (TSD Circuit) is built-in in this IC. As for the Tem perature Protect Circuit (TSD Circuit),
because it a circuit that aims to block the IC from insistent careless runs, it is not aimed for protection and guarantee of
IC. Therefore, please do not assume the continuing use after operation of this circuit and the Temperature Protect
Circuit operation.

(7) About checking with Set boards

When doing examination with the set board, during connection of capacitor to the pin that has lo w impedance, there is
a possibility of stress in the IC, so for every 1 process, please make sure to do electric discharge. As a countermeasure
for static electricity, in the process of assembly, do grounding, and when transporting or storing please be careful. Also,
when doing connection to the jig in the examination process, please make sure to turn off the power supply, then
connect. After that, turn off the power supply then take it off.

(8) About common impedance

For the power supply and the wire of GND, lower the common impedance, then, as much as possible, make the ripple
smaller (as much as possible make the wire thick and short, and lower the ripple from L・C), etc., then and please
consider it sufficiently.

(9) In the application, when the mode where the VCC and each pin electrical potenti al becomes reversed exists, there is a

possibility that the internal circuit will become damaged. For example, during cases wherein the condition when charge
was given in the external capacitor, and the VCC was shorted to GND, it is recommended to insert the bypass diode
to the diode of the back current prevention in the VCC series or the middle of each Pin-VCC.

(10) About High-sid e Nch F ET

Please use within 2.0A contained ripple current, because the absolute maximum rating of high-side Nch FET is 2.0A.

(11) About over curr ent detection

The detecting current is the current flowing through high-side NchFET. Output current containing ripple current,
therefore the detecting current is the current of the output current containing ripple current

.

Technical Note

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16/18

2012.02 - Rev.C

BD9673EFJ

(12) About IC Pin Input

This IC is a Monolithic IC, and between each element, it has P+ isolation for element separation and P board. With the
N layer of each element and this, the P-N junction is formed, and the parasitic element of each type is composed.
For example, like the diagram below, when resistor and transistor is connected to Pin,

○When GND＞(PinA) in Resistor, when GND＞(PinA), when GND＞(Pin B) in Transistor (NPN),

the P-N junction will operate as a parasitic diode.

○Also, during GND＞(Pin B) in the Transistor (NPN), through the N layer of the other elements connected

to the above-mentioned parasitic diode , the parasitic NPN Transistor will operation.
On the composition of IC, depending on the electrical potential, the parasitic element will become necessary. Through
the operation of the parasitic element interference of circuit operation will arouse, and error, therefore destruction can
be caused. Therefore please be careful about the applying of voltage lower than the GND (P board) in I/O Pin, and the
way of using when parasitic element operating.

(Pin A)

N

P Substrate

Technical Note

Resistor

(Pin B)

+

P

N

Parasitic
Element

P+

P

N

N

Parasitic Element

Fig.33 Example of simple structure of Bipolar IC

Transistor (NPN)

C

+

P

B

N

N

～

～

E

P

P Substrate

GND

GND

+

P

N

(Pin A)

GND

～

～

Parasitic
Element

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© 2012 ROHM Co., Ltd. All rights reserved.

17/18

2012.02 - Rev.C

BD9673EFJ

●Ordering part number

B D 9 6 7 3 E F J - E 2

Technical Note

Part No. Part No. Package

HTSOP-J8

6.0±0.2

1.0MAX

4.9±0.1

(MAX 5.25 include BURR)

(3.2)

7

568

3.9±0.1

1

234

0.545

1.27

0.85±0.05

0.08±0.08

(2.4)

1PIN MARK

+0.05

0.42

-

0.04

0.08 S

+

6

°

4

°

−4°

1.05±0.2

0.65±0.15

+0.05

0.17

-

0.08

0.03

M

S

(Unit : mm)

<Tape and Reel information>

EFJ : HTSOP-J8

Embossed carrier tapeTape

Quantity

Direction
of feed

2500pcs
E2

The direction is the 1pin of product is at the upper left when you hold

()

reel on the left hand and you pull out the tape on the right hand

Reel

Packaging and forming specification
E2: Embossed tape and reel

1pin

Order quantity needs to be multiple of the minimum quantity.

∗

Direction of feed

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18/18

2012.02 - Rev.C

Notes

No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.

The content specied herein is subject to change for improvement without notice.

The content specied herein is for the purpose of introducing ROHM's products (hereinafter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.

The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other parties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.

The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, commu­nication devices, electronic appliances and amusement devices).

The Products specied in this document are not designed to be radiation tolerant.

While ROHM always makes efforts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injury (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller, fuel­controller or other safety device). ROHM shall bear no responsibility in any way for use of any
of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology specied herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.

Notice

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Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.

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