Switching Regulator
with MOSFET for DDR-SDRAM Cores
BD95500MUV
●Description
BD95500MUV is a switching regulator with high output current (up to 6A) which can achieve low output voltage
(0.7V to 5.0V) from a wide input voltage range (3V to 20V). High efficiency for the switching regulator can be realized by
utilizing an internal N-MOSFET power transistor. A new technology called H
realize ultra high transient response against load change. SLLM (Simple Light Load Mode) technology is also integrated to
improve efficiency in light load mode, providing high efficiency over a wide load range. For protection and ease of use, the
soft start function, variable frequency function, short circuit protection function with timer latch, over voltage protection
function, and power good function are all built in. This switching regulator is specially designed for sets of various kinds.
●Features
1) Integrated low ON resistance N-MOSFET (TYP. 50mΩ)
4) Thermal Shut Down (TSD), Under Voltage LockOut (UVLO), Adjustable Over Current Protection (OCP),
Over Voltage Protection (OVP), Short Circuit Protection(SCP) built-in
5) Soft start function to minimize rush current during startup
6) Adjustable switching frequency (f=200KHz~1000KHz)
7) Built-in output discharge function
8) VQFN040V6060 Package
9) Tracking Function
10) Integrated boot strap diode
11) Power Good function
●Applications
Mobile PC, Desktop PC, LCD-TV, Digital Components, etc
Power Dissipation 4 Pd4 4.66 *5 W
Operating Temperature Range Topr -10~+100 ℃
Storage Temperature Range Tstg -55~+150 ℃
Junction Temperature Tjmax +150 ℃
*1 Not to exceed Pd, ASO, and Tjmax=150℃.
*2 Reduced by 4.3mW for each increase in Ta of 1℃ over 25℃ (when don’t mounted on a heat radiation board )
*3 Reduced by 8.0mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 70.0mm×70mm×1.6mm Glass-epoxy PCB which has 1 layer.
(Copper foil area : 0mm
*4 Reduced by 30.1mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 70.0mm×70mm×1.6mm Glass-epoxy PCB which has 4 layers.
st
(1
and 4th copper foil area : 20.2mm2, 2nd and 3rd copper foil area : 5505mm2))
*5 Reduced by 37.3mW for increase in Ta of 1℃ over 25℃. (when mounted on a board 70.0mm×70mm×1.6mm Glass-epoxy PCB which has 4 layers.
(All copper foil area : 5505mm
2
))
2
))
●Operating Conditions (Ta=25℃)
Parameter
Symbol
MIN MAX
Ratings
Unit
Input Voltage 1 VCC 4.5 5.5 V
Input Voltage 2 VDD 4.5 5.5 V
Input Voltage 3 VIN 3.0 20 V
BOOT Voltage BOOT 4.5 25 V
SW Voltage SW -0.7 20 V
BOOT-SW Voltage BOOT-SW 4.5 5.5 V
MODE Input Voltage MODE 0 5.5 V
EN Input Voltage EN 0 5.5 V
Output Adjustable Voltage REF 0.7 2.0 V
Is Input Voltage Is+/Is- 0.7 2.7 V
MIN ON Time Tonmin - 200 nsec
*This product should not be used in a radioactive environment.
VCC Bias Current Icc - 1200 2000 μA
VIN Bias Current Iin - 100 200 μA
VCC Standby Current Iccstb - 0 10 μA EN=0V
VIN Standby Current Iinstb - 0 10 μA EN=0V
EN Low Voltage Enlow GND - 0.8 V
EN High Voltage Enhigh 2.3 - 5.5 V
EN Bias Current Ien - 7 10 μA
VREG Voltage Vreg 2.475 2.500 2.525 V
[Under Voltage Locked Out ]
VCC Threshold Voltage Vcc_UVLO 4.1 4.3 4.5 V VCC:Sweep up
VCC Hysteresis Voltage dVcc_UVLO100 160 220 mV VCC:Sweep down
VIN Threshold Voltage Vin_UVLO 2.4 2.6 2.8 V VIN:Sweep up
VIN Hysteresis dVin_UVLO100 160 220 mV VIN:Sweep down
VREG Threshold Voltage Vreg_UVLO2.0 2.2 2.4 V VREG:Sweep up
VREG Hysteresis Voltage dVreg_UVLO100 160 220 mV VREG:Sweep down
[H3REGTM Control Block]
ON Time Ton 400 500 600 nsec
MAX ON Time Tonmax - 3 6.0 μsec
MIN OFF Time Toffmin - 450 550 nsec
[FET Block]
High Side ON Resistance HGhon - 50 80 mΩ
Low Side ON Resistance HGlon - 50 80 mΩ
[SCP Block]
SCP Start up Voltage Vscp REF×0.60 REF×0.70 REF×0.80 V
Delay Time Tscp - 1.0 2.0 ms
[OVP Block]
OVP Detect Voltage Vovp REF×1.16REF×1.2REF×1.24 V
[Soft Start Block]
Charge Current Iss 2 4 6 μA
Discharge Current Idis 0.5 1.0 2.0 μA
Standby Voltage Vss_stb - - 50 mV
[Over Current Protection Block]
Current Limit Threshold 1 Ilim1 40 50 60 mV
Current Limit Threshold2 Ilim2 160 200 240 mV ILIM=2.0V
[Vout Setting]
VOUT Offset Voltage 1 Voutoff1 REF-10mREF REF+10mV Ta=-10℃ to 100℃
VOUT Bias Current Ivout -100 0 100 nA
REF Bias Current Iref -100 0 100 nA
Is+ Input Current IIs+ -1 0 1 μA Is+=1.8V
Is- Input Current IIs- -1 0 1 μA Is-=1.8V
This is the power supply pin for IC internal circuits, except the FET driver. The input supply voltage range is 4.5V to 5.5V.
It is recommended that a 10Ω/0.1uF C-R filter be put in this pin from VDD rail.
・EN (39 Pin)
When EN pin voltage is at least 2.3V, the status of this switching regulator becomes active. Conversely, the status
switches off when EN pin voltage goes lower than 0.8V and circuit current becomes 0µA.
・VDD (14 Pin)
This is the power supply pin to drive the LOW side FET and for Boot-strap diode. It is recommended that a 1~10µF
bypass capacitor be established to compensate for rush current during the FET ON/OFF transition.
・VREG (7 Pin)
This is the reference voltage output pin. The voltage is 2.5V, with 500uA current ability. It is recommended that a
0.22~1µF capacitor (X5R or X7R) be established between VREG and GND (6 Pin). When REF is not adjusted from the
external voltage supply, the REF voltage can be adjusted using the external resistor divider of VREG.
・REF (10 Pin)
This is the output voltage adjustment pin by resistor divider network from VREG pin (0.7~2.0V). It is also very
convenient for synchronizing external voltage supply. The IC controls the output voltage (REF≒VOUT).
・ILIM (4 Pin)
BD95500MUV detects the voltage between Is+ pin and Is- pin and limits the output current (OCP). Voltage equivalent to
1/10 of the ILIM voltage is the voltage drop of external current sense resistor. A very low current sense resistor or
inductor DCR can also be used for this platform.
・SS/TRACK (9 Pin)
This is the adjustment pin to set the soft start time. SS voltage is low during standby status. When EN is ON, the soft
start time can be determined by the SS charge current and capacitor between SS-GND. Until SS reaches REF voltage,
the output voltage is equivalent to SS voltage. And also this pin enables to operate tracking function. The output voltage
keeps track of a power supply rail by connecting 10kΩ resistance between the power supply rail and SS/TRACK pin.
・VINS (37 Pin)
The duty cycle is determined by input voltage and controls output voltage. In other words, the output voltage is affected
by input voltage. Therefore, when VINS voltage fluctuates, the output voltage becomes also unstable. Since the VINS
line is also the input voltage of the switching regulator, stability depends on the impedance of the voltage supply. It is
recommended to establish a bypass capacitor or CR filter suitable for the actual application.
・FS (8 Pin)
This is the pin to adjust the switching frequency with the resistor. It is recommended that a resistor be established to
GND (6 pin).The frequency range is from 200kHz to 1000kHz.
・Is+ (13 pin), Is- (12 pin)
These pins are connected to both sides of the current sense resistor to detect output current. The voltage drop between
Is+ and Is- is compared with the voltage equivalent to 1/10 of ILIM voltage. When this voltage drop hits the specified
voltage level, the output voltage is OFF. Since the maximum input voltage is 2.7V, set the output voltage by the
resistance division value in case the output voltage is 2.7V or more.
・BOOT (38 pin)
This is the voltage supply to drive the high side FET and a Diode for BOOT strap function is built in. The maximum
absolute ratings are 30V (from GND) and 7V (from SW). BOOT voltage swings between (VIN+Vcc) and Vcc during
active operation.
・PGOOD (1 pin)
This pin is output pin for Power Good. It is open drain pin and recommended to connect to other power supply through
the pull-up resistance (about 100kΩ).
・CE (3 pin)
This pin is for the ceramic capacitor. It is useful to utilize low ESR capacitor for output capacitor.
・MODE (40 pin)
This is the control mode changeable pin. The status is Low : continuous mode, the status is High : SLLM
・VOUT (11 pin)
This is the monitor pin for output voltage. This IC controls the voltage in the status of REF≒VOUT. When output voltage
is required 2V or more, set the output voltage by the resistance division value.
・SW (22-29 pin)
This is connected pin for coil. SW voltage swings between VIN and GND. It is recommended to connect by heavy and
short pattern to coil.
・VIN (31-36 pin)
This is input power supply pin. Recommend input voltage is 3.3V to 20V. Connect the input capacitor against PGND
directly.
・PGND (15-21, 30 pin)
This is power ground pin. It is recommended to connect by heavy and short pattern. Connect in reverse side of IC when
connecting to GND (6 pin).
The BD95500MUV is a switching regulator controller incorporating ROHM’s proprietary H
system. When V
OUT drops due to a rapid load change, the system quickly restores VOUT by extending the tON time interval.
3
RegTM CONTROLLA control
Thus, it serves to improve the regulator’s transient response. Activating the Light Load Mode will also exercise Simple Light
Load Mode (SLLM) control when the load is light, to further increase efficiency.
H3RegTM control
(Normal operation)
VOUT
REF
When V
OUT falls to a threshold voltage (REF), the drop is
detected, activating the H
3
RegTM CONTROLLA system.
HG
TON=
REF
VIN
×
1
f
[sec]・・・(1)
LG
HG output is determined by the formula above.
OUT drops due to a rapid load change)
(V
VOUT
REF
Io
tON+α
When VOUT drops due to a rapid load change, and the
voltage remains below V
REF after the programmed tON
time interval has elapsed, the system quickly restores
OUT by extending the tON time, improving the transient
Spontaneous Discharge
(It is determined by load and output
capacitor)
Technical Note
Soft start is exercised with the EN pin set high. Current
control takes effect at startup, enabling a moderate
output voltage “ramping start.” Soft start timing and
incoming current are calculated with formulas (2) and (3)
below.
Soft start time
REF×Css
Tss=
4μA(typ)
Rush current
I
IN (ON)=
Co×VOUT
(Css: Soft start capacitor; Co: Output capacitor)
Soft stop is exercised with the EN pin set low. Current
control takes effect at startup, enabling a moderate
output voltage. Soft start timing and incoming current are
calculated with formulas (4) below.
Soft stop time
T
SS (OFF) =
ΔV
SS= 1.2[V] (typ)
=
Tdelay
1μA(typ)
When output voltage (Is-) falls to REF×0.7 or less, SCP
comparator inside IC is exercised.
If the status of High is continued 1ms or more
(programmed time inside IC), the IC goes OFF. It can be
restored either by reconnecting the EN pin or disabling
UVLO.
When output rise to or above REF×1.2, output ove
voltage protection is exercised, and low side FET goes
up maximum for reducing output. (LG=High, HG=Low).
When output falls, it returns to the standard mode.
During the normal operation, when VOUT becomes less
than REF Voltage, HG becomes High during the time t
(P9). However, when inductor current exceeds I
threshold, HG becomes OFF.
fter MAX ON TIME, HG becomes ON again if the output
voltage is lower than the specific voltage level and I
lower than I
LIMIT
level.
These power supply sequences are realized to connect
SS pin to other power supply output through the
resistance (10kΩ).
The inductor value is a major influence on the output ripple current.
s formula (5) below indicates, the greater the inductor or the
switching frequency, the lower the ripple current.
ΔI
L=
IN-VOUT)×VOUT
L×VIN×f
・・・(4)
(V
The proper output ripple current setting is about 30% of maximum
output current.
L=0.3×IOUTmax. [A]・・・(5)
ΔI
(VIN-VOUT)×VOUT
L=
L: output ripple current; f: switch frequency)
(ΔI
L×VIN×f
・・・(6)
※Passing a current larger than the inductor’s rated current will cause magnetic saturation in the inductor and decrease
system efficiency. In selecting the inductor, be sure to allow enough margin to assure that peak current does not exceed
the inductor rated current value.
※To minimize possible inductor damage and maximize efficiency, choose a inductor with a low (DCR, ACR) resistance.
L
) Selection
O
ESR
ESL
Co
VOUT
When determining the proper output capacitor, be sure to factor in the equivalent
series resistance and equivalent series inductance required to set the output ripple
voltage 20mV or more.
In selecting the limit of inductor, be sure to allow enough margin for output voltage.
Output ripple voltage is determined as in formula (7) below.
ΔVOUT=ΔIL×ESR + ESL×ΔIL / TON・・・(7)
L: Output ripple current; ESR: CO equivalent series resistance,
(ΔI
ESL: equivalent series inductance)
2. Output Capacitor (C
VIN
HG
SW
LG
PGND
Output Capacitor
Please give due consideration to the conditions in formula (8) below for output capacity, bear in mind that output rise time
must be established within the soft start time frame.
Co≦
TSS×(Limit-I
V
OUT
OUT)
・・・(8)
Tss: Soft start time (See formula (2) in P10)
Limit: Over current detection (See formula (10)(11) in P13)
Note: Improper capacitor may cause startup malfunctions
3. Input Capacitor (Cin) Selection
HG
LG
VIN
SW
Cin
VOUT
L
Co
PGND
Input Capacitor
The input capacitor selected must have low enough ESR resistance to fully support
large ripple output, in order to prevent extreme over current. The formula for ripple
current IRMS is given in (9) below.
√
V
IN
IRMS=IOUT×
Where V
IN=2×VOUT, IRMS=
VIN-VOUT
VIN
I
OUT
・・・(9)
2
A low ESR capacitor is recommended to reduce ESR loss and maximize efficiency.
The over current protection function detects the output ripple current peak
value. This parameter (setting value) is determined as in formula (10)
below.
ILIM×0.1
VOUT
Co
ILMIT=
(V
When the over current protection is detected by DCR of coil L, this
parameter (setting value) is determined as in formula (11) below.
VOUT
Co
ILMIT=VILIM×0.1×
(RL=
(V
current becomes specific threshold, the gate voltage of the high side
MOSFET becomes low.
Since the peak voltage of the inductor ripple current is detected, this
operation can sense high current ripple operation caused by inductance
saturated rated current and lead to high reliable systems.
t
When the output voltage is 2.7V or more, use the resistance for setting
output voltage like left figure, for Is+ and Is-.
R
Co
VOUT
to the divided ratio.
I
(VILIM: ILIM voltage R: Detection resistance)
V
[A]・・・(10)
R
ILIM: ILIM voltage, R: Detection resistance)
r×C
[A]・・・(11)
L
L
)
r×C
ILIM:ILIM voltage, RL: the DCR value of coil)
s soon as the voltage drop between Is+ and Is- generated by the inductor
ccording to the setting value above, ILIMIT setting current is in proportion
The On Time (t
resistance value connected to FS pin.
But actually SW rising time and falling time come up
due to influence of the external MOSFET gate capacit
or switching speed and tON is increased.
The frequency is determined by the following formula
after tON, input current and the REF voltage are fixed.
F=
・・・(13)
V
Consequently, total frequency becomes lower than the
formula above.
ON is also influenced by Dead Time around the outpu
T
current 0A area in continuous mode.
This frequency becomes lower than setting frequency.
It is recommended to check the steady frequency in
large current area (at the point where the coil current
doesn’t back up).
It is available to synchronize setting the reference
voltage (REF) with outside supply voltage [V] by using
outside power supply voltage.
It is available to set the reference voltage (REF) by the
resistance division value from VREG in case it is no
set REF from an external power supply.
An excess in the absolute maximum ratings, such as supply voltage, temperature range of operating conditions, etc.,
can break down the devices, thus making impossible to identify breaking mode, such as a short circuit or an open circuit.
If any over rated values will expect to exceed the absolute maximum ratings, consider adding circuit protection devices,
such as fuses.
(2) Connecting the power supply connector backward
Connecting of the power supply in reverse polarity can damage IC. Take precautions when connecting the power supply
lines. An external direction diode can be added.
(3) Power supply lines
Design PCB layout pattern to provide low impedance GND and supply lines. To obtain a low noise ground and supply
line, separate the ground section and supply lines of the digital and analog blocks. Furthermore, for all power supply
terminals to ICs, connect a capacitor between the power supply and the GND terminal. When applying electrolytic
capacitors in the circuit, not that capacitance characteristic values are reduced at low temperatures.
(4) GND voltage
The potential of GND pin must be minimum potential in all operating conditions.
(5) Thermal design
Use a thermal design that allows for a sufficient margin in light of the power dissipation (Pd) in actual operating
conditions.
(6) Inter-pin shorts and mounting errors
Use caution when positioning the IC for mounting on printed circuit boards. The IC may be damaged if there is any
connection error or if pins are shorted together.
(7) Actions in strong electromagnetic field
Use caution when using the IC in the presence of a strong electromagnetic field as doing so may cause the IC to
malfunction.
(8) ASO
When using the IC, set the output transistor so that it does not exceed absolute maximum ratings or ASO.
(9) Thermal shutdown circuit
The IC incorporates a built-in thermal shutdown circuit (TSD circuit). The thermal shutdown circuit (TSD circuit) is
designed only to shut the IC off to prevent thermal runaway. It is not designed to protect the IC or guarantee its operation.
Do not continue to use the IC after operating this circuit or use the IC in an environment where the operation of this
circuit is assumed.
TSD ON Temp. [℃] (typ.) Hysteresis Temp. [℃] (typ.)
BD95500MUV 175 15
Technical Note
(10) Testing on application boards
When testing the IC on an application board, connecting a capacitor to a pin with low impedance subjects the IC to
stress. Always discharge capacitors after each process or step. Always turn the IC's power supply off before connecting
it to or removing it from a jig or fixture during the inspection process. Ground the IC during assembly steps as an
antistatic measure. Use similar precaution when transporting or storing the IC.
This monolithic IC contains P+ isolation and P substrate layers between adjacent elements in order to keep them
isolated. P-N junctions are formed at the intersection of these P layers with the N layers of other elements, creating a
parasitic diode or transistor. For example, the relation between each potential is as follows:
○When GND > Pin A and GND > Pin B, the P-N junction operates as a parasitic diode.
○When GND > Pin B, the P-N junction operates as a parasitic transistor.
Parasitic diodes can occur inevitable in the structure of the IC. The operation of parasitic diodes can result in mutual
interference among circuits, operational faults, or physical damage. Accordingly, methods by which parasitic diodes
operate, such as applying a voltage that is lower than the GND (P substrate) voltage to an input pin, should not be used.
Pin A
N
+
P
P
Parasitic element
GND
(12) Ground Wiring Pattern
When using both small signal and large current GND patterns, it is recommended to isolate the two ground patterns,
placing a single ground point at the ground potential of application so that the pattern wiring resistance and voltage
variations caused by large currents do not cause variations in the small signal ground voltage. Be careful not to change
the GND wiring pattern of any external components, either.
●Power Dissipation
VQFN040V6060
5.0
④4.66W
4.5
4.0
③3.77W
3.5
3.0
2.5
2.0
1.5
Power Dissipation: Pd [W]
1.0
0.5
②1.00W
①0.54W
0
0
25 50 75 100125150
IC unit time
θj-a=231.5℃/W
②1 layer (Substrate surface copper foil area : 0mm
θj-a=125.0℃/W
③4 layer (Substrate surface and bottom copper foil area : 20.2mm2
2nd and 3rd copper foil area : 5505mm2)
θj-a=33.2℃/W
④4 layer (all layers copper foil area : 5505mm2) θj-a=26.8℃/W
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which can be obtained from ROHM upon request.
Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.
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The technical information specied herein is intended only to show the typical functions of and
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Notice
The Products specied in this document are intended to be used with general-use electronic
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