ROHM BD9271KUT Schematics

t

Datashee

LED Drivers for LCD Backlights

White LED Diver for
Backlight of Medium/Large-sized LCDs

BD9271KUT

General Description

BD9271KUT is a white LED diver used on backlight of
Medium/Large-sized LCDs. This IC can achieve
dimming function by SPI control. And through the SPI
correspondence, it can set the ON/OFF of each switch,
analog dimming and etc. The signals of PWM dimming
can set the frequency, ON time and delay of PWM by
inputting the external signals to the register.

BD9271KUT has equipped several protection functions

to deal with the abnormal states, including LED OPEN
protection, LED SHORT protection, external current
setting resistance SHORT protection, external MOS
transistor SHORT protection, etc. So it can be used in a
wide output voltage range and various load conditions.

Key Specifications

■ VCC power supply range： 9.0V～35.0V

■ DVDD power supply range： 3.0V～3.6V

■ CLK frequency setting range： 100～10000kHz

■ Operating Circuit current range： 2.4mA(typ.)

■ Operating temperature range： -40℃～+85℃

Applications

TV, PC display

Other LCD backlight

Ty pical A pplication Circuit

Features

■ 16-ch constant current driver (external FET(NMOS）is

equipped.)

■ LED voltage can be set externally.

■ PWM dimming and Analogue dimming can be

controlled by SPI.

■ LED Abnormal operation detection circuit (OPEN

protection/ SHORT protection) is equipped.

■ LED SHORT protection detection voltage is adjustable

(LSP terminal)

■ LED SHORT protection detection CH

■ FAIL INDICATION function is equipped by ERR_DET

terminal.

■ 3 lines serial interface

■ Package: TQFP64U

Package W(Typ.) D(Typ.) H(Max.)

TQFP64U 9.00mm×9.00mm×1.20mm
Pin Pitch 0.4mm

Figure 1. TQFP64U

Figure 2. Typical Application Circuit

○Product structure：Silicon monolithic integrated circuit ○This product is not designed protection against radioactive rays
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Datasheet

BD9271KUT

Datasheet

Absolute Maximum Ratings

Power Supply Voltage

Power Supply Voltage at digital part

STB Terminal Voltage
D1～16 Terminal Voltage

ERR_DET Terminal Voltage
S1～S16, G1～G16, VREF5V, LSP,

COMP1, COMP2 Terminal Voltage
CS, CLK, DI, DO, VSYNC, HSYNC Terminal
Voltage

Power Dissipation

Operating Temperature Range

Storage temperature range

Junction temperature

（Ta =2 5℃）

Parameter Symbol Ratings Unit

VCC 36 V

DVDD 4.5 V

VSTB VCC V

VD1～VD16 40 V

VERR_DET VCC V

VS1～S16, VG1～VG16,VREF5V,VLSP,
VCOMP1,VCOMP2

7 V

VCS,VCLK,VDI,VDO,VVSYNC,VHSYNC 4.5 V

Pd 1.37

(Note 1)

W

Topr -40～+85 ℃

Tst g -5 5 ～+150 ℃

Tjmax 150 ℃

(Note 1)When Ta = 25°C or higher, power dissipation is down with 11.0mW/°C (when a 70 mm x 70 mm x 16 mm 1-layer
glass epoxy board is mounted).

Operation range（Ta= 25 ℃）

Parameter Symbol Limits Unit

Power source voltage VCC 9.0～35.0 V

Power Supply Voltage at digital part

CLK oscillation frequency setting range

DVDD 3.0～3.6 V

ｆCLK 100～10000 kHz

VSYNC input oscillation frequency range ｆVSYNC 80 ～ 1000 Hz

LSP terminal input voltage

VLSP 0.8 ～ 3.0 V

The operating ranges above are acquired by evaluating the IC separately. Please take care when set the IC in applications.

External Components Recommended Range

Parameter Symbol Range Unit

VCC pin connection capacitance CVCC 1～10 uF
VREF5V pin connection capacitance CREF 0.1～10 uF

The operating ranges above are acquired by evaluating the IC separately. Please take care when set the IC in applications.

Block diagram Package outline drawing

33

34

35

36

37

38

39

40

41

42

43

44

45

46

47

48

D12

D15

S15

S16

D16

G16

G14

G15

D13

G13

S14

D14

S12

S13

G11

G12

TQFP64U (TOP VIEW)

D1

S1

D2

S2G3D3

S3G4D4

9

10111213141516

2

3

G2

45678

G1

1

Figure 3. Pin Configuration Figure 4. Marking Diagram

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Marking

BD9271

S5

G6

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Datasheet

BD9271KUT

Electrical characteristics (unless otherwise specified, Ta = 25°C, VCC = 12V, STB=3V)

Item Symbol

【Whole device】

Operating circuit
current

Stand-by circuit
current

【VREF5V block】

VREF5V output
voltage

VREF5V Maximum
output current

【Error amplifier block】

COMP1,COMP2
terminal sink current

LED control voltage VLED 270 300 330 mV

【UVLO block】

Operation power
source voltage(VCC)

hysteresis voltage

（VCC）
【LED DRIVER block】

LED terminal current
accuracy

OPEN detection
voltage

SHORT detection
voltage

Upper resistance of
divided LSP terminal
resistance

Lower resistance of
divided LSP terminal
resistance

Error detection of
current detection
resistance

【STB block】

STB terminal HIGH
voltage

STB terminal LOW
voltage

STB terminal Pull
Down resistance

【FAIL block】

ERR_DET terminal
ON resistance

【LOGIC input (CS, CLK, DI, HSYNC, VSYNC)】

Input High voltage VINH

Input Low voltage VINL -0.3 -

Input inflow current IIN1 -5 0 5 µA VIN=3.3V

【LOGIC output (DO) 】

Output High voltage VOUTH

Icc － 2.4 5.0 mA LED1-16 OFF

IST － 200 500 μA STB=0V

VREF5 4.95 5.00 5.05 V IO=0mA

IREF5 15 － - mA

ICOMPSINK 300 - - µA VCOMP=0.5V

VUVLO_VCC 6.0 7.0 8.0 V VCC=SWEEP UP

VUHYS_VCC 150 300 600 mV VCC=SWEEP DOWN

⊿ILED

VOPEN 0.05 0.10 0.15 V VD=SWEEP DOWN

VSHORT 4.5 5.0 5.5 V VD=SWEEP UP

RupLSP 1000 - - kΩ LSP=0V

RdownLSP 250 - - kΩ LSP=5V

VRESSH 0.10 0.15 0.20 V LEDREF default

STBH 2.0 - VCC V

STBL -0.3 - 0.8 V

REN 600 1000 1800 kΩ VIN=3V( STB )

RFAIL 55 110 220 Ω IERR_DET=5mA

Minimum Standard Maximum

-1.5 - 1.5 % ILED=100mA

0.7×

DVDD

DVDD

-0.6

Standard value

-

DVDD

-0.3

Unit Condition

DVDD

+0.3

0.3×

DVDD

- V IOL=-1mA

V

V

Datasheet

Output Low voltage VOUTL - 0.19 0.60 V IOL=1mA

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Datasheet

BD9271KUT

Terminal No., Name, and Function

No. Terminal

G1

1

D1

2

S1

3

G2

4

D2

5

S2

6

G3

7

D3

8

S3

9

G4

10

D4

11

S4

12

G5

13

D5

14

S5

15

G6

16

Function

CH1 NMOS gate
terminal

CH1 NMOS drain
terminal

CH1 NMOS source
terminal

CH2 NMOS gate
terminal

CH2 NMOS drain
terminal

CH2 NMOS source
terminal

CH3 NMOS gate
terminal

CH3 NMOS drain
terminal

CH3 NMOS source
terminal

CH3 NMOS gate
terminal

CH4 NMOS drain
terminal

CH4 NMOS source
terminal

CH5 NMOS gate
terminal

CH5 NMOS drain
terminal

CH5 NMOS source
terminal

CH6 NMOS gate
terminal

No. Terminal

17

18

19

20

21

22

23

24

25

26

27

28

29

30

31

32

CH6 NMOS drain

D6

terminal

CH6 NMOS source

S6

terminal

CH7 NMOS gate

G7

terminal

CH7 NMOS drain

D7

terminal

CH7 NMOS source

S7

terminal

CH8 NMOS gate

G8

terminal

CH8 NMOS drain

D8

terminal

CH8 NMOS source

S8

terminal

CH9 NMOS source

S9

terminal

CH9 NMOS drain

D9

terminal

CH9 NMOS gate

G9

terminal

CH10 NMOS source

S10

terminal

CH10 NMOS drain

D10

terminal

CH10 NMOS gate

G10

terminal

CH11 NMOS source

S11

terminal

CH11 NMOS drain

D11

terminal

Function

No. Terminal

G11

33

S12

34

D12

35

G12

36

S13

37

D13

38

G13

39

S14

40

D14

41

G14

42

S15

43

D15

44

G15

45

S16

46

D16

47

G16

48

Function

CH11 NMOS gate
terminal

CH12 NMOS source
terminal

CH12 NMOS drain
terminal

CH12 NMOS gate
terminal

CH13 NMOS source
terminal

CH13 NMOS drain
terminal

CH13 NMOS gate
terminal

CH14 NMOS source
terminal

CH14 NMOS drain
terminal

CH14 NMOS gate
terminal

CH15 NMOS source
terminal

CH15 NMOS drain
terminal

CH15 NMOS gate
terminal

CH16 NMOS source
terminal

CH16 NMOS drain
terminal

CH16 NMOS gate
terminal

No. Terminal

VREF5V

49

LSP

50

VCC Power source terminal

51

STB

52

GND GND terminal

53

COMP2

54

COMP1

55

DGND Digital GND terminal

56

57 CS

58 CLK

59 DI

60 DO

VSYNC VSYNC signal terminal

61

HSYNC HSYNC signal terminal

62

ERR_DET

63

DVDD

64

5V regulator output terminal

SHORT detection setting
terminal

Enable terminal

ERROR AMP output
(CH9～16)

ERROR AMP output
(CH1～8)

Chip select terminal

Clock input terminal

DATE input terminal

DATE output terminal

Abnormal detection output
terminal

Digital Power source
terminal

Datasheet

Function

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BD9271KUT

Internal Equivalent Circuit Diagram

G1～G16 D1～D16 S1～S16

Datasheet

VREF5V

S1～S16

GND

10kΩ

GND

VREF5V LSP STB

VREF5V

2MΩ

500kΩ

LSP

GND

STB

GND

GND

1M

GND

COMP1, COMP2 CS, CLK, DI DO

CS,CLK,DI

DVDD

DVDD

DVDD

10kΩ

DVDD

50Ω

GND

500k

GND

DO

DGND

DGND

DGND

GND

VSYNC, HSYNC ERR_DET

Figure 5. Pin ESD Type

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BD9271KUT

Block Diagram

FPGA

VCC

GND

DVDD

DI

CLK

CS

DO

DGND

STB

VREF5V

REG

SPI I/F

register

VREF

Protect

logic

UVLO

UVLO

VREF5V

FB1

FB16

MS1

MS16

LED_ref

DAC

EAMP_ref

DAC

LSP

LED

OPEN

DET

RES

SHORT

DET

LED

SHORT

DET

MOS

SHORT

DET

DVDD

FB1

LED1_dr_moni

ERR_DET

LED16_dr_moni

PWM16

LED1_dr_moni

PWM1

PWM2

+

-

+

-

+

-

MS1

MS2

MS16

Datasheet

D1

G1

CH1

S1

D2

G2

CH2

S2

VSYNC

(ON timming)

HSYNC

(clock)

CONTROL

PWM
DUTY

PWM1
PWM16

FB1

FB8

FB9

FB16

+

+

-

+

+

-

COMP2

COMP1

FB2

FB16

LED2_dr_moni

LED16_dr_moni

D16

G16

S16

CH16

Figure 6. Block Diagram

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BD9271KUT

Typical Performance Curves

400

350

300

250

200

IST[uA]

150

100

50

0

9 131721252933

Figure 7. Stand-by Current (IST) [µA] vs. VCC[V]

5.5

5.4

5.3

5.2

5.1

5.0

VREF5V[V]

4.9

4.8

4.7

4.6

4.5

9 13172125 2933

VCC[V]

VCC[V]

Datasheet

5.0

4.5

4.0

3.5

3.0

2.5

Icc[mA]

2.0

1.5

1.0

0.5

0.0

9 131721252933

VCC[V]

Figure 8. Operating Current (Icc) [mA] vs. VCC[V]

(LED1-16 OFF)

Figure 9. VREF5V[V] vs. VCC[V]

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BD9271KUT

Pin Function Descriptions

G1-G16 （1,4,7,10,13,16,19,22,27,30,33,36,39,42,45,48PIN

External FET gate driving terminal of LED constant current driver, operating range : 0～5V.

（

S1-S16

D1-D16

3,6,9,12,15,18,21,24,25,28,31,34,37,40,43,46PIN

Connect to external FET’s source terminal of LED constant current driver. Through the operations of constant current
driver, all CHs of S1-S16 terminals are outputted the set voltages at addresses of 02h, 03h, and S1-S16 proceed the
constant current operation.
By monitoring the voltage of this terminal, the external resistance SHORT detection of each CH and external MOS
SHORT during Drain-Source detection proceed.
When Dimming＝HIGH, external resistance SHORT detection proceeds, and output the errors.
When Dimming＝LOW, external MOS Drain-Source SHORT detection proceeds, and output the errors.

The detection voltage of Sx pin for RESSHORT, MOSSHORT protection corresponds to the register value of 02h, 03h
LEDREF (the normal operation voltage of Sx pin). Please refer to the condition of protections.

LEDREF[11:0] Abnormal detection

voltage
000h - 0CDh 0.05V 0.1V
800h - FFFh 0.50V 1.0V

266h(default) 0.15V 0.3V

（

2,5,8,11,14,17,20,23,26,29,32,35,38,41,44,47PIN）

At output terminal of LED constant current driver, drain of external FET is connected. By monitoring the voltage of this
terminal, LED OPEN detection and LED SHORT detection of each terminal proceed.
When Dimming＝HIGH, if LED is in SHORT mode or OPEN mode, error signals are outputted.

LED OPEN protection detected voltage ・・・0.1V(typ.)
LED SHORT protection detected voltage・・・5.0V(typ.)・・・(It can be changed by setting the LSP terminal. Details are
given in LSP Pin Description.)

When Dimming ＝ LOW, the abnormal state when Dimming ＝ HIGH just before continues. In other words, when
Dimming=HIGH and the abnormal state is detected, the error signal is still outputted even turned to Dimming＝LOW.
To prevent the mistake of detection caused by the time change of state, abnormal detection mask can be set at address

of 04h.

）

）

Normal operation

voltage

Datasheet

At D1～16 pin
① LED OPEN detection（when PWM=H）
② LED SHORT detection（when PWM=H）

At S1～16 pin
③ RESISTOR SHORT detection（when PWM=H）
④ MOS SHORT detection（when PWM=L）

are detected, then the error signals are outputted.

VREF5V （49PIN）

The VREF5V pin is used to output power (5V) to the internal block of the IC and serves as a main power supply for the

internal circuit of the IC. Install a ceramic capacitor as close to this pin as possible in order to stabilize the power supply
voltage.

Figure 10. LED Protected operation

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BD9271KUT

g

LSP （50PIN）

A pin used for setting the LED SHORT protection detecting

voltage. When LSP pin is in OPEN state, the voltage in inward
of IC is 1V typ.（Set it in range of 0.8V~3.0V）

When LED is lighting, if the voltage of D1～16 pin is higher

than

「Voltage of LSP x 5 (V) 」（default 5V）
the abnormal state of IC is detected.
Because this pin has a high impedance, please connect a

capacitor about 1000pF to remove the noise basically.

SHORT

DET

Datasheet

REG

VREF5V

CLSP

R1

R2

2.0MΩ

ー

D1
D2
D3
D4

500kΩ

…

GND

＋
＋
＋
＋
＋

D16

LSP

GND GND

ure 11. LSP Pin Internal Equivalent Circuit Diagram

Fi

In case of outputting a voltage to LSP by using the resistor divider circuit, REF5V

VIN

LSP

AGND AGND

Figure 12. Setting for LSP

CLSP

R1

LSP

R2

AGND

20

15

10

5

BS x Pin LED short detec t voltage [V]

0

01234

LSP Pin voltage [V]

Figure 13. LED SHORT detect Voltage [V] vs. LSP [V]

（

VCC

51PIN）

The VCC pin is used to supply power for the IC in the range of 9 to 35V. If the VCC pin voltage reaches 7.0V (Typ.) or
more, the IC will initiate operation. If it reaches 6.7V (Typ.) or less, the IC will be shut down. Basically, insert a resistor of
approx. 10 ohms in resistance between the VCC pin and the external power supply and install a ceramic capacitor of
approx. 1uF in capacitance in the vicinity of the IC.

（

STB

52PIN）

The STB pin is used to make setting of turning ON and OFF the IC and allowed for use to reset the IC from shutdown.
Note: Set the STB pin voltage below the VCC pin voltage.
Note: The IC state is switched (i.e., the IC is switched between ON and OFF state) according to voltages input in the STB
pin. Avoid using the STB pin between two states (0.8 to 2.0V).

（

GND

53PIN）

The GND pin is an analog circuit ground pin of the IC. Set the ground pattern as close as possible to that of resistors
connected to the S1 to S16 pins.

COMP1(55PIN)

The COMP1 pin is used to feed back the state of voltage to the external power supply in order to optimize the power
supply voltage for the LED layer.
Positive feedback voltage is output to a pin having the lowest voltage out of the D1 to D8 pins. If the lowest voltage of the
D1 to D8 pins is higher than 0.6V typical voltage, the COMP1 pin will become open-circuited. If the lowest voltage of
these pins is lower than 0.6V typical voltage, the internal NPN transistor of the COMP1 pin will turn ON. The COMP1 pin
is intended to connect to the output voltage monitor pin of the DC/DC converter.

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BD9271KUT

COMP2(54PIN)

The COMP2 pin is used to feed back the state of voltage to the external power supply in order to optimize the power
supply voltage for the LED layer.
Positive feedback voltage is output to a pin having the lowest voltage out of the D9 to D16 pins. If the lowest voltage of
the D9 to D16 pins is higher than 0.6V typical voltage, the COMP2 pin will become open-circuited. If the lowest voltage of
these pins is lower than 0.6V typical voltage, the internal NPN transistor of the COMP2 pin will turn ON. The COMP2 pin
is intended to connect to the output voltage monitor pin of the DC/DC converter.

CS(57PIN), CLK(58PIN,)

These pins are used to control the IC with the CS, CLK, DI, and DO serial interfaces. Input levels are determined by the
DVDD power supply of the digital block. For data input format and timing, refer to the description of Logic block to be
hereinafter provided.

High-level input

Low-level input

VSYNC(61PIN), HSYNC(62PIN)

The VSYNC and HSYNC input signals enable the PWM light modulation signal to make setting of PWM frequency, PWM

ON time, and PWM delay time. For data input format and timing, refer to the description of Logic block to be hereinafter
provided.

ERR_DET(63PIN)

The ERR_DET pin is used to output an IC error detection signal and provides the N-MOS open-drain output function. If
this pin is pulled up to the DVDD voltage of the IC or else, it will be set to output High voltage for normal operation. If any
error is detected, the internal NMOS of the IC will be put into ON state, setting the pin to output Low voltage.

Normal operation OPEN

LED error detection GND Level

When the ERR_DET pin is put into the GND Level, the LED has already caused an error. In this case, reading the
registers located at addresses 05h to 0Ch makes it possible to recognize what channel is in what type of error state. (For

detail, refer to the description of registers to be hereinafter provided.)

DGND(56PIN)

The DGND pin is a digital circuit ground pin of the IC. Lay out the DGND pin using interconnect independent of that for
the GND pin wherever possible.

DVDD(64PIN)

The DVDD pin is used to input power in the digital block of the IC in the range of 3.0 to 3.6V. When the DVDD pin voltage
reaches 3.3V (typ.), the IC will start operating. Insert a ceramic capacitor of approx. 1uF in capacitance between the DVDD
and DGND pins in the vicinity of the IC.

DI(59PIN), DO(60PIN)

Input State Input Level

DVDD×0.7~ DVDD+0.3[V]

-0.3~DVDD×0.3 [V]

State FAIL Signal Output

Datasheet

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Datasheet

BD9271KUT

Functions of Logic Block

Serial interface block

This IC is controlled with the CS, CLK, DI, and DO serial interfaces.

The following section describes data input format and timing.

◆WRITE MODE

・To write 1 byte of data:

CS

CLK

DI

CSS

t

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16

DIS

t

DIH

t

CYC

t

A3A4A5A6

A2 A1 A0

CLKH

t

CLKL

t

W

DO

Figure 14. WRITE MODE (for 1byte)

Low

・Write consecutive 32 bytes of data:

CS

CLK

DI

DO

①

②

1 2 3 4 5 6 7 8 9 10111213141516

A3A4A5A6

A2 A1 A0

WD255

Low

17

18 19 20 21 22 23 24

③

D247

D246

D245

D244

D243

D242 D241 D240

④

Figure 15. WRITE MODE (for 32byte)

Low

Addresses are automatically counted up in increments of 1 address by 8 bits after the first set value.

D7 D6 D5 D4 D3 D2 D1 D0

D254 D253

257 258 259 260 261 262 263 264

D7

D252 D251 D250 D249

D6 D5

D4 D3 D2 D1

D248

Datasheet

CSH

t

①

②

③

④

D0

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BD9271KUT

◆READ MODE

CS

CLK

DI

CSS

t

1 2 3 4 5 6 7 8 9 10111213141516

DIS

t

DIH

t

DO

DO_EN

AC electrical characteristics:

CLK cycle tCYC 100 - - ns
CLK high level range tCLKH 35 - - ns
CLK low level range tCLKL 35 - - ns
DI input setup time tDIS 50 - - ns
DI input hold time tDIH 50 - - ns
CS input setup time tCSS 50 - - ns
CS input hold time tCSH 50 - - ns
DO output delay time tDOD - - 40 ns

Parameter Symbol

◆HSYNC, VSYNC

・VSYNC SETUP/HOLD time

AC electrical characteristics:

CYC

t

A3A4A5A6 A2 A1 A0 R

Low

Figure 16. READ MODE

Figure 16-2. HSYNC VSYNC timing

HSYNC

VSYNC

t

VSYNCS

Figure 16-3. VSYNC SETUP/HOLD time

t

CLKH

CLKL

t

********

DOD

t

D7 D6 D5 D4 D3 D2 D1 D0

Rating

Min. Typ. Max.

(Output load capacitance: 15pF)

t

VSYNCH

CSH

t

Unit

Datasheet

Parameter Symbol

HSYNC cycle tHSYNCCYC 244 - - ns
HSYNC high level range tHSYNCCKH 122 - - ns
HSYNC low level range tHSYNCCKL 122 - - ns
VSYNC cycle tVSYNCCYC 1000 - - us
VSYNC setup time tVSYNCS 20 - - ns
VSYNC hold time tVSYNCH 20 - - ns

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TSZ22111・ 15・001

Rating

Min. Typ. Max

(Output load capacitance: 15pF)

12/34

Unit

TSZ02201-0F1F0C100260-1-2

22.Jul.2015 Rev.006