ROHM BD9011EKN, BD9011KV, BD9775FV Technical data

Large Current External FET Controller Type Switching Regulator

Dual-output, high voltage,
high-efficiency step-down
Switching Regulator
(Controller type)

BD9011EKN , BD9011KV , BD9775FV

●Overview

The BD9011EKN/KV is a 2-ch synchronous controller with rectification switching for enhanced power management efficiency.
It supports a wide input range, enabling low power consumption ecodesign for an array of electronics.

●Features

1) Wide input voltage range: 3.9V to 30V

2) Precision voltage references: 0.8V±1%

3) FET direct drive

4) Rectification switching for increased efficiency

5) Variable frequency: 250k to 550kHz (external synchronization to 550kHz)

6) Built-in selected OFF latch and auto remove over current protection

7) Built-in independent power up/power down sequencing control

8) Make various application , step-down , step-up and step-up-down

9) Small footprint packages: HQFN36V, VQFP48C

●Applications
Car audio and navigation systems, CRTTV，LCDTV，PDPTV，STB，DVD，and PC systems，portable CD and DVD players,
etc.

●Absolute Maximum Ratings (Ta=25℃)

TECHNICAL NOTE

Parameter Symbol

EXTVCC Voltage EXTVCC 34 *1 V COMP1,2 Voltage COMP1,2

VCCCL1,2 Voltage VCCCL1,2 34 *1 V DET1,2 Voltage DET1,2

CL1,2 Voltage CL1,2 34 V RT､SYNC Voltage RT､SYNC

SW1,2 Voltage SW1,2 34 *1 V

BOOT1,2 Voltage BOOT1,2 40 *1 V

BOOT1,2-SW1,2

Voltage

STB, EN1,2 Voltage STB, EN1,2 VCC V

VREG5,5A

VREG33 VREG33 VREG5 V Storage temperature Tstg -55 to +150 ℃

SS1,2､FB1,2

*1 Regardless of the listed rating, do not exceed Pd in any circumstances.
*2 Mounted on a 70mm x 70mm x 0.8mm glass-epoxy board. De-rated at 7.44mW/℃（

above 25℃.

BOOT1,2-SW1,2 7

VREG5,5A 7 V

SS1,2､FB1,2

Rating Unit

*1

V

VREG5

V

Parameter Symbol

Power Dissipation

Operating

temperature

Junction temperature Tj +150 ℃

HQFN36V） or 8.8mW/℃（VQFP48C）

Pd

Topr

Rating Unit

VREG5 V

*2

0.875

（HQFN36V）

*2

1.1

（VQFP48C）

-40 to +105

W

W

℃

Apr.2008

●Operating conditions (Ta=25℃)

Parameter Symbol Min. Typ. Max. Unit

Input voltage 1 EXTVCC 3.9 *1 *2 12 30 V

Input voltage 2 VCC 3.9 *1 *2 12 30 V

BOOT－SW voltage BOOT－SW 4.5 5 VREG5 V

Carrier frequency OSC 250 300 550 kHz

Synchronous frequency SYNC OSC - 550 kHz

Synchronous pulse duty Duty 40 50 60 ％

Min OFF pulse TMIN - 100 - nsec

★This product is not designed to provide resistance against radiation.

*1 After more than 4.5V, voltage range.

*2 In case of using less than 6V, Short to VCC, EXTVCC and VREG5.

●Electrical characteristics (Unless otherwise specified, Ta=25℃

VCC=12V STB=5V EN1,2=5V)

Parameter Symbol

Min. Typ. Max.

Unit Conditions

VIN bias current IIN - 5 10 mA

Shutdown mode current IST - 0 10 μA VSTB=0V

［Error Amp Block］

Limit

Feedback reference voltage

Feedback reference voltage

(Ta=-40 to 105℃)

VOB 0.792 0.800 0.808 V

VOB+ 0.784 0.800 0.816 V Ta=-40 to 105℃ ※

Open circuit voltage gain Averr - 46 - dB

VO input bias current IVo+ - - 1 μA

［FET Driver Block］

HG high side ON resistance

HG low side ON resistance

LG high side ON resistance

LG low side ON resistance

HGhon - 1.5 - Ω

HGlon - 1.0 - Ω

LGhon - 1.5 - Ω

LGlon - 0.5 - Ω

［Oscillator］

Carrier frequency FOSC 270 300 330 kHz RT=100 kΩ

Synchronous frequency Fsync - 500 - kHz RT=100 kΩ,SYNC=500kHz

［Over Current Protection Block］

CL threshold voltage

CL threshold voltage

（Ta=-40 to 105℃）

Vswth 70 90 110 ｍV

Vswth+ 67 90 113 ｍV Ta=-40 to 105℃ ※

［VREG Block］

VREG5 output voltage VREG5 4.8 5 5.2 V IREF=6mA

VREG33 reference voltage VREG33 3.0 3.3 3.6 V IREG=6mA

VREG5 threshold voltage VREG_UVLO 2.6 2.8 3.0 V VREG:Sweep down

VREG5 hysteresis voltage DVREG_UVLO 50 100 200 mV VREG:Sweep up

［Soft start block］

Charge current

Charge current

(Ta=-40 to 105℃)

ISS 6.5 10 13.5 μA VSS=1V

ISS+ 6 10 14 μA VSS=1V,Ta=-40 to 105℃ ※

Note: Not all shipped products are subject to outgoing inspection.

2/28

●Reference data (Unless otherwise specified, Ta=25℃)

p

p

]

L

100

90

80

70

60

50

40

EFFICIENCY[%]

30

20

10

0

0123

2.6V 3.3V

1.8V

1.2V

OUT PUT CURRE NT：Io[A]

5.0V

VIN=12V

Fig.1 Efficiency 1

0.816

0.812

0.808

0.804

0.800

0.796

0.792

0.788

RE FER ENC E VOL TAG E ： VO B[V ]

0.784

-40 -15 10 35 60 85 110
AMBIENT TEMPERATURE ： Ta[℃]

100

90

80

70

60

50

40

EFFICIENCY[%]

30

20

10

3.3V

0

6 9 12 15 18 21 24

INPUT VOLTAGE ： V

Fig.2 Efficiency 2

110

100

90

80

70

過電流検出電圧 ： Vswth[ mV]

60

-40 -15 10 35 60 85 110
AMBIENT TEMPERATURE ： Ta[℃]

5.0V

Io=2A

[V]

IN

6

5

4

3

2

CIRC UIT　CURRENT [mA]

1

0

0102030

INPUT VOLTAGE：V

105℃

25℃

-40℃

[V]

IN

Fig.3 Circuit current

330

RT=100kΩ

320

[kHz]

OSC

310

300

290

280

OSILATING FREQUENCY ： F

270

-40 -15 10 35 60 85 110

AMBIENT TEMPERATURE ： Ta[℃]

Fig.4 Reference voltage vs.

temperature characteristics

5.25

5.00

4.75

4.50

4.25

4.00

3.75

3.50

OUTPUT VOLTAGE ： Vo [V]

3.25

3.00

-40 -15 10 35 60 85 110

VREG5

VREG33

AMBIENT TEMPERATURE ： Ta[℃]

Fig.7 Internal Reg vs.

tem

erature characteristics

6

5

4

3

2

1

OUTPU T　VOLTAGE ： Vo[V]

0

0246

105℃

25℃

-40℃

INPUT VOLTAGE：V

[V]

EN

Fig.5 Over current detection vs.

temperature characteristics

6

5

3.3V

5.0V

[V]

IN

4

3

2

OUTPUT VOLTAGE ： Vo [V]

1

0

0 5 10 15 20 25

INPUT VOLT AGE ： V

OUTPUT VOLTAGE ： Vo[V

Fig.6 Frequency vs.

tem

erature characteristics

3.0

2.5

RCL=15mΩ

2.0

1.5

1.0

0.5

0.0

LOFF=

0123456

OUTP UT CUR RENT: I o[A]

Fig.8 Line regulation Fig.9 Load regulation

50mV/div

VOUT VOUT

OUT

I

1A/div

I

OUT

LOFF= H

50mV/div

1A/div

Fig.10 EN threshold voltage Fig.11 Load transient response 1 Fig.12 Load transient response 2

3/28

●Block diagram (Parentheses indicate VQFP48C pin numbers)

SYNC

OSC

Slope

(GNDS)

(34)

(30)

16

3.3V Reg

5(19)

17(35)

LLM

33(8)

VCCCL1

34(10)

35(11)

36(12)

1(13)

4(17)

3(15)

2(14)

6(21)

8(23)

7(22)

CL1

BOOT1

OUTH1

SW1

VREG5A

OUTL1

DGND1

FB1

SS1

COMP1

PWM
COMP

Set

Reset

Set

Sequence DET

13

(29)

GND

Q

Reset

DRV

TSD

UVLO

Err Amp

Q

Reset

OCP

SW

LOGIC

(24)

DET1

0.8V

Set

0.56V

9

24(44)

VREG5

CL2

BOOT2

OUTH2

SW2

OUTL2

DGND2

FB2

SS2

31(5)

30(3)

29(2)

28(1)

27(48)

25(46)

26(47)

21(39)

19(37)

20(38)

VCCCL2

COMP2

EXTVCC

22

(41) 10(25)

5V Reg

UVLO

2.7V

OCP

SW

VREG5

LOGIC

Err Amp

－
＋
＋

0.8V

Set

Reset

Sequence DET

0.56V

18

(36)

DET2 LOFF EN2 EN1

VCC RT

STB

32
(7)

B.G SYNC

TSD

TSD

Set

DRV

Reset

TSD

UVLO

Q

PWM
COMP

Reset Set

Q

14

(31)

Slope

UVLO

12

(27)

(26)

15

(33)

11

●Pin configuration

●PIN function table

BD9011EKN（HQFN36V）

SW2

DGND2

OUTL2

27 26 25 24 23 22 21 20 19

CL2

VCC

CL1

28

29

30

31

32

33

34

35

36

1 2 3 4 5 6 7 8 9

OUTH2

BOOT2

VCCCL2

VCCCL1

BOOT1

OUTH1

SW1

OUTL1

DGND1

VREG5

VREG33

VREG5A

Fig-14

EXTVCC

FB2

FB1

COMP1

COMP2

SS1

SS2

DET1

18

17

16

15

14

13

12

11

10

Fig-13

DET2

LMM

SYNC

RT

LOFF

GND

EN2

EN1

STB

Pin

Pin name Function

No.

1 SW1 High side FET source pin 1
2 DGND1 Low side FET source pin 1
3 OUTL1 Low side FET gate drive pin 1
4 VREG5A FET drive REG input
5 VREG33 Reference input REG output
6 FB1 Error amp input 1
7 COMP1 Error amp output 1
8 SS1 Soft start setting pin 1

9 DET1 FB detector output 1
10 STB Standby ON/OFF pin
11 EN1 Output 1ON/OFF pin
12 EN2 Output 2ON/OFFpin
13 GND Ground

14 LOFF

Over current protection OFF latch

function ON/OFF pin
15 RT Switching frequency setting pin
16 SYNC External synchronous pulse input pin
17 LLM Built-in pull-down resistor pin
18 DET2 FB detector output 2
19 SS2 Soft start setting pin 2
20 COMP2 Error amp output 2
21 FB2 Error amp input 2
22 EXTVCC External power input pin
23 － N.C.
24 VREG5 FET drive REG output
25 OUTL2 Low side FET gate drive pin 2
26 DGND2 Low side FET source pin 2
27 SW2 High side FET source pin 2
28 OUTH2 Hi side FET gate drive pin 2
29 BOOT2 OUTH2 driver power pin
30 CL2 Over current detector setting pin 2
31 VCCCL2 Over current detection VCC2
32 VCC Input power pin
33 VCCCL1 Over current detection VCC1
34 CL1 Over current detector setting pin 1
35 BOOT1 OUTH1 driver power pin
36 OUTH1 High side FET gate drive pin 1

4/28

●Pin configuration ●Pin function table

BD9011KV（VQFP48C）

DET2

36 35

LLM

34 33

SYNC

RT

32

LOFF

GNDS

GND

N.C

EN2

EN1

N.C

31

30 29

27 26 25

28

STB

BOOT1

24

DET1

23

SS1

22

COMP1

21

FB1

20

N.C

19

VREG33

18

N.C

17

VREG5A

16

N.C

15

OUTL1

14

DGND1

13

SW1

OUTH1

SS2

COMP2

FB2

N.C

EXTVCC

N.C

N.C

VREG5

N.C

OUTL2

DGND2

SW2

37

38

39

40

41

42

43

44

45

46

47

48

1 2

OUTH2

BOOT2

3 4

CL2

N.C

6

5

VCCCL2

8 9 10 11 12

7

N.C

VCC

VCCCL1

N.C

CL1

Fig-15

●Block functional descriptions

・Error amp

The error amp compares output feedback voltage to the 0.8V reference voltage and provides the comparison result as COMP voltage, which is

used to determine the switching Duty. COMP voltage is limited to the SS voltage, since soft start at power up is based on SS pin voltage.

・Oscillator (OSC)

Oscillation frequency is determined by the switching frequency pin (RT) in this block. The frequency can be set between 250kHz and 550kHz.

・ SLOPE

The SLOPE block uses the clock produced by the oscillator to generate a triangular wave, and sends the wave to the PWM comparator.

・PWM COMP

The PWM comparator determines switching Duty by comparing the COMP voltage, output from the error amp, with the triangular wave from the
SLOPE block. Switching duty is limited to a percentage of the internal maximum duty, and thus cannot be 100% of the maximum.

・Reference voltage (5Vreg，33Vreg)

This block generates the internal reference voltages: 5V and 3.3V.

・External synchronization (SYNC)

Determines the switching frequency, based on the external pulse applied.

・Over current protection (OCP)

Over current protection is activated when the VCCCL-CL voltage reaches or exceeds 90mV. When over current protection is active, Duty is low,
and output voltage also decreases. When LOFF=L, the output voltage has fallen to 70% or below and output is latched OFF. The OFF latch
mode ends when the latch is set to STB, EN.

・Sequence control (Sequence DET)

Compares FB voltage with reference voltage (0.56V) and outputs the result as DET.

・Protection circuits (UVLO/TSD)

The UVLO lock out function is activated when VREG falls to about 2.8V, while TSD turns outputs OFF when the chip temperature reaches or
exceeds 150℃. Output is restored when temperature falls back below the threshold value.

Pin

Pin name Function

No.

1 OUTH2 High side FET gate drive pin 2
2 BOOT2 OUTH2 driver power pin
3 CL2 Over current detection pin 2
4 N.C Non-connect (unused) pin
5 VCCCL2 Over current detection VCC2
6 N.C Non-connect (unused) pin
7 VCC Input power pin
8 VCCCL1 Over current detection CC1

9 N.C Non-connect (unused) pin
10 CL1 Over current detection setting pin 1
11 BOOT1 OUTH1 driver power pin
12 OUTH1 High side FET gate drive pin 1
13 SW1 High side FET source pin 1
14 DGND1 Low side FET source pin 1
15 OUTL1 Low side FET gate drive pin 1
16 N.C Non-connect (unused) pin
17 VREG5A FET drive REG input
18 N.C Non-connect (unused) pin
19 VREG33 Reference input REG output
20 N.C Non-connect (unused) pin
21 FB1 Error amp input 1
22 COMP1 Error amp output 1
23 SS1 Soft start setting pin 1
24 DET1 FB detector output 1
25 STB Standby ON/OFF pin
26 EN1 Output 1 ON/OFF pin
27 EN2 Output 2 ON/OFF pin
28 N.C Non-connect (unused) pin
29 GND Ground
30 GNDS Sense ground

31 LOFF

32 N.C Non-connect (unused) pin
33 RT Switching frequency setting pin
34 SYNC External synchronous pulse input pin
35 LLM Built-in pull-down resistor pin
36 DET2 FB detector output 2
37 SS2 Soft start setting pin 2
38 COMP2 Error amp output 2
39 FB2 Error amp input 2
40 N.C Non-connect (unused) pin
41 EXTVCC External power input pin
42 N.C Non-connect (unused) pin
43 N.C Non-connect (unused) pin
44 VREG5 FET drive REG output
45 N.C Non-connect (unused) pin
46 OUTL2 Low side FET gate drive pin 2
47 DGND2 Low side FET source pin 2
48 SW2 High side FET source pin 2

Over current protection OFF latch

function ON/OFF pin

5/28

(

)

●Application circuit example (Parentheses indicate VQFP48C pin numbers)

Ω

BOOT1

EN1

15m

CL1

EN2

VIN(12V)

Ω

0.33

uF

33

(8)34(10)

VCCCL1

GND

15m

10

Ω

1nF1nF

31

32

(5)

(7)30(3)

VCC

VCCCL2

LOFF

RT

Ω

100

CL2

SYNC

Ω

29

(2)28(1)

BOOT2

DGND2

OUTL2

VREG5

EXTVCC

COMP2

DET2

LLM

SP8K2 SP8K2

100uF

100

1uF

1uF

39kΩ 15000pF

0.1uF

RB160
VA- 40

0.1
uF

(SLF12565：TDK)

68kΩ

10uH Vo(5V/3A)

RB051

L-40

220uF

(OSｺﾝ)

13kΩ

1(13)

2(14)

3(15)

4

5(19)

6(21)

7(22)

8(23)

9(24)

(17)

36

(12)35(11)

OUTH1

SW1

DGND1

OUTL1

VREG5A

VREG33

FB1

COMP1

SS1

DET1

STB

100kΩ

Fig-16A（Step-Down：Cout=OS Capacitor）

OUTH2

SW2

FB2

SS2

18

(36)17(35)16(34)15(33)14(31)13(29)12(27)11(26)10(25)

27(48)

26(47)

25(46)

24(44)

22(41)

21(39)

20(38)

19(37)

23

RB160
VA- 40

0.1
uF

1uF

0.33uF

39kΩ 15000pF

0.1uF

(SLF12565：TDK)

10uH Vo(3.3V/3A)

RB051
L-40

220uF

OS

47k

Ω

ｺﾝ

15k

Ω

There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.

VIN(12V)

3(15)

4(17)

5(19)

6(21)

7(22)

8(23)

9

1

2(14)

(24)

(13)

100uF

OUTH1

SW1

DGND1

OUTL1

VREG5A

VREG33

FB1

COMP1

SS1

DET1

3300pF

150

Ω

Vo(1 .8V/2 A)

15kΩ

12kΩ

(SLF10145：TDK)

10uH

RB051

L-40

30uF

(C2012JB

0J106K

TDK)

：

SP8K2 SP8K2

RB160

VA- 40

0.1
uF

1uF

1uF

330pF

1kΩ 10000pF

0.1uF

36

(12)35(11

STB

100

Ω

)

BOOT1

EN1

23m

34

(10)

CL1

EN2

12

(27)11(26)10(25)

23m

Ω

10

0.33

Ω

uF

1nF1nF

31

33

(5)

(8)32(7)30(3)

VCC

VCCCL1

VCCCL2

GND

LOFF

15

(33)14(31)13(29)

Ω

100

Ω

OUTH2

SW2

FB2

SS2

18

(36)17(35)

27

26(47)

25(46)

24

22(41)

21(39)

20(38)

19(37)

(48)

(44)

23

RB160

VA- 40

0.1
uF

1uF

0.33uF

330pF

0.1uF

(SLF10145：TDK)

10uH Vo(2.5V/2A)

RB051
L-40

30uF

(C2012JB

0J106K

TDK)

：

3.3kΩ 3300pF

43

1000pF

k

Ω

20k

510Ω

Ω

29

(2)28(1)

CL2

BOOT2

DGND2

OUTL2

VREG5

EXTVCC

COMP2

DET2

RT

SYNC

LLM

16

(34)

100kΩ

Fig-16B（Step-Down：Cout=Ceramic Capacitor）

There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.

6/28

A

100

(11

35

Ω

(10)33(8)

)

BOOT1

EN1

12

(27)11(26)

10m

34

CL1

EN2

VIN(12V)

Ω

0.33

uF

VCCCL1

GND

100kΩ

10m

Ω

10

Ω

100

Ω

1nF1nF

OUTH2

SW2

OUTL2

FB2

SS2

18

(36)17(35)

27

26

25

24

22

21

20

19

RB160
VA- 40

(48)

(47)

(46)

(44)

23

(41)

(39)

(38)

(37)

0.1
uF

1000pF

1uF

0.33uF

0.1uF

32

(7)

VCC

29

30

(2)28(1)

(3)31(5)

CL2

BOOT2

VCCCL2

DGND2

VREG5

EXTVCC

COMP2

LOFF

15

(33)14(31)13(29)

DET2

RT

SYNC

LLM

16

(34)

＊

SP8K2

(SLF12565：TDK)

4.7kΩ22000pF

REGSPIC

L2

27uH

RB051
L-40

Do3

Co2

220
uF

TM

Vo(12 V/1A)

91
kΩ

6.2kΩ

3300pF

10kΩ

＊ REGSPICTM is

Trade Mark of RHOM

Vo(2 4V/1A )

RB051L-40

L1
27uH

(SLF12565：TDK)

100uF

1

2

(15)

3

(17)

4

(19)

5

(21)

6

(22)

7

(23)

8

(24)

9

(13)

(14)

36

(12)

OUTH1

SW1

DGND1

OUTL1

VREG5A

VREG33

FB1

COMP1

SS1

DET1

STB

10

(25)

1000pF

5.1k

680
kΩ

Ω

23.5k

RSS

Co1

065N03

220uF

1uF

1uF

1uF

Ω

1000pF

10kΩ 22000pF

0.1uF

Fig-16C（Step-Down：Low Input Voltage）

There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.

Vo(1.8V/2A)

3300pF

100

Ω

(SLF10145：TDK)

15kΩ

12kΩ

6.8uH

RB051

30uF

(

ｾﾗｺﾝ

L-40

VIN(5V)

100uF

SP8K2

RB160

-40

V

0.1uF

)

1uF

1uF

100pF

3.3kΩ 4700pF

0.1uF

1

2

3

4

5

6

7

8

9

(13)

(14)

(15)

(17)

(19)

(21)

(22)

(23)

(24)

OUTH1

SW1

DGND1

OUTL1

VREG5A

VREG33

FB1

COMP1

SS1

DET1

36

(12)35(11

STB

100

Ω

)

BOOT1

EN1

23m

34

(10)

CL1

EN2

12

(27)11(26)10(25)

23m

Ω

10

0.33

Ω

uF

1nF1nF

31

33

(5)

(8)32(7)30(3)

VCC

VCCCL1

VCCCL2

GND

LOFF

RT

15

(33)14(31)13(29)

Ω

16

(34)

100

CL2

SYNC

Ω

29

(2)28(1)

OUTH2

SW2

BOOT2

DGND2

OUTL2

VREG5

EXTVCC

COMP2

DET2

LLM

18

(36)17(35)

FB2

SS2

27

26

25

24

22

21

20

19

(48)

(47)

(46)

(44)

23

(41)

(39)

(38)

(37)

RB160

VA- 40

1uF

0.33uF

33pF

0.1uF

0.1uF

10kΩ 2200pF

SP8K2

(SLF10145：TDK)

6.8uH Vo(2.5V/2A)

RB051
L-40

30uF

(

)

ｾﾗｺﾝ

43
k

20k

1000pF

Ω

300Ω

Ω

100kΩ

Fig-16D（Step-Up：and Step-Up-Down）

There are many factors(The PCB board layout, Output Current, etc.)that can affect the DCDC characteristics.
Please verify and confirm using practical applications.

7/28

●Application component selection

(1) Setting the output L value

ΔIL

The coil value significantly influences the output ripple current.
Thus, as seen in equation (5), the larger the coil, and the higher
the switching frequency, the lower the drop in ripple current.

Fig-17

VCC

（VCC-VOUT）×VOUT

ΔIL = [A]・・・（5）

L×VCC×f

I

L

VOUT

The optimal output ripple current setting is 30% of maximum current.
ΔIL = 0.3×IOUTmax.[A]・・・（6）

L

Co

（VCC-VOUT）×VOUT

L = [H]・・・（7）

ΔIL×VCC×f

Fig-18

Output ripple current

（ΔIL：output ripple current f：switching frequency）

※Outputting a current in excess of the coil current rating will cause magnetic saturation of the coil and decrease

efficiency.

Please establish sufficient margin to ensure that peak current does not exceed the coil current rating.

※Use low resistance (DCR, ACR) coils to minimize coil loss and increase efficiency.

(2) Setting the output capacitor Co value

Select the output capacitor with the highest value for ripple voltage (V

PP) tolerance and maximum drop voltage

(at rapid load change). The following equation is used to determine the output ripple voltage.

ΔIL Vo 1

Step down ΔV

PP = ΔIL × RESR + × × [V] Note: f：switching frequency

Co Vcc

f

Be sure to keep the output Co setting within the allowable ripple voltage range.

※Please allow sufficient output voltage margin in establishing the capacitor rating. Note that low-ESR capacitors enable

lower output ripple voltage.
Also, to meet the requirement for setting the output startup time parameter within the soft start time range, please factor
in the conditions described in the capacitance equation (9) for output capacitors, below.

TSS × (Limit – IOUT) Tss： soft start time

Co ≦ ・・・ （9）

VOUT ILimit：over current detection value（2/16）reference

Note: less than optimal capacitance values may cause problems at startup.

(3) Input capacitor selection

VIN

The input capacitor serves to lower the output impedance of the power
source connected to the input pin (VCC). Increased power supply output
impedance can cause input voltage (VCC) instability, and may negatively

Cin

impact oscillation and ripple rejection characteristics. Therefore, be
certain to establish an input capacitor in close proximity to the VCC and

VOUT

L

Co

GND pins. Select a low-ESR capacitor with the required ripple current
capacity and the capability to withstand temperature changes without
wide tolerance fluctuations. The ripple current IRMSS is determined
using equation (10).

IRMS = IOUT × [A]・・・（10）

VOUT（VCC - VOUT）

Also, be certain to ascertain the operating temperature, load range and

Fig-19

Input capacitor

MOSFET conditions for the application in which the capacitor will be used,
since capacitor performance is heavily dependent on the application’s
input power characteristics, substrate wiring and MOSFET gate drain
capacity.

VCC

8/28

(4) Feedback resistor design

Please refer to the following equation in determining the proper feedback resistance. The recommended setting is in a range
between 10kΩ and 330kΩ. Resistance less than 10kΩ risks decreased power efficiency, while setting the resistance value
higher than 330kΩ will result in an internal error amp input bias current of 0.2uA increasing the offset voltage.

Internal ref. 0.8V

R8 +R9
Vo = × 0.8 [V] ・・・（11 ）

R9

Fig-20

(5) Setting switching frequency

The triangular wave switching frequency can be set by connecting a resistor to the RT 15(33) pin. The RT sets the frequency
by adjusting the charge/discharge current in relation to the internal capacitor. Refer to the figure below in determining proper
RT resistance, noting that the recommended resistance setting is between 50kΩ and 130kΩ. Settings outside this range
may render the switching function inoperable, and proper operation of the controller overall cannot be guaranteed when
unsupported resistance values are used.

550

500

450

400

350

周波数 [ kHz ]

300

250

50 60 70 80 90 100 110 120 130

RT [ kΩ]

Fig-21 RT vs. switching frequency

(6) Setting the soft start delay

The soft start function is necessary to prevent an inrush of coil current and output voltage overshoot at startup. The figure
below shows the relation between soft start delay time and capacitance, which can be calculated using equation (12) at right.

0.8V(typ.)×CSS
TSS = [sec]・・・(12)
ISS(10μA Typ.)

10

1

0.1

DELAY TIME[ms]

0.01

0.001 0.01 0.1

SS CAPACITANCE[uF]

Fig-22 SS capacitance vs. delay time

Recommended capacitance values are between 0.01uF and 0.1uF. Capacitance lower than 0.01uF may generate output
overshoots. Please use high accuracy components (such as X5R) when implementing sequential startups involving other
power sources. Be sure to test the actual devices and applications to be used, since the soft start time varies, depending on
input voltage, output voltage and capacitance, coils and other characteristics.

9/28