ROHM BD8919FV Technical data
IC Card Interface ICs
IC Card Interface ICs
with Built-in Low Noise LDO Regulator
BD8918F,BD8918FV,BD8919F,BD8919FV
No.09056EDT01
●Overview
This is an interface IC for a 5V smart card.
It works as a bidirectional signal buffer between a smart card and a controller. Also, it supplies 5V power to a smart card.
With an electrostatic breakdown voltage of more than HBM; ±6000V, it protects the card contact pins.
●Features
1) 1 half duplex bidirectional buffers
2) Protection against short-circuit for all the card contact pins
3) 5V power source for the card (VCC)
4) Over-current protection for card power source
5) Built-in thermal shutdown circuit
6) Built-in supply voltage detector
7) Automatic activation/deactivation sequence function for card contact pin
Activation sequence: driven by a signal from controller (CMDVCCB)
Deactivation sequence: driven by a signal from controller (CMDVCCB) and fault detection (card removal, short
circuit of card power, IC overheat detection, VDD or VDDP drop)
8) Card contact pin ESD voltage ≧ ±6000V
9) Recommend frequency of crystal oscillator: 8MHz (BD8918F/FV), 16MHz (BD8919F/FV)
10) Programmable for card clock division of output signal: 1/1 and 1/2(BD8918F/FV), 1/2 and 1/4(BD8919F/FV).
11) RST output control by RSTIN input signal (positive output)
12) One multiplexed card status output by OFFB signal
●Applications
Interface for CLASS A smart cards
Interface for B-CAS cards
●Line up matrix
Part No
BD8918F
BD8918FV SSOP-B16
BD8919F
BD8919FV SSOP-B16
Ratio of dividing frequency
Card clock
1/1f, 1/2f
1/2f, 1/4f
Package
SOP16
SOP16
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© 2009 ROHM Co., Ltd. All rights reserved.
1/15
2010.4 - Rev.D
BD8918F,BD8918FV,BD8919F,BD8919FV
●Absolute maximum ratings (Ta=25°C)
Parameter Symbol Ratings Unit Notes
VDD Input Voltage VDD -0.3 ~ 6.5 V
Technical Note
VDDP Input Voltage V
I/O Pin Voltage
-0.3 ~ 6.5 V
DDP
V
V
MIN
MOUT
-0.3 ~ +6.5 V
Pin: XTAL1, XTAL2, CLKSEL, RSTIN, IO_U
CMDVCCB, OFFB
Card Contact Pin Voltage VCD -0.3 ~ +6.5 V Pin: PRES, CLK, RST, IO_C
Junction Temperature T
Storage Temperature T
Power Dissipation P
*1 BD8918F/BD8919F, *2 BD8918FV/BD8919FV
• This product is not designed to be radiation tolerant.
• Absolute maximum ratings are not meant for guarantee of operation.
+150 °C
jmax
-55 ~ +150 °C
stg
*1
tot
0.375
0.500
*2
T = -20 ~ +85°C
W
(Refer to the following package power dissipation)
●Operating Conditions (Ta=25°C)
Parameter
Symb
ol
Ratings Unit Notes
MIN TYP MAX
VDD Input Voltage VDD 2.7 - 5.5 V
VDDP Input Voltage V
Operating Temperature T
4.75 - 5.5 V VCC ≥ 4.55V
DDP
-40 - +85 °C
opr
●Package Power Dissipation
The power dissipation of a simple package in case of a boadless will be as follows.
Use of this device beyond the following the power dissipation may cause permanent damage.
BD8918F/BD8919F Pd=375mW; however, reduce 3mW per 1°C when used at Ta ≥ 25°C.
BD8918FV/BD8919FV Pd=500mW; however, reduce 4mW per 1°C when used at Ta ≥ 25°C.
0.4
Package power
0.6
Package power
0.3
0.5
0.4
0.2
Pd (W)
0.3
Pd (W)
0.1
0.2
0.1
0.0
0 25 50 75 100 125 150
Temp (℃)
0.0
0 25 50 75 100 125 150
Temp (℃)
Fig. 1.1 BD8918F/BD8919F Power Dissipation Fig. 1.2 BD8918FV/BD8919FV Power Dissipation
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© 2009 ROHM Co., Ltd. All rights reserved.
2/15
2010.4 - Rev.D
BD8918F,BD8918FV,BD8919F,BD8919FV
●Block Diagram
2.7V-5.5V
VDD
0.1uF
VIREF
VDET
TSD
VDD
LVS
20k
POWER_ ON
ALARM
OFFB
RSTIN
CMDVCCB
CLKSEL
VDD
50k
50k
50k
CLK
DIV
SEQUENCER
DIVEN
DIVCLK
22pF
22
F
pF
IO_U
XTAL1
220Ω
XTAL
XT
OSC
2
MAX 1MHz
VDD
11k 11k
GND
BD8918F/FV F=8MHz
BD8919F/FV F=16MHz
TSD
ALARM
IOEN
Fig. 2
VREF
VCCEN
VCC
ALARM
RSTEN
CLKEN
IO TRANS
LVS
VDD
4.75V-5.5V
VDDP
LDO
LVS
RST BUF
LV S
CLK BUF
LVS
VDD
10µF
50k
VCC
Technical Note
5V
VCC
1µF
CGND
RST
CLK
PRES
IO_C
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© 2009 ROHM Co., Ltd. All rights reserved.
3/15
2010.4 - Rev.D
BD8918F,BD8918FV,BD8919F,BD8919FV
●Pin Description
Pin No. Pin Name I/O
Signal
Level
Technical Note
Pin Function
1 XTAL1 I VDD
2 XTAL2 O VDD
3 VDD S VDD
4 CLKSEL I VDD
5 RSTIN I VDD
6 IO_U I/O VDD
7 CGND S GND
8 IO_C I/O VCC
9 RST O VCC
10 CLK O VCC
11 VCC O VCC
12 VDDP S VDDP
13 PRES I VDD
14 OFFB O VDD
15 CMDVCCB I VDD
Crystal connection or input for external clock
Crystal connection (leave open pin when external clock source is used)
3.3 V power source pin for host interface.
Connect 0.1µF capacitor between the VDD and GND pins.
Input for clock frequency
division setting.
Pulled down to GND
with a 50k resistor.
Card reset signal input. Pulled down to GND with a 50k resistor.
Host data I/O line; Pulled up to VDD with an 11k resistor
GND
I/O data line on the card side. Pulled up to VCC with an 11kresistor.
Card reset output
Card clock output
Card supply voltage. Connect 1µF capacitor between VCC and the CGND pins.
5V power source pin for card power feed. Connect 10µF capacitor between the
VDDP and CGND pins.
Card presence contact input (“H” active). Pulled up to VDD with a 50k resistor.
Connected to a switch where GND level is inputted when no card is inserted and
OPEN is inputted when a card is inserted. When “H” level is detected, a card is
assumed to be inserted and waits for the CMDVCCB input for the confirmation,
after the debounce time of typ. 8ms.
Alarm output pin (“L” active).
NMOS open drain output. Pulled up to VDD with a 20k resistor.
Activation sequence command input; The activation sequence starts by signal
input (HL) from the host
BD8918F/FV H: 1/1 division; L: 1/2 division.
BD8919F/FV H: 1/2 division; L: 1/4 division.
16 GND S GND
*Capacitors to be connected to VDD, VDDP and VCC should be placed immediately next to the pins (ESR<100m).
GND
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© 2009 ROHM Co., Ltd. All rights reserved.
4/15
2010.4 - Rev.D
BD8918F,BD8918FV,BD8919F,BD8919FV
●Pin Function Diagram
Pin
No.
Pin
Name
Pin function Diagram
Pin
No.
Pin
Name
Technical Note
Pin function Diagram
VDD
VDD
1XTAL1
1
2
1. 2 M
Ω
100
Ω
8IO_C
2XTAL2
3
3VDD 9 RST
VDD
4CLKSEL
VDDP8VREG
11K
Ω
VREG
VREG
VREG
VDDP
9
VDDP
4,5
50K
5RSTIN
6IO_U 11 VCC
5
Ω
VDD VDD
11 K
Ω
10 CLK
7CGND
VDDP
1
Ω
10
VDDP
11
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© 2009 ROHM Co., Ltd. All rights reserved.
5/15
2010.4 - Rev.D
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