ROHM BD8628EFV, BD8624EFV Technical data

TECHNICAL NOTE

System Power Supply for TV Series

Built-in 1ch FET Synchronous Rectification Type DC/DC converters

BD8628EFV, BD8624EFV

●Description BD8628EFV / BD8624EFV have realized the high performance and reliability required as a power supply for thin-screen TV. With built-in FET 1ch current mode control, the DC/DC Converter series has the advantage of high-speed load response and wide phase margin. Due to the high-speed load response, it is most suitable for TV-purpose processors with increasingly high performance, and due to the wide phase margin it leaves a good margin for board pattern & constant setting and so facilitates its application design. As a high-reliability design, it has various built-in protection circuits (overcurrent protection, output voltage abnormal protection, thermal protection, and off-latch function at the time of abnormality etc.), therefore as an advantage it does not easily damage in every possible abnormal condition such as all-pin short circuit test etc. and hence most suitable for thin-screen TV which requires the high reliability.

●Features

1) 1ch synchronous rectification step-down system DC/DC converter

2) Soft start, soft off function

3) Built-in low voltage / overvoltage protection function

4) Built-in overcurrent protection function

5) Frequency setting by external resistance is available. (RT terminal)

6) Protection time setting by external resistance is available. (RSET terminal)

7) Built-in RT / RSET terminal open/short protection function

8) Protection control with built-in sequencer

9) Built-in adjustment function time of off latch

10) Built-in error state detection signal output function

11) Built-in tracking function

12) Corresponded to protecting bus

13) Load current Maximum 3A

14) HTSSOP－B24 Package

Aug. 2008

2

F

C

R

P

t

O

5

_

P

● Electric characteristic

(Ta=25℃, VCC=6.5V, GND=0V,CTL=6.5V unless otherwise specified.)

Parameter Symbol

Circuit current 1 Circuit current 2

I

- 0 10 μA CTL=0V

Q1

I

- 3.4 - mA CTL=VCC

Q

< Error amplifier part > Standard voltage （VREF） V Terminal FB Input bias current I Terminal FC Clamping voltage H Terminal FC Clamping voltage L Terminal FC Sink current Terminal FC Source current I Open loop gain A

0.792 0.8 0.808 V Terminal FB and FC terminal short

RE

-1 0 1 μA VFB=0.9V

FBB

V

1.8 - - V VFB=0.7V

FCH

V

- - 0.2 V VFB=0.9V

FCL

I

0.5 - - mA VFB=0.9V, V

FCSINK

FCSOURCE

- - -70 μA VFB=0.7V, V

- 100 - dB

VER

Oscillation frequency F

400 500 600 kHz

OSC

<Soft start > Charging current ISS -3 -2.5 -2 μA VSS=1.0V Terminal SS Threshold voltage V Terminal SS Clamping voltage V Terminal SS Standby voltage

0.98 1.08 1.18 V V

SSTH

2.2 2.4 - V

SSCLM

V

0.1 0.15 - V V

SSSTB

Terminal SS Discharge resistance RSS 49 70 91 kΩ CTL=0V

Terminal SS Protection circuit start voltage Terminal SS Protection circuit start voltage Maximum

hysteresis error

V

SSPON

V

SSPON_HYS

1.0 1.1 1.2 V V

< Low voltage, over voltage detection part＞

Terminal FB Low voltage detection voltage Terminal FB Overvoltage detection voltage

V

0.51 0.56 0.61 V V

LV

V

0.86 0.96 1.06 V VFB

OV

< Over current detection part＞ Output current limitation threshold I

VCC-0.9 VCC-0.7 VCC-0.5 V VSW

lm

<Power MOS> Upper side MOS ON resistance R Lower side MOS ON resistance R

- 110 - mΩ V

ONU

- 110 - mΩ V

NL

<Others＞

Terminal PDET L output voltage Terminal CTL input voltage H level voltage Terminal CTL input voltage L level voltage Terminal CTL input current I

V

- - 0.4 V IOL=100uA

OL

DET

V

2.0 - VCC V CTL terminal

IH_CTL

V

- - 0.5 V CTL terminal

IL_CTL

- 60 90 μA CTL terminal, CTL=VCC

I_CTL

VFB : FB terminal voltage, VFC : FC terminal voltage, VSS : SS terminal voltage, V

Not designed for radiation resistance.

Current capability should not exceed Pd.

specification value

MIN TYP MAX

UNIT Condition

10 100 200 mV V

: MONVCC terminal voltage

MONVCC

When terminal RT 27kΩ is connected

SS Voltage

FB Voltage

Volt age

Vol tage

BOOT－VSW

=5V

VREG

=0.4V

F

=1.6V

F

(L→H)

=5V

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jc

j

T

[

T

x

[

T

x

[

T

x

[

T

j

x

[

Permissible loss

This package is a product of which the feature is the high heat radiation, and connect the back to GND based on recommended land pattern when you mount.

cma

θ

[ ℃ /W]

a

θ

[ ℃/W]

STGmin

]

℃

STGma

℃

]

a min

[℃]

a ma

℃

]

Destruction temperature

]

℃

ma

Destruction temperature

]

℃

19.0 31.3 -50.0 150.0 -45.0 85.0 150.0 150.0

Permissible loss ： Pd [W]

ROHM standard substrate specification Material 4 layer glass epoxy substrate(back copper foil70mm×70mm) Size 70mm×70mm×1.6mmt(Sarmalbiaing is in the substrate.)

Figure 1 Heat decrease curve

※These values are the actual measurement values, and no guarantee values.

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● Block diagram

RSET

PDET

PIO

CTL

VCC

PVCC

OSC

OPEN/SHORT

SEQ

Control

RT

Driver

Control

OVP LVP

RT

OSC

time

PROTECT

BUS

I/F

17

CTL

18 19

OSC

VREF

VREG5

SS

FB

FC

10

GND

９８７５

VREG5

BOOT

SW

６

SW

TEST2

TEST1

N.C.

Figure-2 Block diagram・Application diagram

N.C.

４

N.C.

３

PGND

２１

PGND

● Terminal explanation

No. Symbol Description No. Symbol Description

1 PGND

2 PGND

3 N.C.

4 N.C

5 SW

6 SW

7 BOOT

8 VREG5

9 GND

10 FC

11 F B

12 SS

Soft start adjustment capacity connection terminal

Internal power supply (5.0V) output terminal

Power GND terminal

No wire connection. (Connect to GND. ) No wire connection. (Connect to GND. )

SW terminal

High side Power MOS gate drive

power source terminal

GND

Phase amends terminal

Feedback terminal

※Please give to VCC+0.3V as an operation condition in all input terminals except the terminal BOOT.

However, please do not exceed the absolute maximum rating as VCC=PVCC.

Table 1 Terminal explanation

13 RT

14 RSET

15

16

ＰＤＥＴ Error state notification terminal

PＩＯ

Frequency adjustment resistance connection terminal

Off latch effective time adjustment resistance terminal

17 CTL

18 VCC

19 PVCC

20 PVCC

21 TEST2

22 TEST1

23 N.C.

24 N.C.

Error state notification

and external IC error detection terminal

Enable input

VCC power supply terminal

Power VCC terminal

Test terminal (Connect to GND. )

No wire connection.

(Connect to GND. )

No wire connection.

(Connect to GND. )

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● Terminal equivalent circuit chart

Terminal

No.

1 PGND

2 PGND

5 SW SW terminal

6 SW SW terminal

Terminal

name

Power GND (The same potential as the GND terminal) Power GND (The same potential as the GND terminal)

Explanation Terminal equivalent circuit chart

PVCC PVCC

PGND

⑤ ⑥

7 BOOT

High side Power MOS gate drive power source terminal

8 VREG5 Internal power supply (5.0V) output terminal

9 GND GND

VREG5

⑦

PGND

10 FC Phase amends terminal

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