ROHM BD8312HFN Technical data

Single-chip Type with Built-in FET Switching Regulators

Output 1.5A or Less
High-efficiency Step-down Switching Regulator
with Built-in Power MOSFET

BD8312HFN

●Description

BD8312HFN produces step-down output including 1.2, 1.8, 3.3, or 5 V from 4 batteries, batteries such as Li2cell or Li3cell,
etc. or a 5V/12V fixed power supply line.
This IC allows easy production of small power supply by a wide range of external constants, and is equipped with an external
coil/capacitor downsized by high frequency operation of 1.5 MHz, built-in synchronous rectification SW capable of
withstanding 15 V, and flexible phase compensation system on board.

●Features

1) Incorporates Pch/Nch synchronous rectification SW capable of withstanding 1.0 A/15V.

2) Incorporates phase compensation device between input and output of Error AMP.

3) Small coils and capacitors to be used by high frequency operation of 1.5MHz

4) Input voltage 3.5 V – 14 V
Output current 1.2A(7.4V input, 3.3V output)

0.8A(4.5V input, 3.3V output)

5) Incorporates soft-start function.

6) Incorporates timer latch system short protecting function.

7) As small as 2.9mm×3 mm, SON 8-pin package HSON8

●Application

For portable equipment like DSC/DVC powered by 4 dry batteries or Li2cell and Li3cell, or general consumer-equipment
with 5 V/12 V lines

●Operating Conditions (Ta = 25℃)

Parameter Symbol Voltage circuit Unit

Power supply voltage VCC 3.5 to 14 V

Output voltage VOUT 1.2 to 12 V

●Absolute Maximum Ratings

Parameter Symbol Rating Unit

Maximum applied power voltage VCC, PVCC 15 V

Maximum input current Iinmax 1.0 A

Power dissipation Pd 630 mW
Operating temperature range Topr -25 to +85 ℃
Storage temperature range Tstg -55 to +150 ℃
Junction temperature Tjmax +150 ℃

*1 When used at Ta = 25℃ or more installed on a 70×70×1.6tmm board, the rating is reduced by 5.04mW/℃.
* These specifications are subject to change without advance notice for modifications and other reasons.

No.11027EDT04

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1/14

2011.04 - Rev.D

BD8312HFN

Technical Note

●Electrical Characteristics
（Unless otherwise specified, Ta = 25 ℃, VCC = 7.4 V）

Parameter Symbol

Target Value

Min Typ Max

Unit Conditions

[Low voltage input malfunction preventing circuit]

Detection threshold voltage VUV - 2.9 3.2 V VREG monitor
Hysteresis range ΔVUVhy 100 200 300 mV
[Oscillator]
Oscillation frequency Fosc 1.38 1.5 1.62 MHz

[Regulator]

Output voltage VREG 4.65 5.0 5.35 V

[Error AMP]
INV threshold voltage VINV 0.99 1.00 1.01 V

Input bias current IINV -50 0 50 nA VCC=12.0V , VINV=6.0V
Soft-start time Tss 3.2 5.3 7.4 msec

[PWM comparator]
LX Max Duty Dmax - - (※)100 %

[Output]
PMOS ON resistance RONP - 450 600 mΩ
NMOS ON resistance RONN - 300 420 mΩ
Leak current Ileak -1 0 1 µA

[STB]

STB pin
control voltage

STB pin pull-down resistance

Operation VSTBH 2.5 - 11 V
No-operation VSTBL -0.3 - 0.3 V

250 400 700 kΩ

[Circuit current]

Standby current

VCC pin I

PVCC pin ISTB2 - - 1 µA

Circuit current at operation VCC

Circuit current at operation PVCC

(※1) 100% is MAX Duty as behavior of a PWM conparetor.

Using in region where High side PMOS is 100% on state when the same or less input voltage than output voltage is supplied as an application circuit
causes detection of SCP then DC/DC converter stops.

 Not designed to be resistant to radiation

STB1 - - 1 µA

- 600 900 µA VINV=1.2V

- 30 50 µA VINV=1.2V

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2011.04 - Rev.D

BD8312HFN

●Description of Pins

GND

VCC

VREG

INV

STB

PVCC

PGND

Lx

Fig.1 Terminal layout

Pin No. Pin Name Function

1 GND Ground terminal

2 VCC Control part power input terminal

3 VREG

4 PGND Power transistor ground terminal

5 Lx Coil connecting terminal

6 PVCC DC/DC converter input terminal

7 STB ON/OFF terminal

8 INV Error AMP input terminal

●Block Diagram

ON/OFF

STB

VREG

VCC

STBY_IO

1.0MHz

OSC

DC/DC
converter
100% High

Duty

STOP

5V REG

SCP

OSC×4000 ｃount

PWM

CONTROL

Step down

GND

VREF

+-+

ERROR_AMP

Soft
Start

OSC×8000 ｃount

INV

Reference

VREF

PRE

DRIVER

TIMMING

CONTROL

PRE

DRIVER

Fig.2 Block diagram

Technical Note

5 V output terminal of regulator for
internal circuit

PVCC

UVLO

450mΩ

LX

VREG

300mΩ

PGND

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2011.04 - Rev.D

BD8312HFN

●Description of Blocks

1. Reference
This block produces ERROR AMP standard voltage.
The standard voltage is 1.0 V.

2. 5 V Reg
5 V low saturation regulator for internal analog circuit
BD8312HFN is equipped with this regulator for the purpose of protecting the internal circuit from high voltage. Therefore,
this output is reduced when VCC is less than 5 V, then PMOS ON resistance increases and Power efficiency and
Maximum output current of DC/DC converter decreases in this region. Please see attached data (fig14,15,16,17) about
increasing of PMOS ON resistance in this region.

3 UVLO

Circuit for preventing low voltage malfunction
Prevents malfunction of the internal circuit at activation of the power supply voltage or at low power supply voltage.
Monitors VCC pin voltage to turn off all output FET and DC/DC converter output when VCC voltage is lower than 2.9 V,
and reset the timer latch of the internal SCP circuit and soft-start circuit. This threshold contains 200 mV hysteresis.

4 SCP

Timer latch system short-circuit protection circuit
When DC/DC converter is 100% High Duty , the internal SCP circuit starts counting.
The internal counter is in synch with OSC, the latch circuit is activated about 2.7 msec after the counter counts about 4000
oscillations to turn off DC/DC converter output.
To reset the latch circuit, turn off the STB pin once. Then, turn it on again or turn on the power supply voltage again.

5 OSC

Circuit for oscillating sawtooth waves with an operation frequency fixed at 1.5 MHz

6 ERROR AMP

Error amplifier for detecting output signals and output PWM control signals
The internal standard voltage is set at 1.0 V.
A primary phase compensation device of 200 pF, 62 kΩ is built in-between the inverting input terminal and the output
terminal of this ERROR AMP.

7 PWM COMP

Voltage-pulse width converter for controlling output voltage corresponding to input voltage
Comparing the internal SLOPE waveform with the ERROR AMP output voltage, PWM COMP
controls the pulse width to the output to the driver.

8 SOFT START

Circuit for preventing in-rush current at startup by bringing the output voltage of the DC/DC converter into a soft-start
Soft-start time is in synch with the internal OSC, and the output voltage of the DC/DC converter reaches the set voltage
after about 8000 oscillations.

9 PRE DRIVER/TIMING CONTROL

CMOS inverter circuit for driving the built-in synchronous rectification SW
The synchronous rectification OFF time for preventing feedthrough is about 25 nsec.

10 STBY_IO

Voltage applied on STB pin (7 pin) to control ON/OFF of IC
Turned ON when a voltage of 2.5 V or higher is applied and turned OFF when the terminal is open or 0 V is applied.
Incorporates approximately 400 kΩ pull-down resistance.

11 Pch/Nch FET SW

Built-in synchronous rectification SW for switching the coil current of the DC/DC converter
Incorporates a 450 mΩ PchFET SW capable of withstanding 15 V.and 300 mΩ SW capable of withstanding 15 V.
Since the current rating of this FET is 1.0A, it should be used within 1.0A including the DC current and ripple current of the coil.

Technical Note

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2011.04 - Rev.D

BD8312HFN

●Reference data
（Unless otherwise specified, Ta = 25℃, VCC = 7.4 V）

1.02

1.02

1.01

1.01

1.00

INV THRESHOLD [V]

0.99

1.00

INV THRESHOLD [V]

0.99

0.98

-40 -20 0 20 40 60 80 100 120

TEMPERATURE [℃]

0.98

Fig.3. INV

8

7

6

5

4

VREG[V]

3

2

1

0

02468101214

VCC [V]

1.7

1.6

1.5

FREQUENCY [MHz]

1.4

1.3

Fig.6. VREG

3.50

Hysteresis width

3.30

Vhys [V]

3.10

UVLO release voltage

0.25

0.20

0.15

02468101214

VCC [V]

Fig.4. INV

-40 0 40 80 120

TEMPERATURE [℃]

Fig.7. fosc

500

ID=500mA

400

300

Technical Note

5.3

5.2

5.1

5.0

4.9

VREG VOLTAGE [V]

4.8

4.7

-40 0 40 80 120

TEMPERATURE [℃]

Fig.5. VREG output

1.7

1.6

1.5

FREQUENCY [ MHz ]

1.4

1.3

3691215

600

ID=500mA

500

400

300

VCC [V]

Fig.8. fosc

2.90

ヒステリシス電圧

2.70

Hysteresis Voltage Vhys[V]

UVLO detection voltage

2.50

-40 0 40 80 120

Environmental temperature Ta [°C]

環境温度

Ta [℃]

Fig.9. UVLO

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0.10

0.05

0.00

200

ON RESISTANCE [ mΩ ]

100

-40 0 40 80 120

TEMPARATURE [℃]

Fig.10. Nch FET ON resistance

5/14

200

ON RESISTANCE [ mΩ]

100

0

3 6 9 12 15

VCC [V]

Fig.11. Nch FET ON resistance

2011.04 - Rev.D