ROHM BD8303MUV Technical data

Large Current External FET Controller Type Switching Regulators

Step-up/down, High-efficiency
Switching Regulators (Controller type)

BD8303MUV

No.09028EAT02

● General Description
ROHM’s highly-efficient step-up/down switching regulator BD8303MUV generates step-up/down output including 3.3 V / 5 V
from 1 cell of lithium battery, 4 batteries, or 2 cells of Li batteries with just one inductor.
This IC adopts an original step-up/down drive system and creates a higher efficient power supply than conventional
Sepic-system or H-bridge system switching regulators.

● Features

1)Highly-efficient step-up/down DC/DC converter to be constructed just with one inductor.

2) Supports a wide range of power supply voltage range (input voltage: 2.7 V - 14.0 V)

3) Supports high-current application with external Nch FET.

4) Incorporates soft-start function.

5) Incorporates timer latch system short protecting function.

6) High heat radiation surface mounted package QFN16 pin, 3 mm × 3 mm

● Application
General portable equipment like DVC, single-lens reflex cameras, portable DVDs, or mobile PCs

● Absolute Maximum Ratings

Parameter Symbol Rating Unit

VCC 15 V
VREG 7 V
Between BOOT

Maximum applied power voltage

Power dissipation Pd 620 mW
Operating temperature range Topr
Storage temperature range Tstg －55 to +150 °C

Junction temperature Tjmax +150 °C

When installed on a 70.0 mm × 70.0 mm × 1.6 mm glass epoxy board. The rating is reduced by 4.96 mW/°C at Ta = 25°C or more.

● Operating Conditions (Ta = 25°C)

Parameter Symbol
Power supply voltage VCC 2.7 － 14 V

Output voltage VOUT 1.8 － 12 V
Oscillation frequency fosc 0.2 0.6 1.0 MHz

* These specifications are subject to change without advance notice for modifications and other reasons.

1, 2 and SW 1, 2
Between BOOT
1, 2 and GND
SW1, 2 15 V

Standard value
MIN TYP MAX

7 V
20 V

－25 to +85

°C

Unit

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BD8303MUV

● Electrical Characteristics

(Unless otherwise specified, Ta = 25 °C, VCC = 7.4 V)

Technical Note

Parameter Symbol

Minimum Typical Maximum

Target Value

Unit Conditions

[Low voltage input malfunction preventing circuit]
Detection threshold voltage VUV - 2.4 2.6 V VREG monitor
Hysteresis range ΔVUVhy 50 100 200 mV
[Oscillator]
Oscillation frequency fosc 480 600 720 kHz RT=51kΩ
[Regulator]
Output voltage VREG 4.7 5.1 5.5 V
[Error AMP]
INV threshold voltage VINV 0.9875 1.00 1.0125 V
Input bias current IINV -50 0 50 nA Vcc=12.0V , IINV=6.0V
Soft-start time Tss 2.4 4.0 5.6 msec RT=51kΩ
Output source current IEO 10 20 30 μA VINV=0.8V , VFB =1.5V
Output sink current IEI 0.6 1.3 3 mA VINV=1.2V , VFB =1.5V
[PWM comparator]
SW1 Max Duty Dmax1 85 90 95 % HG1 ON
SW2 Max Duty Dmax2 85 90 95 % LG2 ON
SW2 Min Duty Dmin2 5 10 15 % LG2 OFF
[Output]
HG1, 2 High side ON resistance RONHp - 4 8 Ω
HG1, 2 Low side ON resistance RONHn - 4 8 Ω
LG1, 2 High side ON resistance RONLp - 4 8 Ω
LG1, 2 Low side ON resistance RONLn - 4 8 Ω
HG1-LG1 dead time Tdead1 50 100 200 nsec
HG2-LG2 dead time Tdead2 50 100 200 nsec
[STB]
STB pin
control voltage

STB pin pull-down resistance

Operation V
No-operation VSTBL -0.3 - 0.3 V

STBH 2.5 - VCC V

STB 250 400 700 kΩ

R
[Circuit current]
Standby
current
Circuit current at operation
VCC
Circuit current at operation
BOOT1,2

VCC pin ISTB - - 1 μA

Icc1 - 650 1000 μA V
Icc2 - 120 240 μA V

INV=1.2V
INV=1.2V

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Technical Note

● Reference Data

1.050

1.050

1.025

1.000

0.975

VREF VOLTAGE [V]

0.950
0 5 10 15

VCC VOLTAGE [V]

1.025

1.000

0.975

VREF VOLTAGE [V]

0.950

-40 0 40 80 120

AMBIENT TEMPERATURE[℃]

6.0

5.0

4.0

3.0

2.0

VREG VOLTAGE [V]

1.0

0.0
0 5 10 15

VCC VOLTAGE [V]

Fig.1 Standard voltage -

Power supply property

Fig.2 Standard voltage -

Temperature property

Fig.3 VREG voltage -

Power supply property

5.300

5.200

5.100

5.000

4.900

VREF VOLTAGE [V]

4.800

4.700

-40 0 40 80 120

AMBIENT TEMPERATURE[℃]

1000

900
800
700
600
500
400
300

VCC CURRENT [uA]

200
100

0

0 5 10 15

Fig.4 VREG voltage –
Temperature property

VCC VOLTAGE [V]

Fig.7 ICC - Power supply

property

800

700

600

500

VREF VOLTAGE [V]

400

0 5 10 15

VCC VOLTAGE [V]

Fig.5 Oscillation frequency –

Power supply property

800

750

700

650

600

VCC CURRENT [uA]

550

500

-40 0 40 80 120

VCC VOLTAGE [V]

Fig.8 ICC - Temperature

property

700
680
660
640
620
600
580
560

VREF VOLTAGE [V]

540
520
500

-40 0 40 80 120

AMBIENT TEMPERATURE[℃]

Fig.6 Oscillation frequency -

Temperature property

160
140
120
100

80
60
40

BOOT PIN CURRENT [uA]

20

0

0123456

BOOT PIN VOLTAGE [V]

Fig.9 IBOOT - Power supply

property

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5.050

5.050

5.025

5.025

5.000

5.000

4.975

VOUT VOLTAGE [V]

4.975

VOUT VOLTAGE [V]

4.950
0 5 10 15

VCC VOLTAGE [V]

Fig.10 Line regulation Fig.11 Load regulation

4.950
0 500 1000 1500

LOAD CURRENT [mA]

STB(5.0V/div)

VOUT(2.0V/div)

Input current (200mA/div)

Fig.13 Starting waveform

(Example of Application Circuit [2])

L=10uH, Cout = 47 uH, fosc = 750

kHz, unloaded

Fig.14 Oscillation waveform

VCC = 5.0 V, Vout = 5.0 V

I LOAD = 1000 mA

100

90
80
70
60
50
40
30

EFFICIENCY [%]

20
10

0

0 1000 2000 3000

Example of Application Circuit [1]

LOAD CURRENT [mA]

Fig.16

Efficiency data (VOUT = 3.3 V)

100

90
80
70
60
50
40
30

EFFICIENCY [%]

20
10

0

0 500 1000 1500

LOAD CURRENT [mA]

Efficiency data (VOUT = 5.0 V)

Example of Application Circuit [2]

● Package Heat Reduction Curve

700

600

500

400

300

200

100

POWER DISSIPATION [mW]

0

0 25 50 75 100 125 150

AMBIENT TEMPERATURE[℃]

Fig.19 heat reduction curve (IC alone)

When used at Ta = 25°C or more, it is reduced by 4.96 mW/°C.

Fig.17

SW1 oscillation
waveform (2.0V/div)

SW2 oscillation
waveform (2.0V/div)

500usec/div

Technical Note

100

90
80
70
60
50
40
30

EFFICIENCY [%]

20
10

0

0 500 1000 1500

LOAD CURRENT [mA]

Fig.12 MAX Duty / MIN Duty

temperature property

VOUT(100mV/div)

ILOAD(500mA/div)

500usec/div

Fig.15 Load variation waveform

(Example of Application Circuit [2])

VCC = 7.4 V, Vout = 5.0 V,

I LOAD = 200 mA1000 mA :40 mA/usec

100

90
80
70
60
50
40
30

EFFICIENCY [%]

20
10

0

0 500 1000 1500 2000

LOAD CURRENT [mA]

Fig.18

Efficiency data (VOUT = 8.4 V)

Example of Application Circuit [3]

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BD8303MUV

● Description of Pins

RT

INV

FB

GND

● Block Diagram

VCC

VREG

BOOT1

STB

HG2

SW2

BOOT2

Fig. 20 Pin layout

RT

INV

FB

GND

HG1

OSC

SOFT

START

OSC x 2400 count

VREF

1.0V

SW1

LG1

PGND

LG2

VCC

UVLO

VREF

ERROR AMP

-

­+

FB=H

SCP

OSC x 8200 count

ON/OFF

LOGIC

STB

ON/OFF

Pin No. Pin Name Function

1 RT Oscillation frequency set terminal
2 INV Error AMP input terminal
3 FB Error AMP output terminal
4 GND Ground terminal
5 STB ON/OFF terminal

6 BOOT2
7 HG2

8 SW2 Output side coil connecting terminal

9 LG2
10 PGND Driver part ground terminal
11 LG1
12 SW1 Input side coil connecting terminal
13 HG1

14 BOOT1
15 VREG 5 V internal regulator output terminal

16 VCC Power input terminal

HG1

BOOT1

VREG

PRE

TIMMING

CONTROL

TIMMING

CONTROL

PRE

DRIVER

HG2

DRIVER

VREG

VREG

SW2

VREG

PWM

CONTROL

BOOT2

Fig. 21 Block diagram

PRE

PRE

Technical Note

Output side high-side driver input

terminal

Output side high-side FET gate drive

terminal

Output side low-side FET gate drive

terminal

Input side low-side FET gate drive

terminal

Input side high-side FET gate drive

terminal

Input side high-side driver input

terminal

VBAT

SW1

LG1

DRIVER

PGND

LG2

DRIVER

VOUT

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BD8303MUV

Technical Note

● Description of Blocks

1. VREF
This block generates ERROR AMP reference voltage.
The reference voltage is 1.0 V.

2. VREG

5.0 V output voltage regulator. Used as power supply for IC internal circuit and BOOT pin supply.
Follows power supply voltage when it is 5.0 V or below and also drops output voltage.
For external oscillation preventive capacitor, 1.0 uF is recommended.

3. UVLO
Circuit for preventing low voltage malfunction
Prevents malfunction of the internal circuit at activation of the power supply voltage or at low power supply voltage.
Monitors VREG pin voltage to turn off DC/DC converter output by changing output voltage of HG1, 2 and LG1, 2 pin to L-logic
when VREG voltage is 2.4 V or below, and reset the timer latch of the internal SCP circuit and soft-start circuit.

4. SCP
Timer latch system short-circuit protection circuit
When the INV pin is the set 1.0 V or lower voltage, the internal SCP circuit starts counting.
The internal counter is in synch with OSC; the latch circuit activates after the counter counts about 8200 oscillations to turn off
DC/DC converter output (about 13.6 msec when RT = 51 kΩ).
To reset the latch circuit, turn off the STB pin once. Then, turn it on again or turn on the power suppl y voltage again.

5. OSC
Oscillation circuit to change frequency by external resistance of the RT pin (1 pin).
When RT = 51 kΩ, operation frequency is set at 600 kHz.

6. ERROR AMP
Error amplifier for detecting output signals and output PWM control signals
The internal reference voltage is set at 1.0 V.

7. PWM COMP
Voltage-pulse width converter for controlling output voltage corresponding to input voltage
Comparing the internal SLOPE waveform with the ERROR AMP output voltage, PWM COMP controls the pulse width and
outputs to the driver.
Also controls Max Duty and Min Duty.
Max Duty and Min Duty are set at the primary side and the secondary side of the inductor respectively, which are as follows:

Primary side (SW1) HG1 Max Duty : About 90 %,
HG1 Min Duty : 0 %
Secondary side (SW 2) LG2 Max Duty : About 90 %,
LG2 Min Duty : About 10 %,

8. SOFT START
Circuit for preventing in-rush current at startup by bringing the output voltage of the DC/DC converter into a soft-start
Soft-start time is in synch with the internal OSC, and the output voltage of the DC/DC converter reaches the set voltage after
about 2400 oscillations (About 4 msec when RT = 51 kΩ).

9. Nch DRIVER
CMOS inverter circuit for driving external Nch FET.
Dead time is provided for preventing feedthrough during switching of HG1 = L → LG1 = H, HG2 = L → LG2 = H and LG1 = L →
HG1 = H, LG2 = L → HG2 = H.
The dead time is set at about 100 nsec in the internal circuit.

10. ON/OFF LOGIC
Voltage applied on STB pin (5 pin) to control ON/OFF of IC. Turned ON when a voltage of 2.5 V or higher is applied and turned
OFF when the terminal is open or 0 V is applied.
Incorporates approximately 400 kΩ pull-down resistance.

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Technical Note

● Example of Application Circuit

* Example of application circuit: VCC = 2.7 – 5.5V, Vout = 3.3V, Iout = 100 mA – 2000 mA

43k

7.5k

150p

Insert a filter
as required.

0.1μF

51k

10000p

6.2k

100k

RT
INV
FB
GND

VCC

STB

1μF

RB521CS-30

VREG

BOOT1

BOOT2

HG2

SW1

HG1

LG1

PGND

LG2

SW2

RB521CS-30

0.1μF

RTQ045N03

22μF

RTQ045N03

4.7μH

(TDK SLF10165)

VCC =

2.7 V

RTQ045N03

RTQ045N03

– 5.5 V

VOUT (set at 3.3 V)

47μF

ON/OFF

0.1μF

Fig. 22 Example of application circuit (1)

* Example of application circuit: VCC=2.7 – 14 V, Vout＝5.0 V, Iout＝100 mA – 1500 mA

30k

5.1k
120p

Insert a filter
as required.

0.1μF

51k

4700p

4.7k

120k

RT
INV
FB
GND

VCC

STB

1μF

RB521CS-30

RB521CS-30

VREG

BOOT1

BOOT2

HG2

SW1

HG1

LG1

PGND

LG2

SW2

0.1μF

RTQ045N03

47μF

RTQ045N03

4.7μH

(TDK SLF10165)

VCC =

2.7 V

RTQ045N03

RTQ045N03

–14 V

VOUT (set at 5.0 V)

47μF

ON/OFF

0.1μF

Fig. 23 Example of application circuit (2)

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* Example of application circuit: VCC=4.0 – 14 V, Vout＝8.4 V, Iout＝100 mA – 1500 mA

27k

7.5k

100p

Insert a filter
as required.

0.1μF

100k

4700p

3.9k

200k

RT
INV
FB
GND

VCC

STB

1μF

RB521CS-30

RB521CS-30

VREG

BOOT1

BOOT2

HG2

SW1

HG1

LG1

PGND

LG2

SW2

0.1μF

RSS065N03

47μF

RSS065N03

4.7μH

(TDK SLF10165)

VCC =

4.0V

RSS065N03

RSS065N03

– 14V

ON/OFF

0.1μF

Fig. 24 Example of application circuit (3)

* Example of application circuit:VCC=2.7 – 14 V, Vout＝12 V, Iout＝100 mA – 1500 mA

30k

5.1k

180p

Insert a filter
as required.

0.1μF

27k

1500p

15k

330k

RT
INV
FB
GND

VCC

STB

1μF

RB521CS-30

RB521CS-30

VREG

BOOT1

BOOT2

HG2

SW1

HG1

LG1

PGND

LG2

SW2

0.1μF

RSS065N03

10μF

RSS065N03

10μH

(TDK SLF10165)

VCC =

2.7 V

RSS065N03

RSS065N03

ON/OFF

0.1μF

Fig. 25 Example of application circuit (4)

Technical Note

VOUT (set at 8.4 V)

47μF×2

– 14 V

VOUT12V

47μF

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BD8303MUV

Technical Note

● Selection of parts for applications

(1) Output inductor
A shielded inductor that satisfies the current rating (current value, Ipeak as shown in the drawing below) and has a low DCR
(direct current resistance component) is recommended.
Inductor values affect output ripple current greatly.
Ripple current can be reduced as the coil L value becomes larger and the
switching frequency becomes higher as the equations shown below.

Ipeak =Iout ×(Vout/VIN) /η＋ ∆IL/2 [A] (1)

Fig. 26Ripple current

ΔIL

(Vin-Vout)

⊿IL= × × [A] (in step-down mode) (2)

L

|(Vin-Vout)|

⊿IL= × × [A] ((in step-up/down mode) (3)

L

Vout

Vin

1

f

Vout×2×0.8

(Vin+Vout)

1

f

(Vout-Vin)

⊿IL= × × [A] (in step-up mode) (4)

L

Vin

Vout

1

f

(η: Efficiency, ∆IL: Output ripple current, f: Switching frequency)

As a guide, output ripple current should be set at about 20 to 50% of the maximum output current.

* Current over the coil rating flowing in the coil brings the coil into magnetic saturation, which may lead to lower efficiency or
output oscillation. Select an inductor with an adequate margin so that the peak current does not exceed the rated current of
the coil.

(2) Output capacitor
A ceramic capacitor with low ESR is recommended for output in order to reduce output ripple.
There must be an adequate margin between the maximum rating and output voltage of the capacitor, taking the DC bias
property into consideration.
Output ripple voltage when ceramic capacitor is used is obtained by the following equation.

Vpp=⊿IL× ＋ ⊿IL×R

Vpp = ∆IL × + ∆IL × R

1

2π×f×Co

1

2π×f×Co

[V] ・・・ (5)

ESR

[V] … (5)

ESR

Setting must be performed so that output ripple is within the allowable ripple voltage.

(3) External FET
An external FET which satisfies the following items and has small Ciss (input capacitance), Qg (total gate charge quantity) and
ON resistance should be selected. There must be an adequate margin between the turn OFF time of MOS and the dead time to
prevent through-current.

Drain-source voltage rating: (Output voltage + BodyDiode Vf of MOS or higher)
Gate-source voltage rating: 7.0 V or higher
Drain-source current rating: IPEAK of Output inductor paragraph or higher

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Technical Note

(5) BOOT-SW capacitor
The capacitor between BOOT and SW should be designed so that the gate drive voltage will not be below Vgs necessary for the
FET to use, taking circuit current input to the BOOT pin into consideration. There must be an adequate margin between the
maximum rating and gate drive voltage.

Gate drive voltage
= (VREG voltage) − (Vf of Di) − (Voltage drop by BOOT pin consumption) [V] (6)
Voltage drop by BOOT pin consumption
＝ (Iboot × (1 / fosc) + Qg of external FET) / Cboot [V] (7)

(6) REG-BOOT diode
A Schottky diode which satisfies the following items and has less forward pressure drop (Vf) should be selected.

Average rectified current: There must be an adequate margin against the current consumed by MOSFET switching.
DC inverse voltage: Input voltage or higher

(3) Setting of oscillation frequency
Oscillation frequency can be set using a resistance value connected to the RT pin (1 pin).
Oscillation frequency is set at 600 kHz when RT = 51 kΩ, and frequency is inversely proportional to RT value.
See Fig. 27 for the relationship between RT and frequency.
Soft-start time changes along with oscillation frequency.
See Fig. 28 for the relationship between RT and soft-start time.

10000

100

1000

10

100

Fig. 27 Oscillation frequency – RT pin
resistance

10

SWITCHNG FREQUENCY [kHz]

10 100 1000

RT PIN RESISTANCE [kΩ]

SOFT START TIME [msec]

1

10 100 1000

RT PIN RESISTANCE [kΩ]

Fig. 28 Soft-start time – RT pin resistance

* Note that the above example of frequency setting is just a design target value, and may differ from the actual equipment.

(4) Output voltage setting
The internal reference voltage of the ERROR AMP is 1.0 V. Output voltage should be obtained by referring to Equation (8) of
Fig. 29.

VOUT

R1

R2

INV

ERROR AMP

(R1+R2)

Vo= ×1.0 [V] … (8)

R2

VREF

1.0V

Fig. 29 Setting of feedback resistance

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Technical Note

(9) Determination of external phase compensation

Condition for stable application
The condition for feedback system stability under negative feedback is as follows:

- Phase delay is 135 °or less when gain is 1 (0 dB) (Phase margin is 45° or higher)

Since DC/DC converter application is sampled according to the switching frequency, the GBW of the whole system (frequency
at which gain is 0 dB) must be set to be equal to or lower than 1/5 of the switching frequency.
In summary, target property of applications is as follows:

- Phase delay must be 135°or lower when gain is 1 (0 dB) (Phase margin is 45° or higher).

- The GBW at that time (frequency when gain is 0 dB) must be equal to or lower than 1/5 of the switching frequency.

For this reason, switching frequency must be increased to improve responsiveness.

One of the points to secure stability by phase compensation is to cancel secondary phase delay (-180°) generated by LC
resonance by the secondary phase lead (i.e. put two phase leads).
Since GBW is determined by the phase compensation capacitor attached to the error amplifier, when it is necessary to reduce
GBW, the capacitor should be made larger.

R

C

FB

GAIN
[dB]

A

0

(A)

-20dB/decade

(B)

Error AMP is a low-pass filter because phase compensation such
as (1) and (2) is performed. For DC/DC converter application, R is a
parallel feedback resistance.

Fig.30 General integrator

PHASE
[degree]

Point (A) fp= [Hz] (9)

Point (B) f

0°

-90°

Phase margin

-180°

1

2πRCA

1

= [Hz] (10)

GBW

2πRC

Fig.31 Frequency property of integrator

Phase compensation when output capacitor with low ESR such as ceramic capacitor is used is as follows:

When output capacitor with low ESR (several tens of mΩ) is used for output, secondary phase lead (two phase leads) must be
put to cancel secondary phase lead caused by LC.
One of the examples of phase compensation methods is as follows:

VOUT

R1

C1
R3

R4

C2

R2

Fig.32 Example of setting of phase compensation

Phase lead fz1= [Hz] (11)

Phase lead fz2 = [Hz] (12)

FB

Phase delay fp1 = [Hz] (13)

LC resonance frequency = [Hz] (14)

1

2πR1C1

1

2πR4C2

1

2πR3C1

1

2π√(LC)

For setting of phase-lead frequency, both of them should be put near LC resonance frequency.
When GBW frequency becomes too hjgh due to the secondary phase lead, it may get stabilized by putting the primary phase
delay in a frequency slightly higher than the LC resonance frequency to compensate it.

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BD8303MUV

● Example of Board Layout

Technical Note

Fig.33 Example of Board Layout

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BD8303MUV

● I/O Equivalence Circuit

RT INV

VREG

VREG

RT

GND

FB STB

VREG

VREG

FB

GND

BOOT1,2
HG1,2
SW1,2

BOOT1,2

LG1,2
PGND

VREG

HG1,2

SW1,2

PGND

PGND

Fig.34 I/O equivalence circuit

INV

STB

VREG

GND

VCC

GND

LG1,2

Technical Note

VREG

VCC

VCC
VREG
GND

VCC

VREG

GND

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BD8303MUV

●

Precautions for Use

Technical Note

1) Absolute Maximum Rating
We dedicate much attention to the quality control of these products, however the possibility of deterioration or destruction exists
if the impressed voltage, operating temperature range, etc., exceed the absolute maximum ratings. In addition, it is impossible to
predict all destructive situations such as short-circuit modes, open circuit modes, etc. If a special mode exceeding the absolute
maximum rating is expected, please review matters and provide physical safety means such as fuses, etc.

2) GND Potential
Keep the potential of the GND pin below the minimum potential at all times.

3) Thermal Design
Work out the thermal design with sufficient margin taking power dissipation (Pd) in the actual operation condition into account.

4) Short Circuit between Pins and Incorrect Mounting
Attention to IC direction or displacement is required when installing the IC on a PCB. If the IC is installed in the wrong way, it
may break. Also, the threat of destruction from short-circuits exists if foreign matter invades between outputs or the output and
GND of the power supply.

5) Operation under Strong Electromagnetic Field
Be careful of possible malfunctions under strong electromagnetic fields.

6) Common Impedance
When providing a power supply and GND wirings, show sufficient consideration for lowering common impedance and reducing
ripple (i.e., using thick short wiring, cutting ripple down by LC, etc.) as much as you can.

7) Thermal Protection Circuit (TSD Circuit)
This IC contains a thermal protection circuit (TSD circuit). The TSD circuit serves to shut off the IC from thermal runaway

and does not aim to protect or assure operation of the IC itself. Therefore, do not use the TSD circuit for continuous use or
operation after the circuit has tripped.

8) Rush Current at the Time of Power Activation

Be careful of the power supply coupling capacity and the width of the power supply and GND pattern wiring and routing since
rush current flows instantaneously at the time of power activation in the case of CMOS IC or ICs with multiple power supplies.

) IC Terminal Input

9

This is a monolithic IC and has P+ isolation and a P substrate for element isolation bet ween each element. P-N junctions are
formed and various parasitic elements are configured using these P layers and N layers of the individual elements.
For example, if a resistor and transistor are connected to a terminal as shown on Fig.-8:
○ The P-N junction operates as a parasitic diode when GND > (Terminal A) in the case of a resistor or when GND > (Pin B) in
the case of a transistor (NPN)
○ Also, a parasitic NPN transistor operates using the N layer of another element adjacent to the prev ious diode in the case of
a transistor (NPN) when GND > (Pin B).
The parasitic element consequently rises under the potential relationship because of the IC’s structure. The parasitic element
pulls interference that could cause malfunctions or destruction out of the circuit. Therefore, use caution to avoid the op eration of
parasitic elements caused by applying voltage to an input terminal lower than the GND (P board), etc.

(Pin A)

N

Resistor

N

P Substrate

P

＋

P＋

P

Parasitic Element

Fig.35 Example of simple structure of Bipolar IC

(Pin B)

N

Ｎ

Parasitic Element

Transistor (NPN)

C

＋

P

P Substrate

B

E

～

～

GND

N

P

N

＋

P

N

(Pin A)

～

Parasitic Element

～

GND

GND

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c

○

2009 ROHM Co., Ltd. All rights reserved.

2009.03 - Rev.A

BD8303MUV

(

 Ordering part number

B D 8 3 0 3 M U V - E 2

Part No. Part No.

VQFN016V3030

<Dimension>

1.0MAX

0.08

C0.2

0.1

±

0.4

0.75

S

16

13

3.0 ± 0.1

1PIN MARK

1.4 ± 0.1

0.5

14

5

8

9

12

0.25

+ 0.05

− 0.04

Technical Note

Package

MUV: VQFN016V3030

<Tape and Reel information>

0.1

±

3.0

Tape
Quantity

Direction

S

+ 0.03

− 0.02

(0.22)

0.02

0.1

±

1.4

of feed

Unit:mm)

Embossed carrier tape
3000pcs

E2

(The direction is the 1pin of product is at the upper left when you hold
reel on the left hand and you pull out the tape on the right hand)

1234

1234

Reel

※When you order , please order in times the amount of package quantity.

1234

1pin

Packaging and forming specification

E2: Embossed tape and reel

1234

1234

1234

Direction of feed

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2009 ROHM Co., Ltd. All rights reserved.

2009.03 - Rev.A

Notes

No copying or reproduction of this document, in part or in whole, is permitted without the
consent of ROHM Co.,Ltd.

The content specied herein is subject to change for improvement without notice.

The content specied herein is for the purpose of introducing ROHM's products (hereinaf ter
"Products"). If you wish to use any such Product, please be sure to refer to the specications,
which can be obtained from ROHM upon request.

Examples of application circuits, circuit constants and any other information contained herein
illustrate the standard usage and operations of the Products. The peripheral conditions must
be taken into account when designing circuits for mass production.

Great care was taken in ensuring the accuracy of the information specied in this document.
However, should you incur any damage arising from any inaccuracy or misprint of such
information, ROHM shall bear no responsibility for such damage.

The technical information specied herein is intended only to show the typical functions of and
examples of application circuits for the Products. ROHM does not grant you, explicitly or
implicitly, any license to use or exercise intellectual property or other rights held by ROHM and
other par ties. ROHM shall bear no responsibility whatsoever for any dispute arising from the
use of such technical information.

Notice

The Products specied in this document are intended to be used with general-use electronic
equipment or devices (such as audio visual equipment, ofce-automation equipment, commu­nication devices, electronic appliances and amusement devices).

The Products specied in this document are not designed to be radiation tolerant.

While ROHM always makes ef forts to enhance the quality and reliability of its Products, a
Product may fail or malfunction for a variety of reasons.

Please be sure to implement in your equipment using the Products safety measures to guard
against the possibility of physical injury, re or any other damage caused in the event of the
failure of any Product, such as derating, redundancy, re control and fail-safe designs. ROHM
shall bear no responsibility whatsoever for your use of any Product outside of the prescribed
scope or not in accordance with the instruction manual.

The Products are not designed or manufactured to be used with any equipment, device or
system which requires an extremely high level of reliability the failure or malfunction of which
may result in a direct threat to human life or create a risk of human injur y (such as a medical
instrument, transportation equipment, aerospace machinery, nuclear-reactor controller,
fuel-controller or other safety device). ROHM shall bear no responsibility in any way for use of
any of the Products for the above special purposes. If a Product is intended to be used for any
such special purpose, please contact a ROHM sales representative before purchasing.

If you intend to export or ship overseas any Product or technology specied herein that may
be controlled under the Foreign Exchange and the Foreign Trade Law, you will be required to
obtain a license or permit under the Law.

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© 2009 ROHM Co., Ltd. All rights reserved.

Thank you for your accessing to ROHM product informations.
More detail product informations and catalogs are available, please contact us.

ROHM Customer Support System

http://www.rohm.com/contact/

R0039

A